This commit updates the Geode LX GLCP delay control setup from the v2 way to the...

[coreboot.git] / src / cpu / amd / model_lx / msrinit.c

diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 53c0a851dcba300224d371333c42803c8b1af030..35c9ae4f250938867ecece2e31586925ceaa0ee4 100644 (file)
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -18,13 +18,9 @@
  */
 
 #include <stdlib.h>
+#include "cpu/x86/msr.h"
 
-struct msrinit {
-       u32 msrnum;
-       msr_t msr;
-};
-
-static const struct msrinit msr_table[] =
+static const msrinit_t msr_table[] =
 {
        {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
                                                                   * Rom Properties: Write Serialize, WriteProtect.
@@ -49,7 +45,7 @@ static void msr_init(void)
 {
        int i;
        for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-               wrmsr(msr_table[i].msrnum, msr_table[i].msr);
+               wrmsr(msr_table[i].index, msr_table[i].msr);
 }