initial counter working

[hwmod.git] / src / beh_uart_tx_tb.vhd

diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd
new file mode 100644 (file)
index 0000000..a02ac72
--- /dev/null
+++ b/src/beh_uart_tx_tb.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity beh_uart_tx_tb is
+end entity beh_uart_tx_tb;
+
+architecture sim of beh_uart_tx_tb is
+
+       constant clk_period  : time := 10ns;
+       signal clock : std_logic;
+       signal reset : std_logic;
+       signal done : std_logic;
+       signal newsig : std_logic;
+begin
+       inst : entity work.uart_tx(beh)
+       port map (
+                sys_clk => clock,
+                sys_res => reset,
+                --=> txd,
+                --=> tx_data,
+                tx_new => newsig,
+                tx_done => done
+       );
+
+       stimuli : process
+       begin
+               newsig <= '0';
+               wait for 10ns;
+               --send 'Hallo Welt'
+               newsig <= '1';
+               wait for 1000ns;
+
+               assert false report "Test finished" severity failure;
+       end process stimuli;
+
+       res_gen : process
+       begin
+               reset <= '0';
+               wait for 20ns;
+               reset <= '1';
+               wait for 1000ns;
+       end process res_gen;
+
+       clock_gen : process
+       begin
+               clock <= '0';
+               wait for clk_period/2;
+               clock <= '1';
+               wait for clk_period/2;
+       end process clock_gen;
+
+end sim;