--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_uart_pkg.all;
+
+architecture behav of extension_uart is
+
+signal int_rec,int_rec_nxt : extmod_rec;
+signal w1_st_co, w1_st_co_nxt, w2_wewillsee, w2_wewillsee_nxt, w3_wewillsee, w3_wewillsee_nxt, w4_wewillsee, w4_wewillsee_nxt : gp_register_t;
+signal new_tx_data, tx_busy : std_logic;
+
+begin
+
+
+rs232_tx_inst : rs232_tx
+port map(
+ --System inputs
+ clk,
+ reset,
+
+ --Bus
+ bus_tx,
+
+ --From/to sendlogic
+ new_tx_data,
+ w3_wewillsee(byte_t'range),
+ tx_busy
+);
+
+
+
+
+
+syn : process (clk, reset)
+begin
+ if (reset = RESET_VALUE) then
+ int_rec.sel <= '0';
+ int_rec.wr_en <= '0';
+ int_rec.byte_en <= (others=>'0');
+ int_rec.data <= (others=>'0');
+ int_rec.addr <= (others=>'0');
+
+
+ elsif rising_edge(clk) then
+ int_rec <= int_rec_nxt;
+
+
+ end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg)
+
+begin
+ if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+ int_rec_nxt <= ext_reg;
+ end if;
+end process gwriten;
+
+gread : process (clk,ext_reg)
+
+variable tmp_data : gp_register_t;
+
+begin
+ if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w1_st_co(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "01" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w2_wewillsee(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_wewillsee((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "10" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w3_wewillsee(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_wewillsee((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "11" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w4_wewillsee(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_wewillsee((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when others => null;
+ end case;
+ else
+ data_out <= (others=>'0');
+ end if;
+end process gread;
+
+proc_data : process (clk,int_rec)
+
+variable tmp_data : gp_register_t;
+
+begin
+ case int_rec.addr(1 downto 0) is
+ when "00" =>
+ tmp_data := (others =>'0');
+ if int_rec.byte_en(0) = '1' then
+ tmp_data(byte_t'range) :=int_rec.data(byte_t'range);
+ end if;
+ if int_rec.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if int_rec.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if int_rec.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ w1_st_co_nxt <= tmp_data;
+ when "01" =>
+ tmp_data := (others =>'0');
+ if int_rec.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := int_rec.data(byte_t'range);
+ end if;
+ if int_rec.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if int_rec.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if int_rec.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ w2_wewillsee_nxt <= tmp_data;
+ when "10" =>
+ tmp_data := (others =>'0');
+ if int_rec.byte_en(0) = '1' then
+ tmp_data(byte_t'range) :=int_rec.data(byte_t'range);
+ end if;
+ if int_rec.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if int_rec.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if int_rec.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ w3_wewillsee_nxt <= tmp_data;
+ when "11" =>
+ tmp_data := (others =>'0');
+ if int_rec.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w4_wewillsee(byte_t'range);
+ end if;
+ if int_rec.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if int_rec.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if int_rec.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ w4_wewillsee_nxt <= tmp_data;
+ when others => null;
+ end case;
+end process proc_data;
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+
+
+
+
+
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+
+end behav;
+
projects / calu.git / blobdiff