port(
--System input pins
sys_clk : in std_logic;
- sys_res : in std_logic;
-- result : out gp_register_t;
- jump_result : out instruction_addr_t
-- reg_wr_data : out gp_register_t
-
+ -- uart
+ bus_tx : out std_logic
);
end core_top;
architecture behav of core_top is
+ signal jump_result : instruction_addr_t;
+ signal sys_res : std_logic;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
generic map('0', '1')
port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
+ sys_res <= '1';
-- reg_wr_data <= reg_wr_data_pin;
end behav;