added instruction rom/ram switch, added new data signaling bit in uart.

[calu.git] / cpu / src / common_pkg.vhd

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 43603d29a9638626502ee2c9640678e2f3ed711c..d111b7da6241b9698ef15d7cb092fa51364f44b3 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -25,6 +25,7 @@ package common_pkg is
 
        constant INSTR_ADDR_WIDTH       : INTEGER := 32;
        constant PHYS_INSTR_ADDR_WIDTH  : INTEGER := 11;
+       constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
        constant REG_ADDR_WIDTH         : INTEGER := 4;
        constant DATA_ADDR_WIDTH        : INTEGER := 11;
        constant PHYS_DATA_ADDR_WIDTH   : INTEGER := 32;
@@ -33,6 +34,8 @@ package common_pkg is
        constant COND_WIDTH : INTEGER := 4;
        constant DATA_END_ADDR          : integer := ((2**DATA_ADDR_WIDTH)-1);
 
+       constant ROM_USE : std_logic := '1';
+       constant RAM_USE : std_logic := '0';
        
        subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
        subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);