new testbench

[calu.git] / cpu / sim / testcore1.do

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
new file mode 100644 (file)
index 0000000..e32ebbc
--- /dev/null
+++ b/cpu/sim/testcore1.do
@@ -0,0 +1,110 @@
+vlib work
+vmap work work
+
+vcom -work work ../src/mem_pkg.vhd
+vcom -work work ../src/r_w_ram.vhd
+vcom -work work ../src/r_w_ram_b.vhd
+vcom -work work ../src/r2_w_ram.vhd
+vcom -work work ../src/r2_w_ram_b.vhd
+vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/core_pkg.vhd
+vcom -work work ../src/decoder.vhd
+vcom -work work ../src/decoder_b.vhd
+vcom -work work ../src/fetch_stage.vhd
+vcom -work work ../src/fetch_stage_b.vhd
+vcom -work work ../src/decode_stage.vhd
+vcom -work work ../src/decode_stage_b.vhd
+
+vcom -work work ../src/alu_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/gpm_pkg.vhd
+
+vcom -work work ../src/exec_op.vhd
+vcom -work work ../src/exec_op/add_op_b.vhd
+vcom -work work ../src/exec_op/and_op_b.vhd
+vcom -work work ../src/exec_op/or_op_b.vhd
+vcom -work work ../src/exec_op/xor_op_b.vhd
+vcom -work work ../src/exec_op/shift_op_b.vhd
+
+vcom -work work ../src/alu.vhd
+vcom -work work ../src/alu_b.vhd
+
+vcom -work work ../src/gpm.vhd
+vcom -work work ../src/gpm_b.vhd
+
+vcom -work work ../src/execute_stage.vhd
+vcom -work work ../src/execute_stage_b.vhd
+
+
+vcom -work work ../src/writeback_stage.vhd
+vcom -work work ../src/writeback_stage_b.vhd
+
+vcom -work work ../src/pipeline_tb.vhd
+
+vsim work.pipeline_conf_beh -t ns
+
+add wave  -group system -format logic /pipeline_tb/sys_clk_pin
+add wave  -group system -format logic /pipeline_tb/sys_res_n_pin
+
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
+add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
+add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
+
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_dest_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src1_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src2_addr
+
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_we
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
+
+
+
+
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg1
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg2
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src1
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src2
+
+
+
+
+
+
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.daddr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr1
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr2
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src1
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src2
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_we
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_addr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/regfile_val
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/left_operand
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/right_operand
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_nxt
+
+
+add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw
+add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/reg
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result_addr
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/br_pred
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/write_en
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/address
+
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_we
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
+
+run 5000 ns