#include "biosvar.h" // GET_BDA
#include "vgatables.h" // VGAREG_*
+// TODO
+// * replace direct in/out calls with wrapper functions
+
/****************************************************************
* Attribute control
****************************************************************/
void
-vgahw_screen_disable()
+vgahw_screen_disable(void)
{
inb(VGAREG_ACTL_RESET);
outb(0x00, VGAREG_ACTL_ADDRESS);
}
void
-vgahw_screen_enable()
+vgahw_screen_enable(void)
{
inb(VGAREG_ACTL_RESET);
outb(0x20, VGAREG_ACTL_ADDRESS);
}
u8
-vgahw_get_overscan_border_color()
+vgahw_get_overscan_border_color(void)
{
inb(VGAREG_ACTL_RESET);
outb(0x11, VGAREG_ACTL_ADDRESS);
}
u8
-vgahw_get_pel_mask()
+vgahw_get_pel_mask(void)
{
return inb(VGAREG_PEL_MASK);
}
* Memory control
****************************************************************/
+void
+vgahw_sequ_write(u8 index, u8 value)
+{
+ outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
+}
+
+void
+vgahw_grdc_write(u8 index, u8 value)
+{
+ outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
+}
+
void
vgahw_set_text_block_specifier(u8 spec)
{
}
void
-get_font_access()
+get_font_access(void)
{
outw(0x0100, VGAREG_SEQU_ADDRESS);
outw(0x0402, VGAREG_SEQU_ADDRESS);
}
void
-release_font_access()
+release_font_access(void)
{
outw(0x0100, VGAREG_SEQU_ADDRESS);
outw(0x0302, VGAREG_SEQU_ADDRESS);
****************************************************************/
static u16
-get_crtc()
+get_crtc(void)
{
return GET_BDA(crtc_address);
}
// Get vertical display end
u16
-vgahw_get_vde()
+vgahw_get_vde(void)
{
u16 crtc_addr = get_crtc();
outb(0x12, crtc_addr);
/****************************************************************
- * Misc
+ * Save/Restore/Set state
****************************************************************/
-void
-vgahw_enable_video_addressing(u8 disable)
-{
- u8 v = (disable & 1) ? 0x00 : 0x02;
- u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
- outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
-}
-
-void
-vgahw_init()
-{
- // switch to color mode and enable CPU access 480 lines
- outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
- // more than 64k 3C4/04
- outb(0x04, VGAREG_SEQU_ADDRESS);
- outb(0x02, VGAREG_SEQU_DATA);
-}
-
void
vgahw_save_state(u16 seg, struct saveVideoHardware *info)
{
- u16 crtc_addr = GET_BDA(crtc_address);
+ u16 crtc_addr = get_crtc();
SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
}
+
+void
+vgahw_set_mode(struct vgamode_s *vmode_g)
+{
+ // Reset Attribute Ctl flip-flop
+ inb(VGAREG_ACTL_RESET);
+
+ // Set Attribute Ctl
+ u8 *regs = GET_GLOBAL(vmode_g->actl_regs);
+ u16 i;
+ for (i = 0; i <= 0x13; i++) {
+ outb(i, VGAREG_ACTL_ADDRESS);
+ outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA);
+ }
+ outb(0x14, VGAREG_ACTL_ADDRESS);
+ outb(0x00, VGAREG_ACTL_WRITE_DATA);
+
+ // Set Sequencer Ctl
+ outb(0, VGAREG_SEQU_ADDRESS);
+ outb(0x03, VGAREG_SEQU_DATA);
+ regs = GET_GLOBAL(vmode_g->sequ_regs);
+ for (i = 1; i <= 4; i++) {
+ outb(i, VGAREG_SEQU_ADDRESS);
+ outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA);
+ }
+
+ // Set Grafx Ctl
+ regs = GET_GLOBAL(vmode_g->grdc_regs);
+ for (i = 0; i <= 8; i++) {
+ outb(i, VGAREG_GRDC_ADDRESS);
+ outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA);
+ }
+
+ // Set CRTC address VGA or MDA
+ u8 miscreg = GET_GLOBAL(vmode_g->miscreg);
+ u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
+ if (!(miscreg & 1))
+ crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
+
+ // Disable CRTC write protection
+ outw(0x0011, crtc_addr);
+ // Set CRTC regs
+ regs = GET_GLOBAL(vmode_g->crtc_regs);
+ for (i = 0; i <= 0x18; i++) {
+ outb(i, crtc_addr);
+ outb(GET_GLOBAL(regs[i]), crtc_addr + 1);
+ }
+
+ // Set the misc register
+ outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
+
+ // Enable video
+ outb(0x20, VGAREG_ACTL_ADDRESS);
+ inb(VGAREG_ACTL_RESET);
+}
+
+
+/****************************************************************
+ * Misc
+ ****************************************************************/
+
+void
+vgahw_enable_video_addressing(u8 disable)
+{
+ u8 v = (disable & 1) ? 0x00 : 0x02;
+ u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
+ outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
+}
+
+void
+vgahw_init(void)
+{
+ // switch to color mode and enable CPU access 480 lines
+ outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
+ // more than 64k 3C4/04
+ outb(0x04, VGAREG_SEQU_ADDRESS);
+ outb(0x02, VGAREG_SEQU_DATA);
+}