#include "biosvar.h" // GET_GLOBAL
#include "util.h" // dprintf
#include "bregs.h" // struct bregs
-#include "vbe.h" // struct vbe_info
#include "stdvga.h" // VGAREG_SEQU_ADDRESS
#include "pci.h" // pci_config_readl
#include "pci_regs.h" // PCI_BASE_ADDRESS_0
};
static struct cirrus_mode_s cirrus_modes[] VAR16 = {
- {0x5f,{MM_PACKED,640,480,8},0x00,
+ {0x5f,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
- {0x64,{MM_DIRECT,640,480,16},0xe1,
+ {0x64,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
- {0x66,{MM_DIRECT,640,480,15},0xf0,
+ {0x66,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
- {0x71,{MM_DIRECT,640,480,24},0xe5,
+ {0x71,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
- {0x5c,{MM_PACKED,800,600,8},0x00,
+ {0x5c,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
- {0x65,{MM_DIRECT,800,600,16},0xe1,
+ {0x65,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
- {0x67,{MM_DIRECT,800,600,15},0xf0,
+ {0x67,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
- {0x60,{MM_PACKED,1024,768,8},0x00,
+ {0x60,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
- {0x74,{MM_DIRECT,1024,768,16},0xe1,
+ {0x74,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
- {0x68,{MM_DIRECT,1024,768,15},0xf0,
+ {0x68,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
- {0x78,{MM_DIRECT,800,600,24},0xe5,
+ {0x78,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
- {0x79,{MM_DIRECT,1024,768,24},0xe5,
+ {0x79,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
- {0x6d,{MM_PACKED,1280,1024,8},0x00,
+ {0x6d,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
- {0x69,{MM_DIRECT,1280,1024,15},0xf0,
+ {0x69,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
- {0x75,{MM_DIRECT,1280,1024,16},0xe1,
+ {0x75,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
- {0x7b,{MM_PACKED,1600,1200,8},0x00,
+ {0x7b,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
};
* helper functions
****************************************************************/
+int
+is_cirrus_mode(struct vgamode_s *vmode_g)
+{
+ return (vmode_g >= &cirrus_modes[0].info
+ && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
+}
+
static u16
cirrus_vesamode_to_mode(u16 vesamode)
{
return 0x04 << x;
}
+int
+clext_get_window(struct vgamode_s *vmode_g, int window)
+{
+ return stdvga_grdc_read(window + 9);
+}
+
+int
+clext_set_window(struct vgamode_s *vmode_g, int window, int val)
+{
+ if (val >= 0x100)
+ return -1;
+ stdvga_grdc_write(window + 9, val);
+ return 0;
+}
+
+int
+clext_get_linelength(struct vgamode_s *vmode_g)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
+ u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
+ return (((reg1b & 0x10) << 4) + reg13) * stdvga_bpp_factor(vmode_g) * 2;
+}
+
+int
+clext_set_linelength(struct vgamode_s *vmode_g, int val)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ int factor = stdvga_bpp_factor(vmode_g) * 2;
+ int new_line_offset = DIV_ROUND_UP(val, factor);
+ stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
+ stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
+ return 0;
+}
+
static void
cirrus_enable_16k_granularity(void)
{
cirrus_clear_vram(u16 param)
{
cirrus_enable_16k_granularity();
- u8 count = cirrus_get_memsize() * 4;
+ u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
u8 i;
for (i=0; i<count; i++) {
stdvga_grdc_write(0x09, i);
}
int
-clext_set_mode(int mode, int flags)
+clext_set_mode(struct vgamode_s *vmode_g, int flags)
{
- dprintf(1, "cirrus mode %x\n", mode);
- SET_BDA(vbe_mode, 0);
- struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
- if (table_g) {
- cirrus_switch_mode(table_g);
- if (!(flags & MF_LINEARFB))
- cirrus_enable_16k_granularity();
- if (!(flags & MF_NOCLEARMEM))
- cirrus_clear_vram(0);
- SET_BDA(video_mode, mode);
- SET_BDA(vbe_mode, mode | flags);
- return 0;
+ if (!is_cirrus_mode(vmode_g)) {
+ cirrus_switch_mode(&mode_switchback);
+ dprintf(1, "cirrus mode switch regular\n");
+ return stdvga_set_mode(vmode_g, flags);
}
- cirrus_switch_mode(&mode_switchback);
- dprintf(1, "cirrus mode switch regular\n");
- return stdvga_set_mode(mode, flags);
+ struct cirrus_mode_s *table_g = container_of(
+ vmode_g, struct cirrus_mode_s, info);
+ cirrus_switch_mode(table_g);
+ if (!(flags & MF_LINEARFB))
+ cirrus_enable_16k_granularity();
+ if (!(flags & MF_NOCLEARMEM))
+ cirrus_clear_vram(0);
+ return 0;
}
static int
static void
clext_101285(struct bregs *regs)
{
- regs->al = cirrus_get_memsize();
+ regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
}
static void
return v;
}
-static void
-cirrus_set_line_offset(u16 new_line_offset)
-{
- new_line_offset /= 8;
- u16 crtc_addr = stdvga_get_crtc();
- stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
- stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
-}
-
static u16
cirrus_get_line_offset(void)
{
| ((b4 & 0x80) << 12));
}
-static void
-cirrus_vesa_05h(struct bregs *regs)
-{
- if (regs->bl > 1)
- goto fail;
- if (regs->bh == 0) {
- // set mempage
- if (regs->dx >= 0x100)
- goto fail;
- stdvga_grdc_write(regs->bl + 9, regs->dx);
- } else if (regs->bh == 1) {
- // get mempage
- regs->dx = stdvga_grdc_read(regs->bl + 9);
- } else
- goto fail;
-
- regs->ax = 0x004f;
- return;
-fail:
- regs->ax = 0x014f;
-}
-
-static void
-cirrus_vesa_06h(struct bregs *regs)
-{
- if (regs->bl > 2) {
- regs->ax = 0x0100;
- return;
- }
-
- if (regs->bl == 0x00) {
- cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
- } else if (regs->bl == 0x02) {
- cirrus_set_line_offset(regs->cx);
- }
-
- u32 v = cirrus_get_line_offset();
- regs->cx = v / cirrus_get_bpp_bytes();
- regs->bx = v;
- regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
- regs->ax = 0x004f;
-}
-
static void
cirrus_vesa_07h(struct bregs *regs)
{
cirrus_vesa(struct bregs *regs)
{
switch (regs->al) {
- case 0x05: cirrus_vesa_05h(regs); break;
- case 0x06: cirrus_vesa_06h(regs); break;
case 0x07: cirrus_vesa_07h(regs); break;
case 0x10: cirrus_vesa_10h(regs); break;
default: cirrus_vesa_not_handled(regs); break;
dprintf(1, "cirrus init 2\n");
u32 lfb_addr = 0;
- if (CONFIG_VGA_PCI)
- lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
+ int bdf = GET_GLOBAL(VgaBDF);
+ if (CONFIG_VGA_PCI && bdf >= 0)
+ lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
& PCI_BASE_ADDRESS_MEM_MASK);
SET_VGA(VBE_framebuffer, lfb_addr);
u16 totalmem = cirrus_get_memsize();
projects / seabios.git / blobdiff