-/*
- * pci.c
- *
- * Copyright (C) 2008 Nguyen Anh Quynh <aquynh@gmail.com>
- * Copyright (C) 2002 MandrakeSoft S.A.
- *
- * This file may be distributed under the terms of the GNU GPLv3 license.
- */
-
-#include "acpi.h"
-#include "hardware.h"
-#include "ioport.h"
-#include "pci.h"
-#include "smm.h"
-#include "types.h"
-#include "util.h"
-
-u32 pm_io_base, smb_io_base;
-int pm_sci_int;
-PCIDevice i440_pcidev;
-
-static u32 pci_bios_io_addr = 0xC000;
-static u32 pci_bios_mem_addr = 0xF0000000;
-static u32 pci_bios_bigmem_addr;
-
-/* host irqs corresponding to PCI irqs A-D */
-static u8 pci_irqs[4] = { 11, 9, 11, 9 };
-
-
-static void
-pci_set_io_region_addr(PCIDevice *d, int region_num, u32 addr)
+// PCI config space access functions.
+//
+// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2002 MandrakeSoft S.A.
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "pci.h" // pci_config_writel
+#include "ioport.h" // outl
+#include "util.h" // dprintf
+#include "paravirt.h" // romfile_loadint
+#include "farptr.h" // MAKE_FLATPTR
+#include "pci_regs.h" // PCI_VENDOR_ID
+#include "pci_ids.h" // PCI_CLASS_DISPLAY_VGA
+
+void pci_config_writel(u16 bdf, u32 addr, u32 val)
{
- u16 cmd;
- u32 ofs, old_addr;
-
- if (region_num == PCI_ROM_SLOT)
- ofs = 0x30;
- else
- ofs = 0x10 + region_num * 4;
-
- old_addr = pci_config_readl(d, ofs);
-
- pci_config_writel(d, ofs, addr);
- BX_INFO("region %d: 0x%08x\n", region_num, addr);
-
- /* enable memory mappings */
- cmd = pci_config_readw(d, PCI_COMMAND);
- if (region_num == PCI_ROM_SLOT)
- cmd |= 2;
- else if (old_addr & PCI_ADDRESS_SPACE_IO)
- cmd |= 1;
- else
- cmd |= 2;
- pci_config_writew(d, PCI_COMMAND, cmd);
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ outl(val, PORT_PCI_DATA);
}
-/* return the global irq number corresponding to a given device irq
- pin. We could also use the bus number to have a more precise
- mapping. */
-static int
-pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+void pci_config_writew(u16 bdf, u32 addr, u16 val)
{
- int slot_addend;
-
- slot_addend = (pci_dev->devfn >> 3) - 1;
-
- return (irq_num + slot_addend) & 3;
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ outw(val, PORT_PCI_DATA + (addr & 2));
}
-static int
-find_bios_table_area(void)
+void pci_config_writeb(u16 bdf, u32 addr, u8 val)
{
- unsigned long addr;
-
- for (addr = 0xf0000; addr < 0x100000; addr += 16) {
- if (*(u32 *)addr == 0xaafb4442) {
- bios_table_cur_addr = addr + 8;
- bios_table_end_addr = bios_table_cur_addr + *(u32 *)(addr + 4);
- BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
- bios_table_cur_addr, bios_table_end_addr);
-
- return 0;
- }
- }
-
- return -1;
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ outb(val, PORT_PCI_DATA + (addr & 3));
}
-static void
-bios_shadow_init(PCIDevice *d)
+u32 pci_config_readl(u16 bdf, u32 addr)
{
- int v;
-
- if (find_bios_table_area() < 0)
- return;
-
- /* remap the BIOS to shadow RAM an keep it read/write while we
- are writing tables */
- v = pci_config_readb(d, 0x59);
- v &= 0xcf;
- pci_config_writeb(d, 0x59, v);
- memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
- v |= 0x30;
- pci_config_writeb(d, 0x59, v);
- memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
-
- i440_pcidev = *d;
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ return inl(PORT_PCI_DATA);
}
-void bios_lock_shadow_ram(void)
+u16 pci_config_readw(u16 bdf, u32 addr)
{
- PCIDevice *d = &i440_pcidev;
- int v;
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ return inw(PORT_PCI_DATA + (addr & 2));
+}
- wbinvd();
- v = pci_config_readb(d, 0x59);
- v = (v & 0x0f) | (0x10);
- pci_config_writeb(d, 0x59, v);
+u8 pci_config_readb(u16 bdf, u32 addr)
+{
+ outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD);
+ return inb(PORT_PCI_DATA + (addr & 3));
}
-static void pci_bios_init_bridges(PCIDevice *d)
+void
+pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on)
{
- u16 vendor_id, device_id;
+ u16 val = pci_config_readw(bdf, addr);
+ val = (val & ~off) | on;
+ pci_config_writew(bdf, addr, val);
+}
- vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
- device_id = pci_config_readw(d, PCI_DEVICE_ID);
+// Helper function for foreachbdf() macro - return next device
+int
+pci_next(int bdf, int bus)
+{
+ if (pci_bdf_to_fn(bdf) == 0
+ && (pci_config_readb(bdf, PCI_HEADER_TYPE) & 0x80) == 0)
+ // Last found device wasn't a multi-function device - skip to
+ // the next device.
+ bdf += 8;
+ else
+ bdf += 1;
- if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371SB_0) {
- int i, irq;
- u8 elcr[2];
+ for (;;) {
+ if (pci_bdf_to_bus(bdf) != bus)
+ return -1;
- /* PIIX3 bridge */
- elcr[0] = 0x00;
- elcr[1] = 0x00;
- for (i = 0; i < 4; i++) {
- irq = pci_irqs[i];
- /* set to trigger level */
- elcr[irq >> 3] |= (1 << (irq & 7));
- /* activate irq remapping in PIIX */
- pci_config_writeb(d, 0x60 + i, irq);
- }
+ u16 v = pci_config_readw(bdf, PCI_VENDOR_ID);
+ if (v != 0x0000 && v != 0xffff)
+ // Device is present.
+ return bdf;
- outb(elcr[0], 0x4d0);
- outb(elcr[1], 0x4d1);
- BX_INFO("PIIX3 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
- }
- else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
- /* i440 PCI bridge */
- bios_shadow_init(d);
+ if (pci_bdf_to_fn(bdf) == 0)
+ bdf += 8;
+ else
+ bdf += 1;
}
}
-static void
-pci_bios_init_device(PCIDevice *d)
+struct pci_device *PCIDevices;
+int MaxPCIBus VAR16VISIBLE;
+
+// Check if PCI is available at all
+int
+pci_probe_host(void)
{
- int class;
- u32 *paddr;
- int i, pin, pic_irq, vendor_id, device_id;
+ outl(0x80000000, PORT_PCI_CMD);
+ if (inl(PORT_PCI_CMD) != 0x80000000) {
+ dprintf(1, "Detected non-PCI system\n");
+ return -1;
+ }
+ return 0;
+}
- class = pci_config_readw(d, PCI_CLASS_DEVICE);
- vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
- device_id = pci_config_readw(d, PCI_DEVICE_ID);
- BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
- d->bus, d->devfn, vendor_id, device_id);
- switch(class) {
- case 0x0101:
- if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371SB_1) {
- /* PIIX3 IDE */
- pci_config_writew(d, 0x40, 0x8000); // enable IDE0
- pci_config_writew(d, 0x42, 0x8000); // enable IDE1
- goto default_map;
- } else {
- /* IDE: we map it as in ISA mode */
- pci_set_io_region_addr(d, 0, 0x1f0);
- pci_set_io_region_addr(d, 1, 0x3f4);
- pci_set_io_region_addr(d, 2, 0x170);
- pci_set_io_region_addr(d, 3, 0x374);
- }
- break;
- case 0x0300:
- if (vendor_id != 0x1234)
- goto default_map;
- /* VGA: map frame buffer to default Bochs VBE address */
- pci_set_io_region_addr(d, 0, 0xE0000000);
- break;
- case 0x0800:
- /* PIC */
- if (vendor_id == PCI_VENDOR_ID_IBM) {
- /* IBM */
- if (device_id == 0x0046 || device_id == 0xFFFF) {
- /* MPIC & MPIC2 */
- pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
+// Find all PCI devices and populate PCIDevices linked list.
+void
+pci_probe_devices(void)
+{
+ dprintf(3, "PCI probe\n");
+ struct pci_device *busdevs[256];
+ memset(busdevs, 0, sizeof(busdevs));
+ struct pci_device **pprev = &PCIDevices;
+ int extraroots = romfile_loadint("etc/extra-pci-roots", 0);
+ int bus = -1, lastbus = 0, rootbuses = 0, count=0;
+ while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) {
+ bus++;
+ int bdf;
+ foreachbdf(bdf, bus) {
+ // Create new pci_device struct and add to list.
+ struct pci_device *dev = malloc_tmp(sizeof(*dev));
+ if (!dev) {
+ warn_noalloc();
+ return;
+ }
+ memset(dev, 0, sizeof(*dev));
+ *pprev = dev;
+ pprev = &dev->next;
+ count++;
+
+ // Find parent device.
+ int rootbus;
+ struct pci_device *parent = busdevs[bus];
+ if (!parent) {
+ if (bus != lastbus)
+ rootbuses++;
+ lastbus = bus;
+ rootbus = rootbuses;
+ if (bus > MaxPCIBus)
+ MaxPCIBus = bus;
+ } else {
+ rootbus = parent->rootbus;
}
- }
- break;
- case 0xff00:
- if (vendor_id == PCI_VENDOR_ID_APPLE &&
- (device_id == 0x0017 || device_id == 0x0022)) {
- /* macio bridge */
- pci_set_io_region_addr(d, 0, 0x80800000);
- }
- break;
- default:
- default_map:
- /* default memory mappings */
- for (i = 0; i < PCI_NUM_REGIONS; i++) {
- int ofs;
- u32 val, size ;
- if (i == PCI_ROM_SLOT)
- ofs = 0x30;
- else
- ofs = 0x10 + i * 4;
- pci_config_writel(d, ofs, 0xffffffff);
- val = pci_config_readl(d, ofs);
- if (val != 0) {
- size = (~(val & ~0xf)) + 1;
- if (val & PCI_ADDRESS_SPACE_IO)
- paddr = &pci_bios_io_addr;
- else if (size >= 0x04000000)
- paddr = &pci_bios_bigmem_addr;
- else
- paddr = &pci_bios_mem_addr;
- *paddr = (*paddr + size - 1) & ~(size - 1);
- pci_set_io_region_addr(d, i, *paddr);
- *paddr += size;
+ // Populate pci_device info.
+ dev->bdf = bdf;
+ dev->parent = parent;
+ dev->rootbus = rootbus;
+ u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID);
+ dev->vendor = vendev & 0xffff;
+ dev->device = vendev >> 16;
+ u32 classrev = pci_config_readl(bdf, PCI_CLASS_REVISION);
+ dev->class = classrev >> 16;
+ dev->prog_if = classrev >> 8;
+ dev->revision = classrev & 0xff;
+ dev->header_type = pci_config_readb(bdf, PCI_HEADER_TYPE);
+ u8 v = dev->header_type & 0x7f;
+ if (v == PCI_HEADER_TYPE_BRIDGE || v == PCI_HEADER_TYPE_CARDBUS) {
+ u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
+ dev->secondary_bus = secbus;
+ if (secbus > bus && !busdevs[secbus])
+ busdevs[secbus] = dev;
+ if (secbus > MaxPCIBus)
+ MaxPCIBus = secbus;
}
+ dprintf(4, "PCI device %02x:%02x.%x (vd=%04x:%04x c=%04x)\n"
+ , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
+ , pci_bdf_to_fn(bdf)
+ , dev->vendor, dev->device, dev->class);
}
- break;
}
+ dprintf(1, "Found %d PCI devices (max PCI bus is %02x)\n", count, MaxPCIBus);
+}
- /* map the interrupt */
- pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
- if (pin != 0) {
- pin = pci_slot_get_pirq(d, pin - 1);
- pic_irq = pci_irqs[pin];
- pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
+// Search for a device with the specified vendor and device ids.
+struct pci_device *
+pci_find_device(u16 vendid, u16 devid)
+{
+ struct pci_device *pci;
+ foreachpci(pci) {
+ if (pci->vendor == vendid && pci->device == devid)
+ return pci;
}
+ return NULL;
+}
- if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
- /* PIIX4 Power Management device (for ACPI) */
- pm_io_base = PM_IO_BASE;
- pci_config_writel(d, 0x40, pm_io_base | 1);
- pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
- smb_io_base = SMB_IO_BASE;
- pci_config_writel(d, 0x90, smb_io_base | 1);
- pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
- pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
-#ifdef CONFIG_SMM
- smm_init(d);
-#endif
- acpi_enabled = 1;
+// Search for a device with the specified class id.
+struct pci_device *
+pci_find_class(u16 classid)
+{
+ struct pci_device *pci;
+ foreachpci(pci) {
+ if (pci->class == classid)
+ return pci;
}
+ return NULL;
}
-static void
-pci_for_each_device(void (*init_func)(PCIDevice *d))
+int pci_init_device(const struct pci_device_id *ids
+ , struct pci_device *pci, void *arg)
{
- PCIDevice d1, *d = &d1;
- int bus, devfn;
- u16 vendor_id, device_id;
-
- for (bus = 0; bus < 1; bus++) {
- for (devfn = 0; devfn < 256; devfn++) {
- d->bus = bus;
- d->devfn = devfn;
- vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
- device_id = pci_config_readw(d, PCI_DEVICE_ID);
- if (vendor_id != 0xffff || device_id != 0xffff)
- init_func(d);
+ while (ids->vendid || ids->class_mask) {
+ if ((ids->vendid == PCI_ANY_ID || ids->vendid == pci->vendor) &&
+ (ids->devid == PCI_ANY_ID || ids->devid == pci->device) &&
+ !((ids->class ^ pci->class) & ids->class_mask)) {
+ if (ids->func)
+ ids->func(pci, arg);
+ return 0;
}
+ ids++;
+ }
+ return -1;
+}
+
+struct pci_device *
+pci_find_init_device(const struct pci_device_id *ids, void *arg)
+{
+ struct pci_device *pci;
+ foreachpci(pci) {
+ if (pci_init_device(ids, pci, arg) == 0)
+ return pci;
}
+ return NULL;
}
void
-pci_bios_init(void)
+pci_reboot(void)
+{
+ u8 v = inb(PORT_PCI_REBOOT) & ~6;
+ outb(v|2, PORT_PCI_REBOOT); /* Request hard reset */
+ udelay(50);
+ outb(v|6, PORT_PCI_REBOOT); /* Actually do the reset */
+ udelay(50);
+}
+
+// helper functions to access pci mmio bars from real mode
+
+u32 VISIBLE32FLAT
+pci_readl_32(u32 addr)
+{
+ dprintf(3, "32: pci read : %x\n", addr);
+ return readl((void*)addr);
+}
+
+u32 pci_readl(u32 addr)
{
- pci_bios_bigmem_addr = ram_size;
+ if (MODESEGMENT) {
+ dprintf(3, "16: pci read : %x\n", addr);
+ extern void _cfunc32flat_pci_readl_32(u32 addr);
+ return call32(_cfunc32flat_pci_readl_32, addr, -1);
+ } else {
+ return pci_readl_32(addr);
+ }
+}
- if (pci_bios_bigmem_addr < 0x90000000)
- pci_bios_bigmem_addr = 0x90000000;
+struct reg32 {
+ u32 addr;
+ u32 data;
+};
- pci_for_each_device(pci_bios_init_bridges);
+void VISIBLE32FLAT
+pci_writel_32(struct reg32 *reg32)
+{
+ dprintf(3, "32: pci write: %x, %x (%p)\n", reg32->addr, reg32->data, reg32);
+ writel((void*)(reg32->addr), reg32->data);
+}
- pci_for_each_device(pci_bios_init_device);
+void pci_writel(u32 addr, u32 val)
+{
+ struct reg32 reg32 = { .addr = addr, .data = val };
+ if (MODESEGMENT) {
+ dprintf(3, "16: pci write: %x, %x (%x:%p)\n",
+ reg32.addr, reg32.data, GET_SEG(SS), ®32);
+ void *flatptr = MAKE_FLATPTR(GET_SEG(SS), ®32);
+ extern void _cfunc32flat_pci_writel_32(struct reg32 *reg32);
+ call32(_cfunc32flat_pci_writel_32, (u32)flatptr, -1);
+ } else {
+ pci_writel_32(®32);
+ }
}
projects / seabios.git / blobdiff