From 688e6cf155660cb69e965154c3e22370cb5c9abb Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Mon, 14 Dec 2009 02:33:18 +0100 Subject: [PATCH] some cleanup --- pkernel/start91460.asm | 1198 +--------------------------------------- 1 file changed, 1 insertion(+), 1197 deletions(-) diff --git a/pkernel/start91460.asm b/pkernel/start91460.asm index a687a51..00889a3 100644 --- a/pkernel/start91460.asm +++ b/pkernel/start91460.asm @@ -237,9 +237,6 @@ #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack ; -#set STACK_FILL OFF ; <<< fills the stack area with pattern -#set STACK_PATTERN 0x55AA6699 ; <<< the pattern to write to stack -; ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts. ; In this case, the user stack could be set to a dummy size. If the active stack is ; set to user stack, it is used for the main program but the system stack is @@ -265,30 +262,6 @@ ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM. ; ;========================================================================================= -; 4.5 Low-Level Library Interface -;========================================================================================= -; -#set CLIBINIT OFF ; <<< select ext. libray usage -; -; This option has only to be set, if stream-IO/standard-IO function of the C-libraray -; have to be used (printf(), fopen()...). This also requires low-level functions to be -; defined by the application software. -; For other library functions like (e.g. sprintf()) all this is not necessary. However, -; several functions consume a large amount of stack. -; -;========================================================================================= -; 4.6 C++ start-up -;========================================================================================= -; -#set CPLUSPLUS OFF ; <<< activate if c++ files are used -; -; In the C++ specifications, when external or static objects are used, a constructor -; must be called followed by the main function. Because four-byte pointers to the main -; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from -; the lower address of the four addresses in that section. If using C++ sources, -; activate this function to create the section EXT_CTOR_DTOR. -; -;========================================================================================= ; 4.7 Clock Configuration ;========================================================================================= ;========================================================================================= @@ -378,709 +351,6 @@ ; stoped at this point. ; ;========================================================================================= -; -#set EXTBUS DEFAULT ; <<< Ext. Bus on/off -; -; ON - The ext. bus interface is enabled and is configured as -; set below. -; -; OFF - The ext. bus interface is diabled. The port function -; registers are set to general I/O. The registers of -; ext. bus interface will not be touched by the start-up -; file. -; Be aware, that the device might be conifgured in ext. -; bus mode by default after reset. -; -; DEFAULT - Neither the register nor the respective port function -; registers are touched by the start-up file. -; Be aware, that the device might be conifgured in ext. -; bus mode by default after reset. -; -; -; Note: This feature is not supported by every device. Please check the data sheet. The -; following devices for example do not offer an external bus interface: MB91464A, -; MB91467C, MB91465K, MB91463N, MB91465X. -; -;========================================================================================= -; 4.8.1 Select Chipselect (Only EXTBUS == ON) -;========================================================================================= -; -#set CS0 OFF ; <<< select CS (ON/OFF) -#set CS1 OFF ; <<< select CS (ON/OFF) -#set CS2 OFF ; <<< select CS (ON/OFF) -#set CS3 OFF ; <<< select CS (ON/OFF) -#set CS4 OFF ; <<< select CS (ON/OFF) -#set CS5 OFF ; <<< select CS (ON/OFF) -#set CS6 OFF ; <<< select CS (ON/OFF) -#set CS7 OFF ; <<< select CS (ON/OFF) -#set SDRAM OFF ; <<< select if a SDRAM is connected -; -; -#set ENACSX B'00000000 ; <<< set CS, ENACSX -; |||||||| -; ||||||||__ CS0 bit, enable/disable CS0 (1/0) -; |||||||___ CS1 bit, enable/disable CS1 (1/0) -; ||||||____ CS2 bit, enable/disable CS2 (1/0) -; |||||_____ CS3 bit, enable/disable CS3 (1/0) -; ||||______ CS4 bit, enable/disable CS4 (1/0) -; |||_______ CS5 bit, enable/disable CS5 (1/0) -; ||________ CS6 bit, enable/disable CS6 (1/0) -; |_________ CS7 bit, enable/disable CS7 (1/0) -; -; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and -; CS 1 (external RAM and flash) to off. -; -; Note: Not all Chipselects are supported by the different devices. Please check the -; data sheet. -; -;========================================================================================= -; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON) -;========================================================================================= -; -#set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0 -#set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1 -#set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2 -#set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3 -#set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4 -#set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5 -#set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6 -#set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7 -; -; Configure the starting address of each used Chipselect. Chipselects which are not used -; (not set to ON in "Select Chipselect") need not be set (setting ignored). -; -; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start -; address 0x00080000 set 0x0008. -; -;========================================================================================= -; 4.8.3 Configure Chipselect Area (only EXTBUS == ON) -;========================================================================================= -; -#set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0 -#set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1 -#set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2 -#set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3 -#set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4 -#set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5 -#set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6 -#set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7 -; |||||||||||||||| -; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type -; |||||||||||||||___ TYP1 bit -; ||||||||||||||____ TYP2 bit -; |||||||||||||_____ TYP3 bit -; ||||||||||||______ LEND bit, select little '1' or big endian '0' -; |||||||||||_______ WREN bit, en-/disable (1/0) Write access -; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch -; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX -; ||||||||__________ BST0 bit, BSTx bits select burst size -; |||||||___________ BST1 bit -; ||||||____________ DBW0 bit, DBWx select data bus width -; |||||_____________ DBW1 bit -; ||||______________ ASZ0 bit, ASZx bits select address size of CS -; |||_______________ ASZ1 bit -; ||________________ ASZ2 bit -; |_________________ ASZ3 bit -; -; Bit description: -; -; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS -; 0 0 X X : Normal access (asynchronous SRAM, I/O, -; single/page/busrt-ROM/FLASH) -; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only) -; 0 X X 0 : WAIT insertion by RDY disabled -; 0 X X 1 : WAIT insertion by RDY enabled -; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes -; (WRX is fixed at H-Level) -; 0 X 1 X : The WRX pin is used as write strobe -; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used) -; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used) -; 1 0 1 0 : setting not allowed -; 1 0 1 1 : setting not allowed -; 1 1 0 0 : setting not allowed -; 1 1 0 1 : setting not allowed -; 1 1 1 0 : setting not allowed -; 1 1 1 1 : mask area setting -; -; LEND : select BYTE ordering -; 0 : Big endian -; 1 : Little endian -; -; WREN : enable or disable write access -; 0 : disabled -; 1 : enabled, -; -; PFEN : Enable or disable the pre-fetch -; 0 : disabled -; 1 : enabled, -; -; SREN : Enable or disable the sharing of BRQ and BGRNTX -; 0 : disabled -; 1 : enabled (CSx pin High-Z) -; -; BST1 BST0 : set burst size of chip select area -; 0 0 : 1 burst (single access) -; 0 1 : 2 bursts (Address boundary 1 bit) -; 1 0 : 4 bursts (Address boundary 2 bit) -; 1 1 : 8 bursts (Address boundary 3 bit) -; -; DBW1 DBW0 : Set data bus width -; 0 0 : 8-bit (BYTE access) -; 0 1 : 16-bit (HALF-WORD access) -; 1 0 : 32-bit (WORD access) -; 1 1 : Reserved -; -; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect -; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits) -; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits) -; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits) -; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits) -; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits) -; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits) -; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits) -; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits) -; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits) -; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits) -; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits) -; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits) -; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits) -; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits) -; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits) -; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit) -; -;========================================================================================= -; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON) -;========================================================================================= -; -; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) -; -#set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0 -#set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1 -#set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2 -#set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3 -#set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4 -#set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5 -; |||||||||||||||| -; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle -; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle -; ||||||||||||||____ W02 bit, Address -> CSX Delay selection -; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing -; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle -; |||||||||||_______ W05 bit -; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle -; |||||||||_________ W07 bit selection -; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle -; |||||||___________ W09 bit select (0-15 cycles) -; ||||||____________ W10 bit -; |||||_____________ W11 bit -; ||||______________ W12 bit, W12-W15 First access wait cycle -; |||_______________ W13 bit select (0-15 cycles) -; ||________________ W14 bit -; |_________________ W15 bit -; -; -; SDRAM and FRAM bus interface (ACRx_Type = 100x) -; -#set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6 -#set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7 -; |||||||||||||||| -; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles -; |||||||||||||||___ W01 bit -; ||||||||||||||____ W02 bit, W2-W3 RAS active Time -; |||||||||||||_____ W03 bit -; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle -; |||||||||||_______ W05 bit -; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle -; |||||||||_________ W07 bit -; ||||||||__________ W08 bit, W8-W10 CAS latency -; |||||||___________ W09 bit -; ||||||____________ W10 bit -; |||||_____________ W11 bit, reserved -; ||||______________ W12 bit, W12-W16 RAS-CAS delay -; |||_______________ W13 bit -; ||________________ W14 bit -; |_________________ W15 bit, reserved -; -; -; The bit meaning depends on the configured bus interface type. The bus interface can be -; configured for different memory types. Depending on the memory type, the wait register -; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface -; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also -; possible and for some devices neccessary to configure other two chip selects as SDRAM -; or FRAM interface. In such a case be aware of the bit meanings. -; -; -; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) -; -------------------------------------------------------------- -; -; Bit description: -; -; W00 : RDY/WRX -> CSX hold extension cycle -; 0 : 0 cycle -; 1 : 1 cycle -; -; W01 : CSX -> RDX/WRX setup extention cycle -; 0 : 0 cycle -; 1 : 1 cycle -; -; W02 : Address -> CSX Delay selection -; 0 : no delay selected -; 1 : delay selected -; -; W03 : WR0X to WR3X/WRX outout timing selection -; 0 : MCLK synchronous write output enable (ASX=L) -; 1 : Asynchronous write strobe output (norma operation) -; -; W05 W04 : select Write recovery cycle -; 0 0 : 0 cycle -; 0 1 : 1 cycle -; 1 0 : 2 cycles -; 1 1 : 3 cycles -; -; W07 W06 : Read -> Write idle cycle selection -; 0 0 : 0 cycle -; 0 1 : 1 cycle -; 1 0 : 2 cycles -; 1 1 : 3 cycles -; -; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles) -; 0 0 0 0 : 0 Wait state -; 0 0 0 1 : 1 Auto-wait cycle -; 0 0 1 0 : 2 Auto-wait cycle -; .... -; 1 1 1 1 : 15 Auto wait cycles -; -; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles) -; 0 0 0 0 : 0 Wait state -; 0 0 0 1 : 1 Auto-wait cycle -; 0 0 1 0 : 2 Auto-wait cycle -; .... -; 1 1 1 1 : 15 Auto wait cycles -; -; -; -; SDRAM and FRAM bus interface (ACRx_Type = 100x) -; ----------------------------------------------- -; -; Bit description: -; -; W01 W00 : RAS precharge cycles. -; 0 0 : 1 cycle -; 0 1 : 2 cycles -; 1 0 : 5 cycles -; 1 1 : 6 cycles -; -; W03 W02 : RAS active Time -; 0 0 : 1 cycle -; 0 1 : 2 cycles -; 1 0 : 5 cycles -; 1 1 : 6 cycles -; -; W05 W04 : set Write recovery cycle (1 - 4 cycles) -; 0 0 : Prohibited -; 0 1 : 2 cycles -; 1 0 : 3 cycles -; 1 1 : 4 cycles -; -; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles) -; 0 0 : 1 cycle -; 0 1 : 2 cycles -; 1 0 : 3 cycles -; 1 1 : 4 cycles -; -; W10 W09 W08 : set CAS latency (1 - 8 cycles) -; 0 0 0 : 1 cycle -; 0 0 1 : 2 cycle -; ... -; 1 1 1 : 8 cycle -; -; W11 : RESERVED, ALWAYS WRITE 0 ! -; -; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles) -; 0 0 0 : 1 cycle -; 0 0 1 : 2 cycle -; ... -; 1 1 1 : 8 cycle -; -; W15 : RESERVED, ALWAYS WRITE 0 ! -; - -; The bit meaning depends on the configured bus interface type -; -;========================================================================================= -; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM) -;========================================================================================= -; -#set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA -; |||||||| -; ||||||||__ ABS0 bit, set max. active banks (ABS1,0) -; |||||||___ ABS1 bit -; ||||||____ BANK bit, set number of banks connected to CS -; |||||_____ WBST bit, Write burst enable/disable -; ||||______ PSZ0 bit, Set page size (PSZ2-0) -; |||_______ PSZ1 bit -; ||________ PSZ2 bit -; |_________ reserved, always write 0 -; -; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must -; be setup. -; -; Bit description: -; -; ABS1 ABS0 : Set maximum number of bank, active at same time -; 0 0 : 1 bank -; 0 1 : 2 banks -; 1 0 : 3 banks -; 1 1 : 4 banks -; -; BANK : Set number of connected SDRAM banks -; 0 : 2 banks -; 1 : 4 banks -; -; WBST : Write burst enable -; 0 : Single Write -; 1 : Busrt Write -; -; PSZ2 PSZ1 PS0 : Select page size of connected memory -; 0 0 0 : 8-bit column address = A0 to A7 -; 0 0 1 : 9-bit column address = A0 to A8 -; 0 1 0 : 10-bit column address = A0 to A9 -; 0 1 1 : 11-bit column address = A0 to A9, A11 -; 1 X X : setting disabled -; -; -;========================================================================================= -; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM) -;========================================================================================= -; -#set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR -; |||||||||||||||| -; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0) -; |||||||||||||||___ TRC1 bit -; ||||||||||||||____ TRC2 bit -; |||||||||||||_____ PON bit, set power-on control -; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0) -; |||||||||||_______ RFC1 bit -; ||||||||||________ RFC2 bit -; |||||||||_________ BRST bit, set burst refresh control -; ||||||||__________ RFINT0 bit, set auto refresh interval -; |||||||___________ RFINT1 bit, (RFINT5-0) -; ||||||____________ RFINT2 bit -; |||||_____________ RFINT3 bit -; ||||______________ RFINT4 bit -; |||_______________ RFINT5 bit -; ||________________ RRLD bit, counter refresh strat control -; |_________________ SELF bit, self refresh control -; -; -; This register sets various SDRAM refresh controls. When SDRAM control is not set for -; any area, the setting of this register is meaningless, but do not change the register -; value at initial state. When a read is performed using a read-modify-write -; instruction, 0 always returns from the SELF, RRLD, and PON bits. -; -; Bit description: -; -; -; TRC2 TRC1 TRC0 : Refresh Cycle -; 0 0 0 : 4 -; 0 0 1 : 5 -; 0 1 0 : 6 -; 0 1 1 : 7 -; 1 0 0 : 8 -; 1 0 1 : 9 -; 1 1 0 : 10 -; 1 1 1 : 11 -; -; PON : Power-on control -; 0 : disabled -; 1 : power-on sequence started -; -; RFC2 RFC1 RFC0 : Refresh Count -; 0 0 0 : 256 -; 0 0 1 : 512 -; 0 1 0 : 1024 -; 0 1 1 : 2048 -; 1 0 0 : 4096 -; 1 0 1 : 8192 -; 1 1 0 : Setting disabled -; 1 1 1 : Refresh disabled -; -; BRST : Burst refresh control -; 0 : Decentralised refresh -; 1 : burst refresh -; -; RFINT[5-0] : auto refresh interval -; -; RRLD : Refresh counter Activation Control -; 0 : Disabled, -; 1 : Autorefresh performed once, then value of RFINT reloaded -; -; SELF : Self refresh control -; 0 : auto refresh or power down -; 1 : Transitions to self-refresch mode -; -; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the -; above setting. Otherwise the settings are not correct set. -; -;========================================================================================= -; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON) -;========================================================================================= -; -#set TIMECONTR B'00000000 ; <<< set TCR register, TCR -; |||||||| -; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1) -; |||||||___ RDW1 bit -; ||||||____ OHT0 bit, set output hold delay (OHT1,0) -; |||||_____ OHT1 bit -; ||||______ reserved, always write 0 -; |||_______ PCLR bit, prefetch buffer clear -; ||________ PSUS bit, prefetch suspend -; |_________ BREN bit, BRQ input enable -; -; This register controls the general functions of the external bus interface controller -; such as the common-pin function setting and timing control. -; -; Bit description: -; -; RDW1 RDW0 : Wait cycle reduction -; 0 0 : Normal Wait (AWR0 - 7 setting) -; 0 1 : 1/2 of AWR0 - 7 setting value -; 1 0 : 1/4 of AWR0 - 7 setting value -; 1 1 : 1/8 of AWR0 - 7 setting value -; -; OHT1 OHT0 : Output hold selection bit -; 0 0 : Output performed at falling edge of SYSCLK/MCLK -; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK -; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK -; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK -; -; PCLR : Prefetch buffer all clear -; 0 : normal state -; 1 : Prefetch buffer cleared -; -; PSUS : prefetch suspension bit -; 0 : Prefetch enabled -; 1 : Prefetch disabled -; -; BREN : BRQ input enable -; 0 : disabled, -; 1 : enabled, Bus sharing of BRQ/BGRNTX performed -; -; Note: This function is used to prevent an excessive access cycle wait while operating -; at a low-speed clock (such as while base clock operating at low speed or -; high frequency division rate for external bus clock). -; -;========================================================================================= -; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON) -;========================================================================================= -; -#set C1024 1 ; CACHE Size: 1024 BYTE -#set C2048 2 ; CACHE Size: 2048 BYTE -#set C4096 3 ; CACHE Size: 4096 BYTE -; -; -#set CACHE OFF ; <<< Select use of cache -#set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE -; -; It is possible to use cache functionality on the I-Bus on several devices. Please -; check the corresponidng data sheet if this feature is available on a certain device -; and for the size of the cache. This is the general cache configuration. It is possible -; to configure for each CS area, if the cache should be used. -; -; Note: This feature is not supported by every device. Please check the data sheet. The -; feature is for example supported by MB91461R, MB91469G. -; -;========================================================================================= -; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON) -;========================================================================================= -; -#set CHEENA B'11111111 ; <<< en-/disable cache, CHER -; |||||||| -; ||||||||__ CHE0 bit, CS0 area -; |||||||___ CHE1 bit, CS1 area -; ||||||____ CHE2 bit, CS2 area -; |||||_____ CHE3 bit, CS3 area -; ||||______ CHE4 bit, CS4 area -; |||_______ CHE5 bit, CS5 area -; ||________ CHE6 bit, CS6 area -; |_________ CHE7 bit, CS7 area -; -; Additional to the general cache enable setting, select which CS area should be used -; with cache functionality. -; -; Note: Not all Chipselects are supported by the different devices. Please check the -; data sheet. -; -; Note: This feature is not supported by every device. Please check the data sheet. The -; Feature is supported by MB91461R, MB91469G. -; -;========================================================================================= -; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON) -;========================================================================================= -; -#set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00 -; |||||||| -; ||||||||__ D24 / P00_0 -; |||||||___ D25 / P00_1 -; ||||||____ D26 / P00_2 -; |||||_____ D27 / P00_3 -; ||||______ D28 / P00_4 -; |||_______ D29 / P00_5 -; ||________ D30 / P00_6 -; |_________ D31 / P00_7 -; -#set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01 -; |||||||| -; ||||||||__ D16 / P01_0 -; |||||||___ D17 / P01_1 -; ||||||____ D18 / P01_2 -; |||||_____ D19 / P01_3 -; ||||______ D20 / P01_4 -; |||_______ D21 / P01_5 -; ||________ D22 / P01_6 -; |_________ D23 / P01_7 -; -#set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02 -; |||||||| -; ||||||||__ D8 / P02_0 -; |||||||___ D9 / P02_1 -; ||||||____ D10 / P02_2 -; |||||_____ D11 / P02_3 -; ||||______ D12 / P02_4 -; |||_______ D13 / P02_5 -; ||________ D14 / P02_6 -; |_________ D15 / P02_7 -; -#set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03 -; |||||||| -; ||||||||__ D0 / P03_0 -; |||||||___ D1 / P03_1 -; ||||||____ D2 / P03_2 -; |||||_____ D3 / P03_3 -; ||||______ D4 / P03_4 -; |||_______ D5 / P03_5 -; ||________ D6 / P03_6 -; |_________ D7 / P03_7 -; -; Select if the ports are set to -; 1 : External bus mode, I/O for data lines or -; 0 : General I/O port (GIO) -; -; Note: Not all data-lines are supported by the different devices. Please check the data -; sheet. -; -;========================================================================================= -; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON) -;========================================================================================= -; -#set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04 -; |||||||| -; ||||||||__ A24 / P04_0 -; |||||||___ A25 / P04_1 -; ||||||____ A26 / P04_2 -; |||||_____ A27 / P04_3 -; ||||______ A28 / P04_4 -; |||_______ A29 / P04_5 -; ||________ A30 / P04_6 -; |_________ A31 / P04_7 -; -#set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05 -; |||||||| -; ||||||||__ A16 / P05_0 -; |||||||___ A17 / P05_1 -; ||||||____ A18 / P05_2 -; |||||_____ A19 / P05_3 -; ||||______ A20 / P05_4 -; |||_______ A21 / P05_5 -; ||________ A22 / P05_6 -; |_________ A23 / P05_7 -; -#set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06 -; |||||||| -; ||||||||__ A8 / P06_0 -; |||||||___ A9 / P06_1 -; ||||||____ A10 / P06_2 -; |||||_____ A11 / P06_3 -; ||||______ A12 / P06_4 -; |||_______ A13 / P06_5 -; ||________ A14 / P06_6 -; |_________ A15 / P06_7 -; -#set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07 -; |||||||| -; ||||||||__ A0 / P07_0 -; |||||||___ A1 / P07_1 -; ||||||____ A2 / P07_2 -; |||||_____ A3 / P07_3 -; ||||______ A4 / P07_4 -; |||_______ A5 / P07_5 -; ||________ A6 / P07_6 -; |_________ A7 / P07_7 -; -; Select if the ports are set to -; 1 : External bus mode, I/O for address lines or -; 0 : General I/O port (GIO) -; -; Note: Not all address-lines are supported by the different devices. Please check the -; data sheet. -; -;========================================================================================= -; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON) -;========================================================================================= -; -#set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08 -; |||||||| -; ||||||||__ WRX0 / P08_0 -; |||||||___ WRX1 / P08_1 -; ||||||____ WRX2 / P08_2 -; |||||_____ WRX3 / P08_3 -; ||||______ RDX / P08_4 -; |||_______ BGRNTX / P08_5 -; ||________ BRQ / P08_6 -; |_________ RDY / P08_7 -; -#set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09 -; |||||||| -; ||||||||__ CSX0 / P09_0 -; |||||||___ CSX1 / P09_1 -; ||||||____ CSX2 / P09_2 -; |||||_____ CSX3 / P09_3 -; ||||______ CSX4 / P09_4 -; |||_______ CSX5 / P09_5 -; ||________ CSX6 / P09_6 -; |_________ CSX7 / P09_7 -; -#set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10 -; |||||||| -; ||||||||__ SYSCLK or !SYSCLK / P10_0 -; |||||||___ ASX / P10_1 -; ||||||____ BAAX / P10_2 -; |||||_____ WEX / P10_3 -; ||||______ MCLKO or !MCLKO / P10_4 -; |||_______ MCLKI or !MCLKI/ P10_5 -; ||________ MCLKE / P10_6 -; |_________ - -; -#set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10 -; |||||||| -; ||||||||__ 0:SYSCLK / 1:!SYSCLK -; |||||||___ - -; ||||||____ - -; |||||_____ - -; ||||______ 0:MCLKO / 1:!MCLKO -; |||_______ 0:MCLKI / 1:!MCLKI -; ||________ 0:MCLKI / 1:!MCLKI -; |_________ - -; -; -; Select if the ports are set to -; 1 : External bus mode, I/O for control lines or -; 0 : General I/O port (GIO) -; -; Note: Not all control-lines are supported by the different devices. Please check the -; data sheet. -; -;========================================================================================= ; 5 Definition of Configurations ;========================================================================================= ; @@ -1492,18 +762,6 @@ .import _main .import _RAM_INIT .import _ROM_INIT - -#if CLIBINIT == ON - .export __exit - .import _exit - .import __stream_init -#endif - -#if CPLUSPLUS == ON - .export __abort - .import ___call_dtors - .import _atexit -#endif ;========================================================================================= ; 6.1 Define Stack Size ;========================================================================================= @@ -1554,10 +812,6 @@ #endif #endif -#if CPLUSPLUS == ON - .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors -#endif - ;----------------------------------------------------------------------------------------- ; MACRO Clear RC Watchdog ;----------------------------------------------------------------------------------------- @@ -1977,358 +1231,11 @@ noClockStartup: #if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \ (DEVICE != MB91463N) && (DEVICE != MB91465X) ; End restriction -#if (EXTBUS == ON) -;========================================================================================= -; 7.7.1 Disable all CS -;========================================================================================= -; Start restriction; Flashless device -#if(DEVICE != MB91461R) -; End restriction - LDI #0x0680, R3 ; chip select enable register CSER - LDI #(0x00), R2 ; load disable settings -smd_cs: - ANDB R2, @R3 ; set register -#endif - -;========================================================================================= -; 7.7.2 Clear TCR Register -;========================================================================================= - LDI #0x0683, R1 ; Pin/Timing Control Register TCR - BORH #0x6,@R1 ; load timing settings - -;========================================================================================= -; 7.7.3 Set CS0 -;========================================================================================= -#if CS0 - LDI #0x0640, R1 ; area select reg ASR0, ACR0 - LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings - ST R0, @R1 ; set registers - - LDI #0x660, R1 ; area wait register awr0 - LDI #WAITREG0, R2 ; wait settings - STH R2, @R1 ; set register -#endif - -;========================================================================================= -; 7.7.4 Set CS1 -;========================================================================================= -#if CS1 - LDI #0x0644, R1 ; area select reg ASR1, ACR1 - LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings - ST R0, @R1 ; set registers - - LDI #0x662, R1 ; area wait register awr1 - LDI #WAITREG1, R2 ; wait settings - STH R2, @R1 ; set register -#endif -smd_cs_mb91461r: -;========================================================================================= -; 7.7.5 Set CS2 -;========================================================================================= -#if CS2 - LDI #0x0648, R1 ; area select reg ASR2, ACR2 - LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x664, R1 ; area wait register awr2 - LDI #WAITREG2, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.6 Set CS3 -;========================================================================================= -#if CS3 - LDI #0x064C, R1 ; area select reg ASR3, ACR3 - LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x666, R1 ; area wait register awr3 - LDI #WAITREG3, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.7 Set CS4 -;========================================================================================= -#if CS4 - LDI #0x0650, R1 ; area select reg ASR4, ACR4 - LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x668, R1 ; area wait register awr4 - LDI #WAITREG4, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.8 Set CS5 -;========================================================================================= -#if CS5 - LDI #0x0654, R1 ; area select reg ASR5, ACR5 - LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x66A, R1 ; area wait register awr5 - LDI #WAITREG5, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.9 Set CS6 -;========================================================================================= -#if (CS6) - LDI #0x0658, R1 ; area select reg ASR6, ACR6 - LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x66C, R1 ; area wait register awr6 - LDI #WAITREG6, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.10 Set CS7 -;========================================================================================= -#if CS7 - LDI #0x065C, R1 ; area select reg ASR7, ACR7 - LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings - ST R0, @R1 ; set registers - LDI #0x66E, R1 ; area wait register awr7 - LDI #WAITREG7, R2 ; wait settings - STH R2, @R1 ; set register -#endif -;========================================================================================= -; 7.7.11 Set special SDRAM config register -;========================================================================================= -#if (SDRAM) - LDI #0x670, R1 ; SDRAM memory config register - LDI #MEMCON, R2 ; wait settings - STB R2, @R1 ; set register -#endif - -;========================================================================================= -; 7.7.12 set Port Function Register -;========================================================================================= -;========================================================================================= -; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port -;========================================================================================= - LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) - LDI #PFUNC0, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port -;========================================================================================= - LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) - LDI #PFUNC1, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port -;========================================================================================= - LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) - LDI #PFUNC2, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port -;========================================================================================= - LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) - LDI #PFUNC3, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port -;========================================================================================= - LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) - LDI #PFUNC4, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port -;========================================================================================= - LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) - LDI #PFUNC5, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port -;========================================================================================= - LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) - LDI #PFUNC6, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port -;========================================================================================= - LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) - LDI #PFUNC7, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port -;========================================================================================= - LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) - LDI #PFUNC8, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port -;========================================================================================= - LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) - LDI #PFUNC9, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port -;========================================================================================= - LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) - LDI #PFUNC10, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port -;========================================================================================= - LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10) - LDI #EPFUNC10, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.13 Set TCR Register -;========================================================================================= - LDI #0x0683, R1 ; Pin/Timing Control Register TCR - LDI #TIMECONTR, R0 ; load timing settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.14 Enable CACHE for selected CS -;========================================================================================= - LDI #0x0681, R3 ; chip select enable register CSER - LDI #CHEENA, R2 - ORB R2, @R3 -;========================================================================================= -; 7.7.15 set SDRAM Referesh Control Register -;========================================================================================= -#if (SDRAM) - LDI #0x0684, R1 ; Refresh Control Register RCR - LDI #REFRESH, R0 ; load refresh settings - STH R0, @R1 ; set register - LDI #0x0008, R2 - OR R2, R0 ; Set PON bit to 1 - STH R0, @R1 ; set register -#endif -;========================================================================================= -; 7.7.16 Enable used CS -;========================================================================================= - LDI #0x0680, R3 ; chip select enable register CSER - LDI #ENACSX, R2 -; Start restriction; Flashless device -#if (DEVICE == MB91461R) -; End restriction -emu_sram_cs_mb91461r: - ANDB R2, @R3 ; set register -#else - ORB R2, @R3 -#endif -;========================================================================================= -; 7.7.17 I-cache on/off -;========================================================================================= -; Start restriction; No cache -#if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others) -; End restriction - #if CACHE - #if CACHE_SIZE == C1024 - LDI #0x03C7, R1 ; Cache size register ISIZE - LDI #0x00, R2 - STB R2, @R1 - LDI #0x03E7, R1 ; Cache control reg ICHCR - LDI #0x07, R2 ; Release entry locks, flush and enable - STB R2, @R1 ; cache - #elif CACHE_SIZE == C2048 - LDI #0x03C7, R1 ; Cache size register ISIZE - LDI #0x01, R2 - STB R2, @R1 - LDI #0x03E7, R1 ; Cache control reg ICHCR - LDI #0x07, R2 ; Release entry locks, flush and enable - STB R2, @R1 ; cache - #elif CACHE_SIZE == C4096 - LDI #0x03C7, R1 ; Cache size register ISIZE - LDI #0x02, R2 - STB R2, @R1 - LDI #0x03E7, R1 ; Cache control reg ICHCR - LDI #0x07, R2 ; Release entry locks, flush and enable - STB R2, @R1 ; cache - #else - #error: Wrong Cache size selected! - #endif - #else - LDI #0x03E7, R1 ; Cache control reg ICHCR - LDI #0x06, R2 ; Release entry locks, flush and disable - STB R2, @R1 ; cache - #endif -#endif -#elif (EXTBUS == OFF) -;========================================================================================= -; 7.7.18 set Port Function Register to general as I/O-Port -;========================================================================================= -;========================================================================================= -; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= -; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port -;========================================================================================= - LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10) - LDI #0x00, R0 ; load port settings - STB R0, @R1 ; set register -;========================================================================================= - -#elif (EXTBUS == DEFAULT) NOP smd_cs_mb91461r: emu_sram_cs_mb91461r: smd_cs: -#endif ; #endif (EXTBUS) + #endif ; #endif (excl. devices) ClearRCwatchdog @@ -2350,74 +1257,6 @@ copy_iram_end: ClearRCwatchdog #endif -;========================================================================================= -; 7.9 Fill stacks -;========================================================================================= -#if STACK_FILL == ON - LDI #STACK_PATTERN, R0 - LDI #SSTACK, R1 - LDI #sizeof(SSTACK), R2 - CMP #0, R2 - BEQ:D fill_sstack_end - MOV R2, R13 - LDI #3, R12 - AND R2, R12 - BEQ:D fill_sstack2 - MOV R2, R3 - SUB R12, R3 - LDI #0x3, R4 - SUB R12, R4 - LSL #0x3, R4 - LDI #STACK_PATTERN, R5 - LSR R4, R5 - LDI #0x8, R4 -fill_sstack1: - ADD #-1, R13 - LSR R4, R5 - CMP R3, R13 - BHI:D fill_sstack1 - STB R5, @(R13, R1) - CMP #0, R3 - BEQ:D fill_sstack_end -fill_sstack2: - ADD #-4, R13 - BGT:D fill_sstack2 - ST R0, @(R13, R1) -fill_sstack_end: - - LDI #STACK_PATTERN, R0 - LDI #USTACK, R1 - LDI #sizeof(USTACK), R2 - CMP #0, R2 - BEQ:D fill_ustack_end - MOV R2, R13 - LDI #3, R12 - AND R2, R12 - BEQ:D fill_ustack2 - MOV R2, R3 - SUB R12, R3 - LDI #0x3, R4 - SUB R12, R4 - LSL #0x3, R4 - LDI #STACK_PATTERN, R5 - LSR R4, R5 - LDI #0x8, R4 -fill_ustack1: - ADD #-1, R13 - LSR R4, R5 - CMP R3, R13 - BHI:D fill_ustack1 - STB R5, @(R13, R1) - CMP #0, R3 - BEQ:D fill_ustack_end -fill_ustack2: - ADD #-4, R13 - BGT:D fill_ustack2 - ST R0, @(R13, R1) -fill_ustack_end: - ClearRCwatchdog -#endif - ;========================================================================================= ; Standard C startup ;========================================================================================= @@ -2482,32 +1321,6 @@ copy_rom2: copy_rom_end: ClearRCwatchdog -;========================================================================================= -; 7.12 C library initialization -;========================================================================================= -#if CLIBINIT == ON - CALL32 __stream_init, r12 ; initialise library -#endif -;========================================================================================= -; 7.13 call C++ constructors -;========================================================================================= -#if CPLUSPLUS == ON - LDI #___call_dtors, r4 - CALL32 _atexit, r12 - - LDI #EXT_CTOR_DTOR, r8 - LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9 - CMP r9, r8 - BEQ L1 -L0: - LD @r8, r10 - CALL:D @r10 - ADD #4, r8 - CMP r9, r8 - BC L0 -L1: -#endif - start_main: ;========================================================================================= ; 7.14 call main routine @@ -2516,15 +1329,6 @@ start_main: LDI:8 #0, r4 ; Set the 1st parameter for main to 0. CALL32:d _main, r12 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0. -#if CLIBINIT == ON - CALL32 _exit, r12 - __exit: -#endif - -#if CPLUSPLUS == ON - __abort: -#endif - ;========================================================================================= ; 7.15 Return from main function ;========================================================================================= -- 2.25.1