From 788f5497a625a2bad72948a622e5530afd2b2e21 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Fri, 11 Dec 2009 22:59:40 +0100 Subject: [PATCH] init --- .gitignore | 6 + Flash.c | 328 + Flash.h | 34 + MAIN.c | 198 + Makefile | 93 + RLT.c | 299 + RLT.h | 45 + Start91460.asm | 2532 + changes_to_HWM.txt | 23 + cscope.out | 114105 ++++++++++++++++++++++++++++++++++++++++++ mb91465k.asm | 14 + mb91465k.h | 15323 ++++++ readme.txt | 58 + tags | 543 + uart.c | 129 + vectors.c | 339 + vectors.h | 13 + 17 files changed, 134082 insertions(+) create mode 100644 .gitignore create mode 100644 Flash.c create mode 100644 Flash.h create mode 100644 MAIN.c create mode 100644 Makefile create mode 100644 RLT.c create mode 100644 RLT.h create mode 100644 Start91460.asm create mode 100644 changes_to_HWM.txt create mode 100644 cscope.out create mode 100644 mb91465k.asm create mode 100644 mb91465k.h create mode 100644 readme.txt create mode 100644 tags create mode 100644 uart.c create mode 100644 vectors.c create mode 100644 vectors.h diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ecaf1aa --- /dev/null +++ b/.gitignore @@ -0,0 +1,6 @@ +*.map +*.obj +*.mhx +*.abs +*.swp +.deps/* diff --git a/Flash.c b/Flash.c new file mode 100644 index 0000000..36dbd6b --- /dev/null +++ b/Flash.c @@ -0,0 +1,328 @@ +/*****************************************************************************/ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*****************************************************************************/ + +#include "Flash.h" +#include "mb91465k.h" + +static unsigned int IFlag; + +#pragma section CODE=IRAM,attr=CODE + + +void FLASH_PrepareWriteHalfWordMode() +{ + /* Set FLASH Access Mode via BootROM Routine */ + /* For details refer to the Hardware Manual or Data Sheet */ +#pragma asm + ST RP,@-R15 + STM0 (R4,R5) + STM1 (R12) + LDI #0x01,R4 ; Set FLASH to 16Bit read/write Mode + LDI #0x04,R5 ; Go 4 times through delay loop (64MHz CLKB) + LDI #0xBF60,R12 + CALL @R12 + LDM1 (R12) + LDM0 (R4,R5) + LD @R15+,RP +#pragma endasm + + /* Set the FLASH Interface to Write Timing */ + /* For details refer to the Hardware Manual or Data Sheet */ + /* Setting shown here is for CLKB = 64MHz */ + FMWT_ATD = 1; + FMWT_WEXH = 0; + FMWT_WTC = 8; +} + +void FLASH_PrepareReadMode() +{ + /* Set FLASH Access Mode via BootROM Routine */ + /* For details refer to the Hardware Manual or Data Sheet */ +#pragma asm + ST RP,@-R15 + STM0 (R4,R5) + STM1 (R12) + LDI #0x00,R4 ; Set FLASH to 32Bit read/write Mode + LDI #0x04,R5 ; Go 4 times through delay loop (64MHz CLKB) + LDI #0xBF60,R12 + CALL @R12 + LDM1 (R12) + LDM0 (R4,R5) + LD @R15+,RP +#pragma endasm + + /* Set the FLASH Interface to Read Timing */ + /* For details refer to the Hardware Manual or Data Sheet */ + /* Setting shown here is for CLKB = 64MHz */ + FMWT_ATD = 1; + FMWT_EQ = 3; + FMWT_WTC = 4; +} + + +unsigned char FLASH_SectorErase(unsigned int secadr) +{ + unsigned char flag = 0; + volatile unsigned int value = 0; + + /* Disable Interrupts if necessary */ + IFlag = FLASH_SaveDisableInterruptFlag(); + + /* Set FLASH access mode to 16Bit Write Mode */ + FLASH_PrepareWriteHalfWordMode(); + + secadr |= 0x0003; + + /* Start FLASH Sector Erase Sequence */ + *hseq_1 = 0x00AA; + *hseq_2 = 0x0055; + *hseq_1 = 0x0080; + *hseq_1 = 0x00AA; + *hseq_2 = 0x0055; + *(unsigned short int *)secadr = 0x0030; + + /* Wait for the Auto Algorithm to start */ + while( !( *(unsigned short int *)secadr & SETIMR ) ) + { + /* Feed the Hardware Watchdog */ + HWWD_CL = 0; + + /* Check for Pending Interrupts */ + if( FLASH_CheckPendingInterrupt() ) + { + /* Wait for Sector Erase Suspend */ + FLASH_SuspendSectorErase(secadr); + + /* Set FLASH access mode to 32Bit Read Mode */ + FLASH_PrepareReadMode(); + + /* Restore the original Interrupt Flag */ + FLASH_RestoreInterruptFlag(IFlag); + + /* Keep on checking for pending Interrupts */ + while( FLASH_CheckPendingInterrupt() ) HWWD_CL = 0; + + /* Disable Interrupts if necessary */ + IFlag = FLASH_SaveDisableInterruptFlag(); + + /* Set FLASH access mode to 16Bit Write Mode */ + FLASH_PrepareWriteHalfWordMode(); + + /* Sector Erase Resume */ + FLASH_ResumeSectorErase(secadr); + } + } + + /* Wait for the Auto Algorithm to finish */ + while( flag == 0 ) + { + /* Feed Hardware Watchdog */ + HWWD_CL = 0; + + /* Check for Pending Interrupts */ + if( FLASH_CheckPendingInterrupt() ) + { + /* Sector Erase Suspend */ + FLASH_SuspendSectorErase(secadr); + + /* Set FLASH access mode to 32Bit Read Mode */ + FLASH_PrepareReadMode(); + + /* Restore the original Interrupt Flag */ + FLASH_RestoreInterruptFlag(IFlag); + + /* Keep on checking for pending Interrupts */ + while( FLASH_CheckPendingInterrupt() ) HWWD_CL = 0; + + /* Disable Interrupts if necessary */ + IFlag = FLASH_SaveDisableInterruptFlag(); + + /* Set FLASH access mode to 16Bit Write Mode */ + FLASH_PrepareWriteHalfWordMode(); + + /* Sector Erase Resume */ + FLASH_ResumeSectorErase(secadr); + } + + + /* Check the Hardware Sequence Flags */ + if( ( *(unsigned short int *)secadr /* value */ & DPOLL ) ) + { + flag = 1; + } + if( ( *(unsigned short int *)secadr /* value */ & TLOVER ) ) + { + if( ( *(unsigned short int *)secadr /* value */ & DPOLL ) ) + { + flag = 1; + } + else + { + /* Reset FLASH */ + FLASH_ReadReset(); + + flag = 2; + } + } + } + + + /* Restore the original Interrupt Flag */ + FLASH_RestoreInterruptFlag(IFlag); + + /* Set FLASH access mode to 32Bit Read Mode */ + FLASH_PrepareReadMode(); + + return flag; +} + +unsigned char FLASH_SectorBlankCheck(unsigned int secaddr, unsigned int size) +{ + unsigned int count; + unsigned char empty_flag = 0; + unsigned int addr = secaddr; + + /* Clear FIXE bit to see FLASH memory content instead of fixed reset vector */ + FMCS_FIXE = 0; + + for(count = 0; count < size; count ++) + { + /* Clear Hardware Watchdog */ + HWWD_CL = 0; + if( *(unsigned int *)addr != 0xFFFFFFFF ) empty_flag = 1; + addr += 4; + } + + /* Set FIXE bit to see fixed reset vector */ + FMCS_FIXE = 1; + + if( empty_flag != 0 ) + { + return 2; + } + + return 1; +} + +unsigned char FLASH_WriteHalfWord(unsigned int adr, unsigned short int data) +{ + unsigned char flag = 0; + + /* Disable Interrupts if necessary */ + IFlag = FLASH_SaveDisableInterruptFlag(); + + /* Set FLASH access mode to 16Bit Write Mode */ + FLASH_PrepareWriteHalfWordMode(); + + /* Start Write FLASH Sequence */ + *hseq_1 = 0x00AA; + *hseq_2 = 0x0055; + *hseq_1 = 0x00A0; + *((volatile unsigned short int *)adr) = data; + + /* Wait for the Auto Algorithm to finish */ + while( flag == 0 ) + { + /* Feed Hardware Watchdog */ + HWWD_CL = 0; + + if( ( *(volatile unsigned short int *)adr & DPOLL ) == (data & DPOLL) ) + { + flag = 1; + } + if( ( *(volatile unsigned short int *)adr & TLOVER ) == TLOVER ) + { + if( ( *(volatile unsigned short int *)adr & DPOLL ) == (data & DPOLL) ) + { + flag = 1; + } + else + { + /* Reset FLASH (keep in mind 16Bit access to FLASH) */ + *hseq_1 = 0x00F0; // Keep in Mind (16Bit access) + + flag = 2; + } + } + } + + /* Set FLASH access mode to 32Bit Read Mode */ + FLASH_PrepareReadMode(); + + /* Restore the original Interrupt Flag */ + FLASH_RestoreInterruptFlag(IFlag); + + return flag; +} + + +unsigned char FLASH_ReadReset() +{ + *hseq_1 = 0x00F0; + + return 1; +} + +#pragma asm +_FLASH_SaveDisableInterruptFlag: + STM0 (R0) + MOV PS,R4 + LDI #0x00000010,R0 + AND R0,R4 ; Store Original Flag + ANDCCR #0xFFFFFFEF ; Clear Interrupt Flag + LDM0 (R0) + RET +#pragma endasm + + +#pragma asm +_FLASH_RestoreInterruptFlag: + STM0 (R0) + MOV PS,R0 ; Get current PS + OR R4,R0 ; Set Flag as saved + MOV R0,PS ; Write back PS + LDM0 (R0) + RET +#pragma endasm + + +unsigned char FLASH_SuspendSectorErase(unsigned int secaddr) +{ + /* Write Sector Erase Suspend Command */ + *(volatile unsigned short int *)secaddr = 0x00B0; + + /* Wait for the FLASH macro to suspend sector erase */ + while(!(*(unsigned short int *)secaddr /* value */ & DPOLL) && (*(unsigned short int *)secaddr /* value */ & SETIMR)) + { + HWWD_CL=0; + } + + return 1; +} + +unsigned char FLASH_ResumeSectorErase(unsigned int secaddr) +{ + /* Write the Sector Erase Resume Command */ + *(volatile unsigned short int *)secaddr = 0x0030; + + /* Wait for the FLASH Macro to resume sector erase */ + while((*(unsigned short int *)secaddr /*value */ & DPOLL) && !(*(unsigned short int *)secaddr /*value */ & SETIMR)) + { + HWWD_CL=0; + } + + return 1; +} + +unsigned char FLASH_CheckPendingInterrupt() +{ + /* Poll for Pending Interrupts which are needed here */ + if(TMCSR0_UF) return 1; /* in this sample the only interrupt source supervised is Reload Timer 0 */ + + /* and return 1 when an Interrupt is pending */ + return 0; +} diff --git a/Flash.h b/Flash.h new file mode 100644 index 0000000..75016d2 --- /dev/null +++ b/Flash.h @@ -0,0 +1,34 @@ +/*****************************************************************************/ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*****************************************************************************/ + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#include "MB91465K.H" + +#define hseq_1 ((volatile unsigned short int *)0x000A1557) +#define hseq_2 ((volatile unsigned short int *)0x000A0AAF) + + +#define DPOLL 0x0080 +#define TLOVER 0x0020 +#define SETIMR 0x0008 + +void FLASH_PrepareWriteHalfWordMode(); +void FLASH_PrepareReadMode(); +unsigned char FLASH_WriteHalfWord(unsigned int adr, unsigned short int data); +unsigned char FLASH_SectorErase(unsigned int sec_adr); +unsigned char FLASH_ChipErase(void); +unsigned char FLASH_SectorBlankCheck(unsigned int secaddr, unsigned int size); +unsigned char FLASH_ReadReset(void); +unsigned char FLASH_SuspendSectorErase(unsigned int secaddr); +unsigned char FLASH_ResumeSectorErase(unsigned int secaddr); +unsigned int FLASH_SaveDisableInterruptFlag(void); +void FLASH_RestoreInterruptFlag(unsigned int flag); +unsigned char FLASH_CheckPendingInterrupt(void); + +#endif /* __FLASH_H__ */ diff --git a/MAIN.c b/MAIN.c new file mode 100644 index 0000000..2972877 --- /dev/null +++ b/MAIN.c @@ -0,0 +1,198 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + MAIN.C + - description + - See README.TXT for project description and disclaimer. + + 06.10.06 1.01 UMa changed includes +-------------------------------------------------------------------------*/ + + +/*************************@INCLUDE_START************************/ +#include "mb91465k.h" +#include "vectors.h" +#include "RLT.h" +#include "Flash.h" +/**************************@INCLUDE_END*************************/ + +/*********************@GLOBAL_VARIABLES_START*******************/ +/**********************@GLOBAL_VARIABLES_END********************/ + + +/*******************@FUNCTION_DECLARATION_START*****************/ + +/*********************@FUNCTION_HEADER_START********************* +*@FUNCTION NAME: main() * +* * +*@DESCRIPTION: The main function controls the program flow * +* * +*@PARAMETER: none * +* * +*@RETURN: none * +* * +***********************@FUNCTION_HEADER_END*********************/ + + +void main(void) +{ + unsigned char error = 0; + unsigned char global_error = 0; + unsigned int i; + + /* Enable Clock Monitor */ + CSCFG_MONCKI = 1; + CMCFG = 0x0D; + + __EI(); /* enable interrupts */ + __set_il(31); /* allow all levels */ + InitIrqLevels(); /* init interrupts */ + + PORTEN = 0x3; /* enable I/O Ports */ + /* This feature is not supported by MB91V460A */ + /* For all other devices the I/O Ports must be enabled*/ + + /* Enable LEDs */ + DDR27 = 0xFF; + PDR27 = 0x00; + + /* Initialize Reload Timer Channel 0 */ + RLT_InitializeTimer(0, RLT_RUMMODE_RELOAD, RLT_CLOCKMODE_DIV32, RLT_TRIGGER_SOFTWARE, RLT_OUTOUTMODE_HIGHLEVEL); + RLT_SetReloadValue(0,0x1388); // CLKP/32, 0.01s Interval => 0x1388 counts + RLT_EnableInterrupt(0); + RLT_TriggerTimer(0); + + /* Initialize UART4 */ + InitUart4(); + + /* Output Welcome Message */ + Puts4(" \n\n"); + Puts4("\n\n********** Welcome to FUJITSU FLASH Programming Demo **********\n"); + + /* Do BlankCheck on Sector at 0xA0000 */ + Puts4("Blank Check of FLASH Sector at 0xA0000 ... "); + error = FLASH_SectorBlankCheck(0xA0000, 0x4000); + if( error == 1 ) + { + Puts4("done.\n"); + } + else + { + Puts4("failed.\n"); + } + + /* Show Current Content of 0xA0000 ... 0xA001F */ + i=0; + Puts4("\nCurrent Content of FLASH at 0xA0000 ... 0xA001F:\n"); + while(i < 0x20) + { + Puts4("0x"); Puthex4( *(unsigned char *)(0xA0000 + i), 2); Puts4(" "); + i++; + if( (i % 0x10) == 0 ) Puts4("\n"); + } + Puts4("\n"); + + /* SectorErase of FLASH Memory 0xA0000*/ + Puts4("Sector Erase of 0xA0000 ... "); + error = FLASH_SectorErase(0xA0000); + error = FLASH_SectorErase(0xA0004); + if( error == 1 ) + { + Puts4("done.\n"); + } + else + { + global_error = 1; + Puts4("failed.\n"); + } + + /* Do BlankCheck on Sectors at 0xA0000 */ + Puts4("Blank Check of FLASH Sector at 0xA0000 ... "); + error = FLASH_SectorBlankCheck(0xA0000, 0x4000); + if( error == 1 ) + { + Puts4("done.\n"); + } + else + { + global_error = 1; + Puts4("failed.\n"); + } + + /* Show Current Content of 0xA0000 ... 0xA001F */ + i=0; + Puts4("\nCurrent Content of FLASH at 0xA0000 ... 0xA001F:\n"); + while(i < 0x20) + { + Puts4("0x"); Puthex4( *(unsigned char *)(0xA0000 + i), 2); Puts4(" "); + i++; + if( (i % 0x10) == 0 ) Puts4("\n"); + } + Puts4("\n"); + + /* Write 0x55AA to 0xA0002 */ + Puts4("Write 0x55AA to 0xA0002 ... "); + error = FLASH_WriteHalfWord(0xA0002,0x55AA); + if( error == 1 ) + { + Puts4("done.\n"); + } + else + { + global_error = 1; + Puts4("failed.\n"); + } + + /* Write 0x33CC to 0xA0004 */ + Puts4("Write 0x33CC to 0xA0004 ... "); + error = FLASH_WriteHalfWord(0xA0004,0x33CC); + if( error == 1 ) + { + Puts4("done.\n"); + } + else + { + global_error = 1; + Puts4("failed.\n"); + } + + /* Show Current Content of 0xA0000 ... 0xA001F */ + i=0; + Puts4("\nCurrent Content of FLASH at 0xA0000 ... 0xA001F:\n"); + while(i < 0x20) + { + Puts4("0x"); Puthex4( *(unsigned char *)(0xA0000 + i), 2); Puts4(" "); + i++; + if( (i % 0x10) == 0 ) Puts4("\n"); + } + Puts4("\n"); + + + /* Output Ready Meassage */ + if( global_error != 0 ) + { + Puts4("\n********* FLASH Programming Demo failed **********\n"); + } + else + { + Puts4("\n********* FLASH Programming Demo done **********\n"); + } + + while(1) /* endless loop */ + { + + HWWD_CL = 0; + + /* feed hardware watchdog */ + /* (Only for devices with hardware (R/C based) watchdog) */ + /* The hardware (R/C based) watchdog is started */ + /* automatically after power-up and can not be stopped */ + /* If the hardware watchdog is not cleared frequently */ + /* a reset is generated. */ + } +} + + +/********************@FUNCTION_DECLARATION_END******************/ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..2c0483a --- /dev/null +++ b/Makefile @@ -0,0 +1,93 @@ +# TODO: make upload, remove warnings + +# hinweise: +# wenn folgende meldung kommt +#> "*** F9012D : tool execute is failed (fasm911s)" +# per 'wine regedit' den string "Path" in +#> HKEY_CURRENT_USER/Environment +# setzen, naemlich auf die ausgabe von +#> winepath $FUJDEV/Bin +# natuerlich muss $FUJDEV richtig gesetzt sein! + +ifeq ($(strip $(FUJDEV)),) +$(error "Set FUJDEV in your environment. Ususally this is the Rootpath of the Softune installer. You MUST NOT install it through wine.") +endif + +PREFIX = wine $(FUJDEV)/Bin/ + +CPUT = -cpu MB91F465K#TODO: change to X + +CFLAGS = -w 1 -O 4 -B -K SPEED -K LONGADDRESS +CFLAGS += -K SCHEDULE -K A1 -K SARG -Xdof +CFLAGS += -K EOPT -K LIB -K UNROLL -Xalign +CFLAGS += -c -cwno $(CPUT) + +ASFLAGS = -w 2 -O 0 -linf ON -lsrc ON -lsec ON +ASFLAGS += -lcros OFF -linc ON -lexp OBJ -pl 60 +ASFLAGS += -pw 100 -tab 8 -Xdof -cwno $(CPUT) + +LDFLAGS = -AL 2 +LDFLAGS += -ra D_RAM=0x0002E000/0x0002FFFF #TODO try 2C000 +LDFLAGS += -ra ID_RAM=0x00030000/0x00031FFF +LDFLAGS += -ro ROM_AREA=0x00080000/0x000FFFFF +LDFLAGS += -ro ROM_AREA_2=0x00148000/0x0014FFFF +LDFLAGS += -sc DATA/Data+INIT/Data+SSTACK/Data+USTACK/Data=D_RAM +LDFLAGS += -sc IRAM/Code=ID_RAM +LDFLAGS += -sc CODE+@INIT+@IRAM+CONST=ROM_AREA +LDFLAGS += -sc CODE_START/Code=0x000F4000 +LDFLAGS += -sc INTVECT/Const=0x000FFC00 +LDFLAGS += -check_locate -pl 60 -pw 132 -Xals +LDFLAGS += -Xalr -na -w 1 -Xdof -Xset_rora -cwno -a $(CPUT) + +LIBRFLAGS = -dt s,d,r,a -pl 60 -pw 132 -cwno $(CPUT) + +CONVFLAGS = -cwno -Xdof + +DEFINES = + +TNAME = fuj +TARGET_MHX = $(TNAME).mhx +TARGET = $(TNAME).abs +DEPDIR = .deps + +#add all objects here + +OBJS = vectors.obj Start91460.obj mb91465k.obj MAIN.obj RLT.obj uart.obj Flash.obj + +AS = $(PREFIX)fasm911s +CC = $(PREFIX)fcc911s +LD = $(PREFIX)flnk911s +LIBR = $(PREFIX)flibs +CONV = $(PREFIX)f2ms + +all: $(TARGET_MHX) + +upload: $(TARGET_MHX) + @echo " TODO upload" + +$(TARGET_MHX): $(TARGET) + @echo " MAKEMHX $@" + @$(CONV) $(CONVFLAGS) $< -o $@ + +$(TARGET): $(OBJS) + @echo " LINK $@" + @$(LD) $(LDFLAGS) -o $@ $(OBJS) -m $(TNAME).map + +%.obj: %.c + @echo " COMPILE $<" + @mkdir -p $(DEPDIR) + @echo -n "$@: " > $(DEPDIR)/$<.d + @$(CC) -H $(CPUT) $< | dos2unix | paste -s -d " " >> $(DEPDIR)/$<.d + @$(CC) $(CFLAGS) $(DEFINES) $< -o $@ + +%.obj: %.asm + @echo " ASSEMBLE $<" + @$(AS) $(ASFLAGS) $(DEFINES) $< -o $@ + +.PHONY: clean +clean: + rm -fr $(DEPDIR) + rm -f $(TARGET) $(TARGET_MHX) $(OBJS) *.map + +-include $(DEPDIR)/* + diff --git a/RLT.c b/RLT.c new file mode 100644 index 0000000..8c637ad --- /dev/null +++ b/RLT.c @@ -0,0 +1,299 @@ +/*****************************************************************************/ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*****************************************************************************/ + +#include "RLT.h" + +void RLT_InitializeTimer(unsigned char channel, unsigned char runmode, unsigned char clockmode, unsigned char triggermode, unsigned char outputmode) +{ + unsigned short setvalue = 0x00; + + /* Prepare seting for the TMCSR Register */ + setvalue |= ( (clockmode << 10) | (triggermode << 7) | ((outputmode & 0x01) << 5) | ((runmode & 0x01) << 4) | 0x02 /* CNTE */ ); + + /* Set the corresponding RLT channel */ + switch(channel) + { + case 0: + { + TMCSR0 = setvalue; + break; + } + case 1: + { + TMCSR1 = setvalue; + break; + } + case 2: + { + TMCSR2 = setvalue; + break; + } + case 3: + { + TMCSR3 = setvalue; + break; + } + case 4: + { + TMCSR4 = setvalue; + break; + } + case 5: + { + TMCSR5 = setvalue; + break; + } + case 6: + { + TMCSR6 = setvalue; + break; + } + case 7: + { + TMCSR7 = setvalue; + break; + } + } +} + +void RLT_SetReloadValue(unsigned char channel, unsigned short int value) +{ + switch(channel) + { + case 0: + { + TMRLR0 = value; + break; + } + case 1: + { + TMRLR1 = value; + break; + } + case 2: + { + TMRLR2 = value; + break; + } + case 3: + { + TMRLR3 = value; + break; + } + case 4: + { + TMRLR4 = value; + break; + } + case 5: + { + TMRLR5 = value; + break; + } + case 6: + { + TMRLR6 = value; + break; + } + case 7: + { + TMRLR7 = value; + break; + } + } +} + +void RLT_TriggerTimer(unsigned char channel) +{ + switch(channel) + { + case 0: + { + TMCSR0_TRG = 1; + break; + } + case 1: + { + TMCSR1_TRG = 1; + break; + } + case 2: + { + TMCSR2_TRG = 1; + break; + } + case 3: + { + TMCSR3_TRG = 1; + break; + } + case 4: + { + TMCSR4_TRG = 1; + break; + } + case 5: + { + TMCSR5_TRG = 1; + break; + } + case 6: + { + TMCSR6_TRG = 1; + break; + } + case 7: + { + TMCSR7_TRG = 1; + break; + } + } +} + +void RLT_EnableInterrupt(unsigned char channel) +{ + switch(channel) + { + case 0: + { + /* Clear Pending Interrupt Flag */ + TMCSR0_UF = 0; + + /* Enable Interrupt */ + TMCSR0_INTE = 1; + break; + } + case 1: + { + /* Clear Pending Interrupt Flag */ + TMCSR1_UF = 0; + + /* Enable Interrupt */ + TMCSR1_INTE = 1; + break; + } + case 2: + { + /* Clear Pending Interrupt Flag */ + TMCSR2_UF = 0; + + /* Enable Interrupt */ + TMCSR2_INTE = 1; + break; + } + case 3: + { + /* Clear Pending Interrupt Flag */ + TMCSR3_UF = 0; + + /* Enable Interrupt */ + TMCSR3_INTE = 1; + break; + } + case 4: + { + /* Clear Pending Interrupt Flag */ + TMCSR4_UF = 0; + + /* Enable Interrupt */ + TMCSR4_INTE = 1; + break; + } + case 5: + { + /* Clear Pending Interrupt Flag */ + TMCSR5_UF = 0; + + /* Enable Interrupt */ + TMCSR5_INTE = 1; + break; + } + case 6: + { + /* Clear Pending Interrupt Flag */ + TMCSR6_UF = 0; + + /* Enable Interrupt */ + TMCSR6_INTE = 1; + break; + } + case 7: + { + /* Clear Pending Interrupt Flag */ + TMCSR7_UF = 0; + + /* Enable Interrupt */ + TMCSR7_INTE = 1; + break; + } + } +} + +__interrupt void RLT_Channel0_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR0_UF = 0; + + /* Do what you have to do */ + PDR27++; +} + +__interrupt void RLT_Channel1_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR1_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel2_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR2_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel3_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR3_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel4_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR4_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel5_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR5_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel6_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR6_UF = 0; + + /* Do what you have to do */ +} + +__interrupt void RLT_Channel7_ISR() +{ + /* Clear Pending Interrupt Flag */ + TMCSR7_UF = 0; + + /* Do what you have to do */ +} diff --git a/RLT.h b/RLT.h new file mode 100644 index 0000000..344014d --- /dev/null +++ b/RLT.h @@ -0,0 +1,45 @@ +/*****************************************************************************/ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*****************************************************************************/ + +#ifndef __RLT_H__ +#define __RLT_H__ + +#include "MB91465K.h" + +#define RLT_RUNMODE_ONESHOT 0x00 +#define RLT_RUMMODE_RELOAD 0x01 + +#define RLT_CLOCKMODE_DIV2 0x00 +#define RLT_CLOCKMODE_DIV8 0x01 +#define RLT_CLOCKMODE_DIV32 0x02 +#define RLT_CLOCKMODE_EXT 0x03 +#define RLT_CLOCKMODE_DIV64 0x05 +#define RLT_CLOCKMODE_DIV128 0x06 + +#define RLT_TRIGGER_SOFTWARE 0x00 +#define RLT_TRIGGER_EXT_FALLINGEDGE 0x01 +#define RLT_TRIGGER_EXT_RISINGEDGE 0x02 +#define RLT_TRIGGER_BOTHEDGES 0x03 + +#define RLT_OUTOUTMODE_HIGHLEVEL 0x00 +#define RLT_OUTPUTMODE_LOWLEVEL 0x01 + +void RLT_InitializeTimer(unsigned char channel, unsigned char runmode, unsigned char clockmode, unsigned char triggermode, unsigned char outputmode); +void RLT_SetReloadValue(unsigned char channel, unsigned short int value); +void RLT_EnableInterrupt(unsigned char channel); +void RLT_TriggerTimer(unsigned char channel); + +__interrupt void RLT_Channel0_ISR(); +__interrupt void RLT_Channel1_ISR(); +__interrupt void RLT_Channel2_ISR(); +__interrupt void RLT_Channel3_ISR(); +__interrupt void RLT_Channel4_ISR(); +__interrupt void RLT_Channel5_ISR(); +__interrupt void RLT_Channel6_ISR(); +__interrupt void RLT_Channel7_ISR(); + +#endif /* __RLT_H__ */ diff --git a/Start91460.asm b/Start91460.asm new file mode 100644 index 0000000..453c85a --- /dev/null +++ b/Start91460.asm @@ -0,0 +1,2532 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +;========================================================================================= +; 1 Contents +;========================================================================================= +; 1 Contents +; 2 Disclaimer +; +; 3 History +; +; 4 Settings +; 4.1 Controller device +; 4.2 Boot / flash security +; 4.3 Stack type and stack size +; 4.4 Copy code from flash to I-RAM +; 4.5 C++ start-up +; 4.6 Low-level library interface +; 4.7 Clock Configuration +; 4.7.1 Clock selection +; 4.7.2 Select Clock Modulator +; 4.8 External bus interface +; 4.8.1 Select chipselect +; 4.8.2 Set memory addressing for chipselects +; 4.8.3 Configure chipselect area +; 4.8.4 Set wait cycles for chipselects +; 4.8.5 Configure chipselects SDRAM memory only +; 4.8.6 Referesh control register RCR +; 4.8.7 Terminal and timing control register +; 4.8.8 Enable / disable I-cache +; 4.8.9 Enable CACHE for chipselect +; 4.8.10 Select external bus mode (data lines) +; 4.8.11 Select external bus mode (address lines) +; 4.8.12 Select external bus mode (control signals) +; +; 5 Definitions of Configurations +; +; 6 Section and data declaration +; 6.1 Define stack size +; 6.2 Define sections +; +; 7. S T A R T +; 7.1 Initialise stack pointer and table base register +; 7.2 Check for CSV reset and set CSV +; 7.3 Check clock condition +; 7.4 Restore default settings after reset +; 7.4.1 Disable clock modulator +; 7.4.2 Check if running on sub clock, change to main clock +; 7.4.3 Disable sub clock +; 7.4.4 Check if running on PLL, gear down PLL +; 7.4.5 Disable PLL +; 7.4.6 Set to main clock +; 7.5 Set memory controller +; 7.6 Clock startup +; 7.6.1 Set Voltage Regulator Settings +; 7.6.2 Power on clock modulator - clock modulator part I +; 7.6.3 Set CLKR register w/o clock mode +; 7.6.4 Start PLLs +; 7.6.5 Wait for PLL oscillation stabilisation +; 7.6.6 Set clocks +; 7.6.6.1 Set CPU and peripheral clock +; 7.6.6.2 Set external bus interface clock +; 7.6.6.3 Set CAN clock prescaler +; 7.6.6.4 Switch main clock mode +; 7.6.6.5 Switch sub clock mode +; 7.6.6.6 Switch to PLL mode +; 7.6.7 Enable frequncy modulation - clock modulator part II +; 7.7 Set BusInterface +; 7.7.1 Disable all CS +; 7.7.2 Clear TCR register +; 7.7.3 Set CS0 +; 7.7.4 Set CS1 +; 7.7.5 Set CS2 +; 7.7.6 Set CS3 +; 7.7.7 Set CS4 +; 7.7.8 Set CS5 +; 7.7.9 Set CS6 +; 7.7.10 Set CS7 +; 7.7.11 Set special SDRAM config register +; 7.7.12 set Port function register +; 7.7.13 Set TCR register +; 7.7.14 Enable cache for selected CS +; 7.7.15 Set SDRAM referesh control register +; 7.7.16 Enable used CS +; 7.7.17 I-cache on/off +; 7.7.18 Set port function register to general as I/O-port +; 7.8 Copy code from flash to I-RAM +; 7.9 Fill stacks +; 7.10 Clear data +; 7.11 Copy Init section from ROM to RAM +; 7.12 C library initialization +; 7.13 Call C++ constructors +; 7.14 Call main routine +; 7.15 Return from main function +; +;========================================================================================= +; 2 Disclaimer +;========================================================================================= +; Fujitsu Microelectronics Europe GmbH +; http://emea.fujitsu.com/microelectronics +; +; The following software is for demonstration purposes only. It is not fully +; tested, nor validated in order to fullfill its task under all circumstances. +; Therefore, this software or any part of it must only be used in an evaluation +; laboratory environment. +; This software is subject to the rules of our standard DISCLAIMER, that is +; delivered with our SW-tools on the Fujitsu Microcontrollers CD/DVD (V3.4 or +; higher "\START.HTM") or on our Internet Pages: +; http://www.fme.gsdc.de/gsdc.htm +; http://emea.fujitsu.com/microelectronics +; +;========================================================================================= +; 3 History +;========================================================================================= +; +;========================================================================================= +; MB914xx (FR60 CORE ONLY) Series C Compiler's +; +; Startup file for memory and basic controller initialisation +;========================================================================================= +;History: +; +; 2005-04-18 V1.0 UMa Release first version +; 2005-06-17 V1.1 UMa Added bus interface, modified c++ startup +; 2005-06-28 V1.2 UMa minor changes +; 2005-07-27 V1.3 UMa default values changed +; 2005-10-04 V1.4 UMa changed code 'Call main Routine' +; Added secutiy section for MB91F467D +; Added Flash Access Read Timing setting section; +; 2005-10-04 V1.5 UMa Added Flash Controller Section +; 2005-10-28 V1.6 UMa Check for CSV reset +; 2005-11.16 V1.7 UMa Monitor Debugger support added: Copy of intvect Table +; Ext. Int 0 as abort function +; Changed PLL-Startup, Reset HWWD added +; 2005-11-16 V1.7 UMa Examples for MUL_G changed +; 2006-02-14 V1.8 UMa mb91464a added +; Settings for Clock Spervisor added +; Name of Section SECURITY changed to SECURITY_VECTORS +; Example values for gear-up changed +; 2006-03-17 V1.9 UMa Changed Startup for Monitor Debugger +; 2006-04-24 v2.0 UMa Added MB91465K and MB91469G +; 2006-05-03 v2.1 UMa Added MB91461R; removed MB91V460A +; Added settings for the external bus-interface +; 2006-07-28 v2.2 UMa Added I-RAM copy function (ROM -> IRAM) +; Added default settings for FLASH Access Read Timing +; Settings +; Changed default settings for FLASH cache configuration +; Register +; Changed check for clock startup +; 2006-08-16 v2.3 MVo Corrected Boot Security Sector Addresses for MB91469G +; 2006-10-06 v2.4 UMa Added new devices +; Corrected typo in I_RAM to flash copy function +; Changed default settings for flash cache configuration +; Changed comments for SDRAM bus interface configuration +; Changed comments and default setting of CAN Prescaler +; Added Stack filler +; Added Settings for REGSEL Register +; 2007-02-13 v2.5 UMa Introduction of default configurations +; Changed I_RAM to flash copy function +; +; +;========================================================================================= +; 4 Settings +;========================================================================================= +; +; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION; +; +; Configure this startup file in the "Settings" section. Search for +; comments with leading "; <<<". This points to the items to be set. +;========================================================================================= +; +#set OFF 0 +#set ON 1 +#set DEFAULT 2 +#set LOW_PRIOR 31 +; +;========================================================================================= +; 4.1 Controller Device +;========================================================================================= +#set MB91464A 2 ; MB91460 series +; +#set MB91467B 10 ; MB91460 series +; +#set MB91467C 11 ; MB91460 series +; +#set MB91467D 4 ; MB91460 series +; +#set MB91469G 6 ; MB91460 series +; +#set MB91465K 3 ; MB91460 series +; +#set MB91463N 8 ; MB91460 series +; +#set MB91461R 1 ; MB91460 series +#set MB91467R 5 ; MB91460 series +; +#set MB91465X 9 ; MB91460 series +; +#set others 7 ; MB91460 series +; +; +; +#set DEVICE MB91465K ; <<< select device +; +;========================================================================================= +; 4.2 Boot / Flash Security +;========================================================================================= +; +#set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector +; +; The flash devices have two flash and two boot security vectors. It is important to set +; the four vectors correctly. Otherwise it might be possible, that the flash device is +; not accessible any more via the bootrom. Please read carefully the hardware manual. +; +; OFF: The security feature is switch off. The section SECURITY_VECTORS is reserved and +; the vectors are set. +; ON: IMPORTANT! The security vectors are not set. But the section SECURITY_VECTORS +; is reserved. +; +; Note: This feature is not supported by every device. Please check the data sheet. This +; feature is not available on MB91461R. +; +;========================================================================================= +; 4.3 Stack Type and Stack Size +;========================================================================================= +; +#set USRSTACK 0 ; user stack: for main program +#set SYSSTACK 1 ; system stack: for main program and +; ; interrupts +; +; +#set STACKUSE SYSSTACK ; <<< set active stack +; +#set STACK_RESERVE ON ; <<< reserve stack area in +; ; this module +#set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack +#set STACK_USR_SIZE 0x2 ; <<< byte size of User stack +; +#set STACK_FILL OFF ; <<< fills the stack area with pattern +#set STACK_PATTERN 0x55AA6699 ; <<< the pattern to write to stack +; +; - If the active stack is set to SYSSTACK, it is used for main program and interrupts. +; In this case, the user stack could be set to a dummy size. If the active stack is +; set to user stack, it is used for the main program but the system stack is +; automatically activated, if an interrupt is serviced. Both stack areas must have a +; reasonable size. +; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module. +; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the +; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning. +; - Even if they are reverved in other modules, they are still initialised in this +; start-up file. +; +; Note: Several library functions require quite a big stack (due to ANSI). +; Check the stack information files (*.stk) in the LIB\911 directory. +; +;========================================================================================= +; 4.4 Copy code from Flash to I-RAM +;========================================================================================= +; +#set I_RAM ON ; <<< select if code in section IRAM +; should be copied +; +; If this option is activated code located in the section IRAM is copied during startup +; from ROM to the instruction-RAM. The code is linked for the instruction-RAM. +; +;========================================================================================= +; 4.5 Low-Level Library Interface +;========================================================================================= +; +#set CLIBINIT OFF ; <<< select ext. libray usage +; +; This option has only to be set, if stream-IO/standard-IO function of the C-libraray +; have to be used (printf(), fopen()...). This also requires low-level functions to be +; defined by the application software. +; For other library functions like (e.g. sprintf()) all this is not necessary. However, +; several functions consume a large amount of stack. +; +;========================================================================================= +; 4.6 C++ start-up +;========================================================================================= +; +#set CPLUSPLUS OFF ; <<< activate if c++ files are used +; +; In the C++ specifications, when external or static objects are used, a constructor +; must be called followed by the main function. Because four-byte pointers to the main +; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from +; the lower address of the four addresses in that section. If using C++ sources, +; activate this function to create the section EXT_CTOR_DTOR. +; +;========================================================================================= +; 4.7 Clock Configuration +;========================================================================================= +;========================================================================================= +; 4.7.1 Clock Selection +;========================================================================================= +; +; No clock settings +#set NO_CLOCK 0x01 +; +; Sub-oscillation input: 32 kHz +#set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11 +; +; Oscillation input: 4 MHz +#set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21 +#set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ 0x22 +#set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23 +#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ 0x24 +#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ 0x25 +#set PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ 0x26 ;not MB91V460, ... +#set PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ 0x27 ;not MB91V460, ... +; +; MB91461R only: Oscillation input: 10 MHz +#set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41 +; +; MB91461R only: Oscillation input: 20 MHz +#set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51 +; +; User settings +#set CLOCK_USER 0x61 +; +; +; +#set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ +; ; <<< Select clock configuration +; +; There are different default configurations available, where all necessary settings for +; clocks and the related registers are made. Beside this configurations, there is the +; possibility to define a user configuration in the chapter "Definition of +; Configurations" +; +; - NO_CLOCK means: +; The clock registers are not set by the start-up file. +; +; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means: +; Main oszillation = 4 MHz, PLL is activated +; CPU clock (CLKB) = 64 MHZ +; Peripheral clock (CLKP) = 16 MHZ +; Ext. bus clock (CLKT) = 32 MHZ +; CAN clock (CLKCAN) = 16 MHz, using PLLx +; +; - CLOCK_USER: +; The user configuration definded in the chapter "Definition of Configurations" is set. +; +; Note: Not all frequencies are supported by every device. Please see the hardware +; manual. +; +;========================================================================================= +; 4.7.2 Select Clock Modulator +;========================================================================================= +; +#set CLOMO OFF ; <<< Enable /disable clock modulator +; +#set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR +; +; Please refer to the data sheet of the device if you enable clock modulation. The +; register CMPR dependant on the PLL-Clock. +; +; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the +; clock for the CAN is not influenced by the clock modulation. If the CLKCAN +; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if +; the clock modulator is enabled). +; +; Note: If the clock modulator is enabled, the wait states of the internal flash wait +; states must be adapted to maximum frequency. Please check the wait states +; settings. +; +; Note: This feature is not supported by every device, e.g. MB91461. Please check the +; data sheet. +; +;========================================================================================= +; 4.8 External Bus Interface +; +; The rest of the configuration is only applicable for devices with an external bus +; interface. +; +; If the device does not offer an external bus interface, the configuration can be +; stoped at this point. +; +;========================================================================================= +; +#set EXTBUS DEFAULT ; <<< Ext. Bus on/off +; +; ON - The ext. bus interface is enabled and is configured as +; set below. +; +; OFF - The ext. bus interface is diabled. The port function +; registers are set to general I/O. The registers of +; ext. bus interface will not be touched by the start-up +; file. +; Be aware, that the device might be conifgured in ext. +; bus mode by default after reset. +; +; DEFAULT - Neither the register nor the respective port function +; registers are touched by the start-up file. +; Be aware, that the device might be conifgured in ext. +; bus mode by default after reset. +; +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; following devices for example do not offer an external bus interface: MB91464A, +; MB91467C, MB91465K, MB91463N, MB91465X. +; +;========================================================================================= +; 4.8.1 Select Chipselect (Only EXTBUS == ON) +;========================================================================================= +; +#set CS0 OFF ; <<< select CS (ON/OFF) +#set CS1 OFF ; <<< select CS (ON/OFF) +#set CS2 OFF ; <<< select CS (ON/OFF) +#set CS3 OFF ; <<< select CS (ON/OFF) +#set CS4 OFF ; <<< select CS (ON/OFF) +#set CS5 OFF ; <<< select CS (ON/OFF) +#set CS6 OFF ; <<< select CS (ON/OFF) +#set CS7 OFF ; <<< select CS (ON/OFF) +#set SDRAM OFF ; <<< select if a SDRAM is connected +; +; +#set ENACSX B'00000000 ; <<< set CS, ENACSX +; |||||||| +; ||||||||__ CS0 bit, enable/disable CS0 (1/0) +; |||||||___ CS1 bit, enable/disable CS1 (1/0) +; ||||||____ CS2 bit, enable/disable CS2 (1/0) +; |||||_____ CS3 bit, enable/disable CS3 (1/0) +; ||||______ CS4 bit, enable/disable CS4 (1/0) +; |||_______ CS5 bit, enable/disable CS5 (1/0) +; ||________ CS6 bit, enable/disable CS6 (1/0) +; |_________ CS7 bit, enable/disable CS7 (1/0) +; +; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and +; CS 1 (external RAM and flash) to off. +; +; Note: Not all Chipselects are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON) +;========================================================================================= +; +#set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0 +#set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1 +#set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2 +#set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3 +#set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4 +#set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5 +#set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6 +#set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7 +; +; Configure the starting address of each used Chipselect. Chipselects which are not used +; (not set to ON in "Select Chipselect") need not be set (setting ignored). +; +; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start +; address 0x00080000 set 0x0008. +; +;========================================================================================= +; 4.8.3 Configure Chipselect Area (only EXTBUS == ON) +;========================================================================================= +; +#set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0 +#set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1 +#set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2 +#set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3 +#set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4 +#set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5 +#set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6 +#set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7 +; |||||||||||||||| +; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type +; |||||||||||||||___ TYP1 bit +; ||||||||||||||____ TYP2 bit +; |||||||||||||_____ TYP3 bit +; ||||||||||||______ LEND bit, select little '1' or big endian '0' +; |||||||||||_______ WREN bit, en-/disable (1/0) Write access +; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch +; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX +; ||||||||__________ BST0 bit, BSTx bits select burst size +; |||||||___________ BST1 bit +; ||||||____________ DBW0 bit, DBWx select data bus width +; |||||_____________ DBW1 bit +; ||||______________ ASZ0 bit, ASZx bits select address size of CS +; |||_______________ ASZ1 bit +; ||________________ ASZ2 bit +; |_________________ ASZ3 bit +; +; Bit description: +; +; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS +; 0 0 X X : Normal access (asynchronous SRAM, I/O, +; single/page/busrt-ROM/FLASH) +; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only) +; 0 X X 0 : WAIT insertion by RDY disabled +; 0 X X 1 : WAIT insertion by RDY enabled +; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes +; (WRX is fixed at H-Level) +; 0 X 1 X : The WRX pin is used as write strobe +; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used) +; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used) +; 1 0 1 0 : setting not allowed +; 1 0 1 1 : setting not allowed +; 1 1 0 0 : setting not allowed +; 1 1 0 1 : setting not allowed +; 1 1 1 0 : setting not allowed +; 1 1 1 1 : mask area setting +; +; LEND : select BYTE ordering +; 0 : Big endian +; 1 : Little endian +; +; WREN : enable or disable write access +; 0 : disabled +; 1 : enabled, +; +; PFEN : Enable or disable the pre-fetch +; 0 : disabled +; 1 : enabled, +; +; SREN : Enable or disable the sharing of BRQ and BGRNTX +; 0 : disabled +; 1 : enabled (CSx pin High-Z) +; +; BST1 BST0 : set burst size of chip select area +; 0 0 : 1 burst (single access) +; 0 1 : 2 bursts (Address boundary 1 bit) +; 1 0 : 4 bursts (Address boundary 2 bit) +; 1 1 : 8 bursts (Address boundary 3 bit) +; +; DBW1 DBW0 : Set data bus width +; 0 0 : 8-bit (BYTE access) +; 0 1 : 16-bit (HALF-WORD access) +; 1 0 : 32-bit (WORD access) +; 1 1 : Reserved +; +; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect +; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits) +; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits) +; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits) +; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits) +; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits) +; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits) +; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits) +; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits) +; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits) +; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits) +; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits) +; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits) +; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits) +; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits) +; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits) +; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit) +; +;========================================================================================= +; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON) +;========================================================================================= +; +; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) +; +#set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0 +#set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1 +#set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2 +#set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3 +#set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4 +#set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5 +; |||||||||||||||| +; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle +; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle +; ||||||||||||||____ W02 bit, Address -> CSX Delay selection +; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing +; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle +; |||||||||||_______ W05 bit +; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle +; |||||||||_________ W07 bit selection +; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle +; |||||||___________ W09 bit select (0-15 cycles) +; ||||||____________ W10 bit +; |||||_____________ W11 bit +; ||||______________ W12 bit, W12-W15 First access wait cycle +; |||_______________ W13 bit select (0-15 cycles) +; ||________________ W14 bit +; |_________________ W15 bit +; +; +; SDRAM and FRAM bus interface (ACRx_Type = 100x) +; +#set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6 +#set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7 +; |||||||||||||||| +; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles +; |||||||||||||||___ W01 bit +; ||||||||||||||____ W02 bit, W2-W3 RAS active Time +; |||||||||||||_____ W03 bit +; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle +; |||||||||||_______ W05 bit +; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle +; |||||||||_________ W07 bit +; ||||||||__________ W08 bit, W8-W10 CAS latency +; |||||||___________ W09 bit +; ||||||____________ W10 bit +; |||||_____________ W11 bit, reserved +; ||||______________ W12 bit, W12-W16 RAS-CAS delay +; |||_______________ W13 bit +; ||________________ W14 bit +; |_________________ W15 bit, reserved +; +; +; The bit meaning depends on the configured bus interface type. The bus interface can be +; configured for different memory types. Depending on the memory type, the wait register +; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface +; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also +; possible and for some devices neccessary to configure other two chip selects as SDRAM +; or FRAM interface. In such a case be aware of the bit meanings. +; +; +; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) +; -------------------------------------------------------------- +; +; Bit description: +; +; W00 : RDY/WRX -> CSX hold extension cycle +; 0 : 0 cycle +; 1 : 1 cycle +; +; W01 : CSX -> RDX/WRX setup extention cycle +; 0 : 0 cycle +; 1 : 1 cycle +; +; W02 : Address -> CSX Delay selection +; 0 : no delay selected +; 1 : delay selected +; +; W03 : WR0X to WR3X/WRX outout timing selection +; 0 : MCLK synchronous write output enable (ASX=L) +; 1 : Asynchronous write strobe output (norma operation) +; +; W05 W04 : select Write recovery cycle +; 0 0 : 0 cycle +; 0 1 : 1 cycle +; 1 0 : 2 cycles +; 1 1 : 3 cycles +; +; W07 W06 : Read -> Write idle cycle selection +; 0 0 : 0 cycle +; 0 1 : 1 cycle +; 1 0 : 2 cycles +; 1 1 : 3 cycles +; +; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles) +; 0 0 0 0 : 0 Wait state +; 0 0 0 1 : 1 Auto-wait cycle +; 0 0 1 0 : 2 Auto-wait cycle +; .... +; 1 1 1 1 : 15 Auto wait cycles +; +; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles) +; 0 0 0 0 : 0 Wait state +; 0 0 0 1 : 1 Auto-wait cycle +; 0 0 1 0 : 2 Auto-wait cycle +; .... +; 1 1 1 1 : 15 Auto wait cycles +; +; +; +; SDRAM and FRAM bus interface (ACRx_Type = 100x) +; ----------------------------------------------- +; +; Bit description: +; +; W01 W00 : RAS precharge cycles. +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 5 cycles +; 1 1 : 6 cycles +; +; W03 W02 : RAS active Time +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 5 cycles +; 1 1 : 6 cycles +; +; W05 W04 : set Write recovery cycle (1 - 4 cycles) +; 0 0 : Prohibited +; 0 1 : 2 cycles +; 1 0 : 3 cycles +; 1 1 : 4 cycles +; +; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles) +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 3 cycles +; 1 1 : 4 cycles +; +; W10 W09 W08 : set CAS latency (1 - 8 cycles) +; 0 0 0 : 1 cycle +; 0 0 1 : 2 cycle +; ... +; 1 1 1 : 8 cycle +; +; W11 : RESERVED, ALWAYS WRITE 0 ! +; +; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles) +; 0 0 0 : 1 cycle +; 0 0 1 : 2 cycle +; ... +; 1 1 1 : 8 cycle +; +; W15 : RESERVED, ALWAYS WRITE 0 ! +; + +; The bit meaning depends on the configured bus interface type +; +;========================================================================================= +; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM) +;========================================================================================= +; +#set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA +; |||||||| +; ||||||||__ ABS0 bit, set max. active banks (ABS1,0) +; |||||||___ ABS1 bit +; ||||||____ BANK bit, set number of banks connected to CS +; |||||_____ WBST bit, Write burst enable/disable +; ||||______ PSZ0 bit, Set page size (PSZ2-0) +; |||_______ PSZ1 bit +; ||________ PSZ2 bit +; |_________ reserved, always write 0 +; +; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must +; be setup. +; +; Bit description: +; +; ABS1 ABS0 : Set maximum number of bank, active at same time +; 0 0 : 1 bank +; 0 1 : 2 banks +; 1 0 : 3 banks +; 1 1 : 4 banks +; +; BANK : Set number of connected SDRAM banks +; 0 : 2 banks +; 1 : 4 banks +; +; WBST : Write burst enable +; 0 : Single Write +; 1 : Busrt Write +; +; PSZ2 PSZ1 PS0 : Select page size of connected memory +; 0 0 0 : 8-bit column address = A0 to A7 +; 0 0 1 : 9-bit column address = A0 to A8 +; 0 1 0 : 10-bit column address = A0 to A9 +; 0 1 1 : 11-bit column address = A0 to A9, A11 +; 1 X X : setting disabled +; +; +;========================================================================================= +; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM) +;========================================================================================= +; +#set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR +; |||||||||||||||| +; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0) +; |||||||||||||||___ TRC1 bit +; ||||||||||||||____ TRC2 bit +; |||||||||||||_____ PON bit, set power-on control +; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0) +; |||||||||||_______ RFC1 bit +; ||||||||||________ RFC2 bit +; |||||||||_________ BRST bit, set burst refresh control +; ||||||||__________ RFINT0 bit, set auto refresh interval +; |||||||___________ RFINT1 bit, (RFINT5-0) +; ||||||____________ RFINT2 bit +; |||||_____________ RFINT3 bit +; ||||______________ RFINT4 bit +; |||_______________ RFINT5 bit +; ||________________ RRLD bit, counter refresh strat control +; |_________________ SELF bit, self refresh control +; +; +; This register sets various SDRAM refresh controls. When SDRAM control is not set for +; any area, the setting of this register is meaningless, but do not change the register +; value at initial state. When a read is performed using a read-modify-write +; instruction, 0 always returns from the SELF, RRLD, and PON bits. +; +; Bit description: +; +; +; TRC2 TRC1 TRC0 : Refresh Cycle +; 0 0 0 : 4 +; 0 0 1 : 5 +; 0 1 0 : 6 +; 0 1 1 : 7 +; 1 0 0 : 8 +; 1 0 1 : 9 +; 1 1 0 : 10 +; 1 1 1 : 11 +; +; PON : Power-on control +; 0 : disabled +; 1 : power-on sequence started +; +; RFC2 RFC1 RFC0 : Refresh Count +; 0 0 0 : 256 +; 0 0 1 : 512 +; 0 1 0 : 1024 +; 0 1 1 : 2048 +; 1 0 0 : 4096 +; 1 0 1 : 8192 +; 1 1 0 : Setting disabled +; 1 1 1 : Refresh disabled +; +; BRST : Burst refresh control +; 0 : Decentralised refresh +; 1 : burst refresh +; +; RFINT[5-0] : auto refresh interval +; +; RRLD : Refresh counter Activation Control +; 0 : Disabled, +; 1 : Autorefresh performed once, then value of RFINT reloaded +; +; SELF : Self refresh control +; 0 : auto refresh or power down +; 1 : Transitions to self-refresch mode +; +; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the +; above setting. Otherwise the settings are not correct set. +; +;========================================================================================= +; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON) +;========================================================================================= +; +#set TIMECONTR B'00000000 ; <<< set TCR register, TCR +; |||||||| +; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1) +; |||||||___ RDW1 bit +; ||||||____ OHT0 bit, set output hold delay (OHT1,0) +; |||||_____ OHT1 bit +; ||||______ reserved, always write 0 +; |||_______ PCLR bit, prefetch buffer clear +; ||________ PSUS bit, prefetch suspend +; |_________ BREN bit, BRQ input enable +; +; This register controls the general functions of the external bus interface controller +; such as the common-pin function setting and timing control. +; +; Bit description: +; +; RDW1 RDW0 : Wait cycle reduction +; 0 0 : Normal Wait (AWR0 - 7 setting) +; 0 1 : 1/2 of AWR0 - 7 setting value +; 1 0 : 1/4 of AWR0 - 7 setting value +; 1 1 : 1/8 of AWR0 - 7 setting value +; +; OHT1 OHT0 : Output hold selection bit +; 0 0 : Output performed at falling edge of SYSCLK/MCLK +; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK +; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK +; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK +; +; PCLR : Prefetch buffer all clear +; 0 : normal state +; 1 : Prefetch buffer cleared +; +; PSUS : prefetch suspension bit +; 0 : Prefetch enabled +; 1 : Prefetch disabled +; +; BREN : BRQ input enable +; 0 : disabled, +; 1 : enabled, Bus sharing of BRQ/BGRNTX performed +; +; Note: This function is used to prevent an excessive access cycle wait while operating +; at a low-speed clock (such as while base clock operating at low speed or +; high frequency division rate for external bus clock). +; +;========================================================================================= +; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON) +;========================================================================================= +; +#set C1024 1 ; CACHE Size: 1024 BYTE +#set C2048 2 ; CACHE Size: 2048 BYTE +#set C4096 3 ; CACHE Size: 4096 BYTE +; +; +#set CACHE OFF ; <<< Select use of cache +#set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE +; +; It is possible to use cache functionality on the I-Bus on several devices. Please +; check the corresponidng data sheet if this feature is available on a certain device +; and for the size of the cache. This is the general cache configuration. It is possible +; to configure for each CS area, if the cache should be used. +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; feature is for example supported by MB91461R, MB91469G. +; +;========================================================================================= +; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON) +;========================================================================================= +; +#set CHEENA B'11111111 ; <<< en-/disable cache, CHER +; |||||||| +; ||||||||__ CHE0 bit, CS0 area +; |||||||___ CHE1 bit, CS1 area +; ||||||____ CHE2 bit, CS2 area +; |||||_____ CHE3 bit, CS3 area +; ||||______ CHE4 bit, CS4 area +; |||_______ CHE5 bit, CS5 area +; ||________ CHE6 bit, CS6 area +; |_________ CHE7 bit, CS7 area +; +; Additional to the general cache enable setting, select which CS area should be used +; with cache functionality. +; +; Note: Not all Chipselects are supported by the different devices. Please check the +; data sheet. +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; Feature is supported by MB91461R, MB91469G. +; +;========================================================================================= +; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00 +; |||||||| +; ||||||||__ D24 / P00_0 +; |||||||___ D25 / P00_1 +; ||||||____ D26 / P00_2 +; |||||_____ D27 / P00_3 +; ||||______ D28 / P00_4 +; |||_______ D29 / P00_5 +; ||________ D30 / P00_6 +; |_________ D31 / P00_7 +; +#set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01 +; |||||||| +; ||||||||__ D16 / P01_0 +; |||||||___ D17 / P01_1 +; ||||||____ D18 / P01_2 +; |||||_____ D19 / P01_3 +; ||||______ D20 / P01_4 +; |||_______ D21 / P01_5 +; ||________ D22 / P01_6 +; |_________ D23 / P01_7 +; +#set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02 +; |||||||| +; ||||||||__ D8 / P02_0 +; |||||||___ D9 / P02_1 +; ||||||____ D10 / P02_2 +; |||||_____ D11 / P02_3 +; ||||______ D12 / P02_4 +; |||_______ D13 / P02_5 +; ||________ D14 / P02_6 +; |_________ D15 / P02_7 +; +#set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03 +; |||||||| +; ||||||||__ D0 / P03_0 +; |||||||___ D1 / P03_1 +; ||||||____ D2 / P03_2 +; |||||_____ D3 / P03_3 +; ||||______ D4 / P03_4 +; |||_______ D5 / P03_5 +; ||________ D6 / P03_6 +; |_________ D7 / P03_7 +; +; Select if the ports are set to +; 1 : External bus mode, I/O for data lines or +; 0 : General I/O port (GIO) +; +; Note: Not all data-lines are supported by the different devices. Please check the data +; sheet. +; +;========================================================================================= +; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04 +; |||||||| +; ||||||||__ A24 / P04_0 +; |||||||___ A25 / P04_1 +; ||||||____ A26 / P04_2 +; |||||_____ A27 / P04_3 +; ||||______ A28 / P04_4 +; |||_______ A29 / P04_5 +; ||________ A30 / P04_6 +; |_________ A31 / P04_7 +; +#set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05 +; |||||||| +; ||||||||__ A16 / P05_0 +; |||||||___ A17 / P05_1 +; ||||||____ A18 / P05_2 +; |||||_____ A19 / P05_3 +; ||||______ A20 / P05_4 +; |||_______ A21 / P05_5 +; ||________ A22 / P05_6 +; |_________ A23 / P05_7 +; +#set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06 +; |||||||| +; ||||||||__ A8 / P06_0 +; |||||||___ A9 / P06_1 +; ||||||____ A10 / P06_2 +; |||||_____ A11 / P06_3 +; ||||______ A12 / P06_4 +; |||_______ A13 / P06_5 +; ||________ A14 / P06_6 +; |_________ A15 / P06_7 +; +#set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07 +; |||||||| +; ||||||||__ A0 / P07_0 +; |||||||___ A1 / P07_1 +; ||||||____ A2 / P07_2 +; |||||_____ A3 / P07_3 +; ||||______ A4 / P07_4 +; |||_______ A5 / P07_5 +; ||________ A6 / P07_6 +; |_________ A7 / P07_7 +; +; Select if the ports are set to +; 1 : External bus mode, I/O for address lines or +; 0 : General I/O port (GIO) +; +; Note: Not all address-lines are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08 +; |||||||| +; ||||||||__ WRX0 / P08_0 +; |||||||___ WRX1 / P08_1 +; ||||||____ WRX2 / P08_2 +; |||||_____ WRX3 / P08_3 +; ||||______ RDX / P08_4 +; |||_______ BGRNTX / P08_5 +; ||________ BRQ / P08_6 +; |_________ RDY / P08_7 +; +#set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09 +; |||||||| +; ||||||||__ CSX0 / P09_0 +; |||||||___ CSX1 / P09_1 +; ||||||____ CSX2 / P09_2 +; |||||_____ CSX3 / P09_3 +; ||||______ CSX4 / P09_4 +; |||_______ CSX5 / P09_5 +; ||________ CSX6 / P09_6 +; |_________ CSX7 / P09_7 +; +#set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10 +; |||||||| +; ||||||||__ SYSCLK or !SYSCLK / P10_0 +; |||||||___ ASX / P10_1 +; ||||||____ BAAX / P10_2 +; |||||_____ WEX / P10_3 +; ||||______ MCLKO or !MCLKO / P10_4 +; |||_______ MCLKI or !MCLKI/ P10_5 +; ||________ MCLKE / P10_6 +; |_________ - +; +#set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10 +; |||||||| +; ||||||||__ 0:SYSCLK / 1:!SYSCLK +; |||||||___ - +; ||||||____ - +; |||||_____ - +; ||||______ 0:MCLKO / 1:!MCLKO +; |||_______ 0:MCLKI / 1:!MCLKI +; ||________ 0:MCLKI / 1:!MCLKI +; |_________ - +; +; +; Select if the ports are set to +; 1 : External bus mode, I/O for control lines or +; 0 : General I/O port (GIO) +; +; Note: Not all control-lines are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 5 Definition of Configurations +;========================================================================================= +; +#set NOCLOCK 0 ; do not touch CKSCR register +#set MAINCLOCK 1 ; select main clock +; ; MB91461R : 1/4 of oscillation input +; ; Others: 1/2 of oscillation input +#set MAINPLLCLOCK 2 ; select main clock with PLL +#set SUBCLOCK 3 ; select subclock (if available) +; +#set PSCLOCK_CLKB 0x00 ; select core clock (initial) +#set PSCLOCK_PLL 0x10 ; select PLL output (x) +#set PSCLOCK_MAIN 0x30 ; select Main Oscillation +; +;========================================================================================= +; 5.1 CLOCKSPEED == CLOCK_USER <<< +;========================================================================================= +; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the +; corresponding application note. +; +#if (CLOCKSPEED == CLOCK_USER ) + #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource + #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF + #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz + #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz + #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz + #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD; + ; Voltage Regulator + #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.2 CLOCKSPEED == NO_CLOCK +;========================================================================================= +; +#if (CLOCKSPEED == NO_CLOCK ) + #set CLOCKSOURCE NOCLOCK +#endif +; +;========================================================================================= +; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ +;========================================================================================= +; +#if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91463N) || (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE SUBCLOCK ; Clocksource + #set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a. + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz + #set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz + #set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz + #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC100 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ +;========================================================================================= +; +#if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a. + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz + #set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz + #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC100 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0B ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC201 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x13 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz + #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x13 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\ + (DEVICE == MB91461R) || (DEVICE == MB91467R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x17 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz + #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\ + (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x17 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz + #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz + #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\ + (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\ + (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz + #set DIV_G 0x0B ; 0x48Eh: PLLDIVG; + #set MUL_G 0x1F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + ; - + ; Memory Controller + ; - +#endif +; +;========================================================================================= +; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\ + (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\ + (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x1F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + ; - + ; Memory Controller + ; - +#endif +; +;========================================================================================= +; 6 Section and Data Declaration +;========================================================================================= + + .export __start + .import _main + .import _RAM_INIT + .import _ROM_INIT + +#if CLIBINIT == ON + .export __exit + .import _exit + .import __stream_init +#endif + +#if CPLUSPLUS == ON + .export __abort + .import ___call_dtors + .import _atexit +#endif +;========================================================================================= +; 6.1 Define Stack Size +;========================================================================================= + .SECTION SSTACK, STACK, ALIGN=4 +#if STACK_RESERVE == ON + .EXPORT __systemstack, __systemstack_top + __systemstack: + .RES.B STACK_SYS_SIZE + __systemstack_top: +#endif + + .SECTION USTACK, STACK, ALIGN=4 +#if STACK_RESERVE == ON + .EXPORT __userstack, __userstack_top + __userstack: + .RES.B STACK_USR_SIZE + __userstack_top: + +#endif +;========================================================================================= +; 6.2 Define Sections +;========================================================================================= + .section DATA, data, align=4 + .section INIT, data, align=4 + .section IRAM, code, align=4 + .section CONST, const, align=4 + .section INTVECT, const, align=4 + +#if I_RAM + .import _RAM_IRAM + .import _ROM_IRAM +#endif + +#if (DEVICE != MB91461R) + #if (DEVICE == MB91469G) + .section SECURITY_VECTORS, code, locate = 0x248000 + #else + .section SECURITY_VECTORS, code, locate = 0x148000 + #endif + + #if (BOOT_FLASH_SEC == OFF) + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + #else + .res.w 4 + #endif +#endif + +#if CPLUSPLUS == ON + .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors +#endif + +;----------------------------------------------------------------------------------------- +; MACRO Clear RC Watchdog +;----------------------------------------------------------------------------------------- +#macro ClearRCwatchdog + LDI #0x4C7,R7 ; clear RC watchdog + BANDL #0x7,@R7 +#endm +;----------------------------------------------------------------------------------------- +; MACRO WAIT_LOOP +;----------------------------------------------------------------------------------------- +#macro wait_loop loop_number +#local _wait64_loop + LDI #loop_number, R0 +_wait64_loop: + ADD #-1, R0 + BNE _wait64_loop +#endm + .section CODE, code, align=4 + .section CODE_START, code, align=4 + + +;========================================================================================= +; 7. S T A R T +;========================================================================================= +__start: ; start point +startnop: + NOP +; + ANDCCR #0xEF ; disable interrupts + STILM #LOW_PRIOR ; set interrupt level to low prior + ClearRCwatchdog ; clear harware watchdog + +;========================================================================================= +; 7.1 Initialise Stack Pointer and Table Base Register +;========================================================================================= +#if STACKUSE == SYSSTACK + ORCCR #0x20 + LDI #__userstack_top, SP ; initialize SP + ANDCCR #0xDF + LDI #__systemstack_top, SP ; initialize SP +#endif + +#if STACKUSE == USRSTACK + ANDCCR #0xDF + LDI #__systemstack_top, SP ; initialize SP + ORCCR #0x20 + LDI #__userstack_top, SP ; initialize SP +#endif + + LDI #INTVECT, R0 ; set Table Base +smd_tbr: + MOV R0, TBR + +#if (CLOCKSOURCE != NOCLOCK) +;========================================================================================= +; 7.2 Check for CSV reset and set CSV +;========================================================================================= +; Start restriction; No clock supervisor (CSV) +#if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N) +; End restriction + LDI:20 #0x04AD, R0 ; CSVCR + BORL #0x8, @R0 ; Enable Main Osc CSV + BTSTH #0x4, @R0 ; Check for Main Osc missing + BEQ NoMAINCSVreset ; Main osc available -> branch + ; to NoCSVreset + BANDL #0x7, @R0 ; Disable Main Osc CSV + + LDI #noClockStartup, R0 ; Main Clock missing -> no + JMP @R0 ; clock startup + +NoMAINCSVreset: + + + BORL #0x4, @R0 ; Enable Sub Osc CSV + BTSTH #0x2, @R0 ; Check for Sub Osc missing + BEQ NoSUBCSVreset ; Sub osc available -> branch + ; to NoCSVreset + BANDL #0xB, @R0 ; Disable Sub Osc SCSV +#if (CLOCKSOURCE == SUBCLOCK) + LDI #noClockStartup, R0 ; Sub Clock missing -> no + JMP @R0 ; clock startup +#endif +NoSUBCSVreset: +#endif +;========================================================================================= +; 7.3 Check Clock Condition +;========================================================================================= + LDI #0x484, R0 ; Check for Default Values + LDI #0x0F, R1 + ANDB R1, @R0 + BEQ clock_startup + +;========================================================================================= +; 7.4 Restore Default Settings after Reset +;========================================================================================= +;========================================================================================= +; 7.4.1 Disable Clock Modulator +;========================================================================================= + LDI #0x04BB, R0 ; Clock Modulator Control Reg + BANDL #0xD, @R0 ; Disable Frequency modulation +FMODwait: + BTSTL #8, @R0 ; Wait until Frequency modulation + BNE FMODwait ; is disabled + + BANDL #0xE, @R0 ; Power down clock modulator + +;========================================================================================= +; 7.4.2 Check if running on Sub Clock, change to Main Clock +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on sub clock + LDUB @R12,R0 + LDI:8 #0x3,R1 + AND R1,R0 + CMP #0x3,R0 + BNE notOnSubClock + + LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped + BTSTL #1, @R12 + BEQ mainNotStopped + + BANDL #0xE, @R12 ; Start Main Oscillation + + LDI #0x4C8, R0 ; Main Stabilisation Wait Time + LDI #0x04, R1 ; 32.7 ms + AND R1, @R0 + BORH #0x02, @R0 + + mainStabTime: ; Wait for stabilisation time + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R0 + BEQ mainStabTime + LDI #0x0, R1 + STB R1, @R0 + +mainNotStopped: + LDI:20 #0x0484, R12 ; disable sub clock as source + BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2) + +notOnSubClock: +;========================================================================================= +; 7.4.3 Disable Sub Clock +;========================================================================================= +#if ENABLE_SUBCLOCK != ON + LDI #0x0484, R0 ; Clock source control reg CLKR + BANDL #0x7, @R0 ; Disable PLL +#endif + +;========================================================================================= +; 7.4.4 Check if running on PLL, Gear Down PLL +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on PLL + LDUB @R12,R0 + LDI:8 #0x3,R1 + AND R1,R0 + CMP #0x2,R0 + BNE notOnPll + + LDI:20 #0x0490, R11 ; clear flags + LDI:8 #0x0,R1 + STB R1, @R11 + LDI #0x04,R1 + STB R1, @R11 ; Set Flag for Simulator; no Effekt on + ; Emulator + + BANDL #0xC, @R12 ; disable PLL as clock source + ; Clock Source = 0x00 (Main/2) + + LDI:20 #0x048E,R12 ; check if DivG != 0 + LDUB @R12, R0 + LDI:8 #0xFF,R1 + AND R1,R0 + BEQ notOnPll + +gearDownLoop: + ClearRCwatchdog ; clear harware watchdog + BTSTL #4, @R11 ; Gear Down + BEQ gearDownLoop ; + + LDI #0x00,R1 ; Clear Flags + STB R1, @R11 ; + +notOnPll: +;========================================================================================= +; 7.4.5 Disable PLL +;========================================================================================= + LDI #0x0484, R0 ; Clock source control reg CLKR + BANDL #0xB, @R0 ; Disable PLL + +;========================================================================================= +; 7.4.6 Set to Main Clock +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on PLL + BANDL #0xC, @R12 ; disable PLL as clock source + ; Clock Source = 0x00 (Main/2) + +clock_startup: +;========================================================================================= +; 7.5 Set Memory Controller +;========================================================================================= +; Start restriction; No embedded flash +#if DEVICE != MB91461R +; End restriction + LDI #0x7002, R1 ; FLASH Controller Reg. + LDI #FLASHCONTROL, R2 ; Flash Controller Settings + STH R2, @R1 ; set register + LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg. + LDI #FLASHREADT, R2 ; wait settings + STH R2, @R1 ; set register + LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg. + LDI #FLASHMWT2, R2 ; wait settings + STB R2, @R1 ; set register +#endif + ClearRCwatchdog + +;========================================================================================= +; 7.6 Clock startup +;========================================================================================= +;========================================================================================= +; 7.6.1 Set Voltage Regulator Settings +;========================================================================================= +; Start restriction; No regulator settings +#if DEVICE != MB91461R +; End restriction + LDI #0x04CF, R0 ; REGCTR + LDI #REGULATORCTRL, R1 + STB R1, @R0 + + LDI #0x04CE, R0 ; REGSEL + LDI #REGULATORSEL, R1 + STB R1, @R0 +#endif + +;========================================================================================= +; 7.6.2 Power on Clock Modulator - Clock Modulator Part I +;========================================================================================= +#if CLOMO == ON + LDI #0x04BB, R0 ; Clock Modulator Control Reg + LDI #0x11, R1 ; Load value to Power on CM + ORB R1, @R0 ; Power on clock modulaor +#endif + +;========================================================================================= +; 7.6.3 Set CLKR Register w/o Clock Mode +;========================================================================================= +; Set Clock source (Base Clock) for the three clock tree selections +; This select Base clock is used to select afterwards the 3 +; Clocks for the diffenrent internal trees. +; When PLL is used, first pll multiplication ratio is set and PLL is +; enabled. After waiting the PLL stabilisation time via timebase +; timer, PLL clock is selected as clock source. + LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N + LDI:20 #PLLSPEED, R1 + STH R1, @R0 + + LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG + LDI #DIV_G, R1 + STB R1, @R0 + + LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG + LDI #MUL_G, R1 + STB R1, @R0 + +;========================================================================================= +; 7.6.4 Start PLL +;========================================================================================= +#if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) ) + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x04, R1 ; Use PLL x1, enable PLL + ORB R1, @R0 ; store data to CLKR register +#endif + + +#if ENABLE_SUBCLOCK == ON + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x08, R1 ; enable subclock operation + ORB R1, @R0 ; store data to CLKR register + LDI #0x4CA, R0 ; Sub Clock oszilation + LDI #0x00, R1 ; stabilitsation time = 32 ms + AND R1, @R0 + BORH #0x02, @R0 +#endif + +;========================================================================================= +; 7.6.5 Wait for PLL oscillation stabilisation +;========================================================================================= +#if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL)) + LDI #0x0482, R12 ; TimeBaseTimer TBCR + LDI #0x00, R1 ; set 1024 us @ 2 MHz + STB R1, @R12 + + BANDH #7, @R12 ; clear interrupt flag + + LDI #0x0483, R0 ; clearTimeBaseTimer CTBR + LDI #0xA5, R1 + STB R1, @R0 + LDI #0x5A, R1 + STB R1, @R0 + + BANDH #7, @R12 ; clear interrupt flag + BORH #8, @R12 ; set interrupt flag for simulator + +PLLwait: + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R12 + BEQ PLLwait +#endif + +;========================================================================================= +; 7.6.6 Set clocks +;========================================================================================= +;========================================================================================= +; 7.6.6.1 Set CPU and peripheral clock +;========================================================================================= +; CPU and peripheral clock are set in one register + LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB) + LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting + STB R3, @R2 +;========================================================================================= +; 7.6.6.2 Set External Bus interface clock +;========================================================================================= +; set External Bus clock +; Be aware to do smooth clock setting, to avoid wrong clock setting +; Take care, always write 0 to the lower 4 bits of DIVR1 register + LDI #0x0487, R2 ; Set DIVR1 + LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting + STB R3, @R2 + +;========================================================================================= +; 7.6.6.3 Set CAN clock prescaler +;========================================================================================= +; Set CAN Prescaler, only clock relevant parameter + LDI #0x04C0, R0 ; Set CAN ClockParameter Register + LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider + STB R1, @R0 ; Set Divider +; enable CAN clocks + LDI #0x04c1, R0 ; Set CAN Clock enable Register + LDI #CANCLOCK, R1 ; Load CANCLOCK + STB R1, @R0 ; set CANCLOCK + +;========================================================================================= +; 7.6.6.4 Switch Main Clock Mode +;========================================================================================= +#if CLOCKSOURCE == MAINCLOCK + +;========================================================================================= +; 7.6.6.5 Switch Subclock Mode +;========================================================================================= +#elif ( (CLOCKSOURCE == SUBCLOCK) ) + #if ENABLE_SUBCLOCK == ON + LDI #0x4CA, R12 +subStabTime: + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R12 ; wait until sub clock stabilisation + BEQ subStabTime ; time is over + LDI #0x0, R1 + STB R1, @R12 + + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x01, R1 ; load value to select main clock + ORB R1, @R0 ; enable main clock (1/2 external) + LDI #0x03, R1 ; load value to select subclock + ORB R1, @R0 ; enable subclock as clock source + #else + #error: Wrong setting! The clock source is subclock, but the subclock is disabled. + #endif + +;========================================================================================= +; 7.6.7 Switch to PLL Mode +;========================================================================================= +#elif ( (CLOCKSOURCE == MAINPLLCLOCK) ) + +#if (DIV_G != 0x00) + LDI #0x0490, R0 ; PLL Ctrl Register + LDI #0x00,R1 + STB R1, @R0 ; Clear Flag + LDI #0x01,R1 + STB R1, @R0 ; Set Flag for Simulator; no Effekt on +#endif ; Emulator + + LDI #0x0484, R3 ; Clock source control reg CLKR + BORL #0x2, @R3 ; enable PLL as clock source + +#if (DIV_G != 0x00) +gearUpLoop: + ClearRCwatchdog ; clear harware watchdog + LDUB @R0, R2 ; LOAD PLLCTR to R2 + AND R1, R2 ; GRUP, counter reach 0 + BEQ gearUpLoop + + LDI #0x00,R1 + STB R1, @R0 ; Clear Gear-Up Flag +#endif + +#endif + +;========================================================================================= +; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II +;========================================================================================= +#if CLOMO == ON ; Only applicable if Modulator is on + LDI #0x04B8, R0 ; Clock Modulation Parameter Reg + LDI #CMPR, R1 ; Load CMP value + STH R1, @R0 ; Store CMP value in CMPR + + LDI #0x04BB, R0 ; Clock Modulator Control Reg + LDI #0x13, R1 ; Load value to FM on CM + ORB R1, @R0 ; FM on +#endif + +#endif +noClockStartup: + +;========================================================================================= +; 7.7 Set BusInterface +;========================================================================================= +; Start restriction; No ext. bus interface +#if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \ + (DEVICE != MB91463N) && (DEVICE != MB91465X) +; End restriction +#if (EXTBUS == ON) +;========================================================================================= +; 7.7.1 Disable all CS +;========================================================================================= +; Start restriction; Flashless device +#if(DEVICE != MB91461R) +; End restriction + LDI #0x0680, R3 ; chip select enable register CSER + LDI #(0x00), R2 ; load disable settings +smd_cs: + ANDB R2, @R3 ; set register +#endif + +;========================================================================================= +; 7.7.2 Clear TCR Register +;========================================================================================= + LDI #0x0683, R1 ; Pin/Timing Control Register TCR + BORH #0x6,@R1 ; load timing settings + +;========================================================================================= +; 7.7.3 Set CS0 +;========================================================================================= +#if CS0 + LDI #0x0640, R1 ; area select reg ASR0, ACR0 + LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings + ST R0, @R1 ; set registers + + LDI #0x660, R1 ; area wait register awr0 + LDI #WAITREG0, R2 ; wait settings + STH R2, @R1 ; set register +#endif + +;========================================================================================= +; 7.7.4 Set CS1 +;========================================================================================= +#if CS1 + LDI #0x0644, R1 ; area select reg ASR1, ACR1 + LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings + ST R0, @R1 ; set registers + + LDI #0x662, R1 ; area wait register awr1 + LDI #WAITREG1, R2 ; wait settings + STH R2, @R1 ; set register +#endif +smd_cs_mb91461r: +;========================================================================================= +; 7.7.5 Set CS2 +;========================================================================================= +#if CS2 + LDI #0x0648, R1 ; area select reg ASR2, ACR2 + LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x664, R1 ; area wait register awr2 + LDI #WAITREG2, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.6 Set CS3 +;========================================================================================= +#if CS3 + LDI #0x064C, R1 ; area select reg ASR3, ACR3 + LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x666, R1 ; area wait register awr3 + LDI #WAITREG3, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.7 Set CS4 +;========================================================================================= +#if CS4 + LDI #0x0650, R1 ; area select reg ASR4, ACR4 + LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x668, R1 ; area wait register awr4 + LDI #WAITREG4, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.8 Set CS5 +;========================================================================================= +#if CS5 + LDI #0x0654, R1 ; area select reg ASR5, ACR5 + LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66A, R1 ; area wait register awr5 + LDI #WAITREG5, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.9 Set CS6 +;========================================================================================= +#if (CS6) + LDI #0x0658, R1 ; area select reg ASR6, ACR6 + LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66C, R1 ; area wait register awr6 + LDI #WAITREG6, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.10 Set CS7 +;========================================================================================= +#if CS7 + LDI #0x065C, R1 ; area select reg ASR7, ACR7 + LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66E, R1 ; area wait register awr7 + LDI #WAITREG7, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.11 Set special SDRAM config register +;========================================================================================= +#if (SDRAM) + LDI #0x670, R1 ; SDRAM memory config register + LDI #MEMCON, R2 ; wait settings + STB R2, @R1 ; set register +#endif + +;========================================================================================= +; 7.7.12 set Port Function Register +;========================================================================================= +;========================================================================================= +; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port +;========================================================================================= + LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) + LDI #PFUNC0, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port +;========================================================================================= + LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) + LDI #PFUNC1, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port +;========================================================================================= + LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) + LDI #PFUNC2, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port +;========================================================================================= + LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) + LDI #PFUNC3, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port +;========================================================================================= + LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) + LDI #PFUNC4, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port +;========================================================================================= + LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) + LDI #PFUNC5, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port +;========================================================================================= + LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) + LDI #PFUNC6, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port +;========================================================================================= + LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) + LDI #PFUNC7, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) + LDI #PFUNC8, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) + LDI #PFUNC9, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) + LDI #PFUNC10, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10) + LDI #EPFUNC10, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.13 Set TCR Register +;========================================================================================= + LDI #0x0683, R1 ; Pin/Timing Control Register TCR + LDI #TIMECONTR, R0 ; load timing settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.14 Enable CACHE for selected CS +;========================================================================================= + LDI #0x0681, R3 ; chip select enable register CSER + LDI #CHEENA, R2 + ORB R2, @R3 +;========================================================================================= +; 7.7.15 set SDRAM Referesh Control Register +;========================================================================================= +#if (SDRAM) + LDI #0x0684, R1 ; Refresh Control Register RCR + LDI #REFRESH, R0 ; load refresh settings + STH R0, @R1 ; set register + LDI #0x0008, R2 + OR R2, R0 ; Set PON bit to 1 + STH R0, @R1 ; set register +#endif +;========================================================================================= +; 7.7.16 Enable used CS +;========================================================================================= + LDI #0x0680, R3 ; chip select enable register CSER + LDI #ENACSX, R2 +; Start restriction; Flashless device +#if (DEVICE == MB91461R) +; End restriction +emu_sram_cs_mb91461r: + ANDB R2, @R3 ; set register +#else + ORB R2, @R3 +#endif +;========================================================================================= +; 7.7.17 I-cache on/off +;========================================================================================= +; Start restriction; No cache +#if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others) +; End restriction + #if CACHE + #if CACHE_SIZE == C1024 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x00, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #elif CACHE_SIZE == C2048 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x01, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #elif CACHE_SIZE == C4096 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x02, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #else + #error: Wrong Cache size selected! + #endif + #else + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x06, R2 ; Release entry locks, flush and disable + STB R2, @R1 ; cache + #endif +#endif +#elif (EXTBUS == OFF) +;========================================================================================= +; 7.7.18 set Port Function Register to general as I/O-Port +;========================================================================================= +;========================================================================================= +; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= + +#elif (EXTBUS == DEFAULT) + NOP +smd_cs_mb91461r: +emu_sram_cs_mb91461r: +smd_cs: +#endif ; #endif (EXTBUS) +#endif ; #endif (excl. devices) + ClearRCwatchdog + +;========================================================================================= +; 7.8 Copy code from Flash to I-RAM +;========================================================================================= +#if I_RAM == ON + LDI #_RAM_IRAM, R0 + LDI #_ROM_IRAM, R1 + LDI #sizeof(IRAM), R13 + CMP #0, R13 + BEQ copy_iram_end +copy_iram1: + ADD #-1, R13 + LDUB @(R13, R1), R12 + BNE:D copy_iram1 + STB R12, @(R13, R0) +copy_iram_end: + ClearRCwatchdog +#endif + +;========================================================================================= +; 7.9 Fill stacks +;========================================================================================= +#if STACK_FILL == ON + LDI #STACK_PATTERN, R0 + LDI #SSTACK, R1 + LDI #sizeof(SSTACK), R2 + CMP #0, R2 + BEQ:D fill_sstack_end + MOV R2, R13 + LDI #3, R12 + AND R2, R12 + BEQ:D fill_sstack2 + MOV R2, R3 + SUB R12, R3 + LDI #0x3, R4 + SUB R12, R4 + LSL #0x3, R4 + LDI #STACK_PATTERN, R5 + LSR R4, R5 + LDI #0x8, R4 +fill_sstack1: + ADD #-1, R13 + LSR R4, R5 + CMP R3, R13 + BHI:D fill_sstack1 + STB R5, @(R13, R1) + CMP #0, R3 + BEQ:D fill_sstack_end +fill_sstack2: + ADD #-4, R13 + BGT:D fill_sstack2 + ST R0, @(R13, R1) +fill_sstack_end: + + LDI #STACK_PATTERN, R0 + LDI #USTACK, R1 + LDI #sizeof(USTACK), R2 + CMP #0, R2 + BEQ:D fill_ustack_end + MOV R2, R13 + LDI #3, R12 + AND R2, R12 + BEQ:D fill_ustack2 + MOV R2, R3 + SUB R12, R3 + LDI #0x3, R4 + SUB R12, R4 + LSL #0x3, R4 + LDI #STACK_PATTERN, R5 + LSR R4, R5 + LDI #0x8, R4 +fill_ustack1: + ADD #-1, R13 + LSR R4, R5 + CMP R3, R13 + BHI:D fill_ustack1 + STB R5, @(R13, R1) + CMP #0, R3 + BEQ:D fill_ustack_end +fill_ustack2: + ADD #-4, R13 + BGT:D fill_ustack2 + ST R0, @(R13, R1) +fill_ustack_end: + ClearRCwatchdog +#endif + +;========================================================================================= +; Standard C startup +;========================================================================================= +;========================================================================================= +; 7.10 Clear data +;========================================================================================= +; clear DATA section +; According to ANSI, the DATA section must be cleared during start-up + LDI:8 #0, R0 + LDI #sizeof DATA &~0x3, R1 + LDI #DATA, R13 + CMP #0, R1 + BEQ data_clr1 +data_clr0: + ADD2 #-4, R1 + BNE:D data_clr0 + ST R0, @(R13, R1) +data_clr1: + LDI:8 #sizeof DATA & 0x3, R1 + LDI #DATA + (sizeof DATA & ~0x3), R13 + + CMP #0, R1 + BEQ data_clr_end +data_clr2: + ADD2 #-1, R1 + BNE:D data_clr2 + STB R0, @(R13, R1) +data_clr_end: + ClearRCwatchdog + +;========================================================================================= +; 7.11 Copy Init section from ROM to RAM +;========================================================================================= +; copy rom +; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area. +; (start value) +; The Application must copy the Section (Init) into the RAM area. + LDI #_RAM_INIT, R0 + LDI #_ROM_INIT, R1 + LDI #sizeof(INIT), R2 + CMP #0, R2 + BEQ:D copy_rom_end + LDI #3, R12 + AND R2, R12 + BEQ:D copy_rom2 + MOV R2, R13 + MOV R2, R3 + SUB R12, R3 +copy_rom1: + ADD #-1, R13 + LDUB @(R13, R1), R12 + CMP R3, R13 + BHI:D copy_rom1 + STB R12, @(R13, R0) + CMP #0, R3 + BEQ:D copy_rom_end +copy_rom2: + ADD #-4, R13 + LD @(R13, R1), R12 + BGT:D copy_rom2 + ST R12, @(R13, R0) +copy_rom_end: + ClearRCwatchdog + +;========================================================================================= +; 7.12 C library initialization +;========================================================================================= +#if CLIBINIT == ON + CALL32 __stream_init, r12 ; initialise library +#endif +;========================================================================================= +; 7.13 call C++ constructors +;========================================================================================= +#if CPLUSPLUS == ON + LDI #___call_dtors, r4 + CALL32 _atexit, r12 + + LDI #EXT_CTOR_DTOR, r8 + LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9 + CMP r9, r8 + BEQ L1 +L0: + LD @r8, r10 + CALL:D @r10 + ADD #4, r8 + CMP r9, r8 + BC L0 +L1: +#endif + +start_main: +;========================================================================================= +; 7.14 call main routine +;========================================================================================= + ClearRCwatchdog ; clear harware watchdog + LDI:8 #0, r4 ; Set the 1st parameter for main to 0. + CALL32:d _main, r12 + LDI:8 #0, r5 ; Set the 2nd parameter for main to 0. +#if CLIBINIT == ON + CALL32 _exit, r12 + __exit: +#endif + +#if CPLUSPLUS == ON + __abort: +#endif + +;========================================================================================= +; 7.15 Return from main function +;========================================================================================= +end: + BRA end + .end __start diff --git a/changes_to_HWM.txt b/changes_to_HWM.txt new file mode 100644 index 0000000..e33bd33 --- /dev/null +++ b/changes_to_HWM.txt @@ -0,0 +1,23 @@ + + +Differences to the manual +------------------------- + + +# Port Data Register + - Bitnames in headerfiles are D7 to D0 + +# ROM Select Register + - ROMS, Bitnames in headerfile are D00 to D15 + +# CAN IFx Data A and Data B Registers IFxDTA_SWPyz + - IFx Data A and Data B Registers with Little endian order are named IFxDTA_SWPyz + for example CAN 0 + Hardware Manual: Address: 0x00C030H; Register Name: IF1DTA20 + Header File : Address: 0x00C030H; Register Name: IF1DTA_SWP20 + +# ADC Status Register, Timing Register, Enable Register and Data Register: + - Status Register: ADCS (16Bit access) in HWM only 2 8Bit types ADCS0 and ADCS1 + - Data Register: ADCR (16Bit access) in HWM only 2 8Bit types ADCR1 and ADCR0 + - Timing Register: ADCT (16Bit access) in HWM only 2 8Bit types ADCT1 and ADCT0 + - Enable Register: ADER (32Bit access) in HWM only 2 16Bit types ADERL and ADERH \ No newline at end of file diff --git a/cscope.out b/cscope.out new file mode 100644 index 0000000..901aebf --- /dev/null +++ b/cscope.out @@ -0,0 +1,114105 @@ +cscope 15 /media/bigdata/Documents/uni/projekt_flexray/flashorn/91460_flash_programming_demo_mb91465k-v10/SRC 0000505034 + @Flash.c + +8  + ~"FÏsh.h +" + +9  + ~"mb91465k.h +" + +11  + gIFÏg +; + +13 #´agm¨ +£ùiÚ + +CODE += +IRAM +, +©Œ +=CODE + +16  + $FLASH_P»·»Wr™eH®fWÜdMode +() + +20 #´agm¨ +asm + + +21 +ST + +RP +,@- +R15 + + +22 + `STM0 + ( +R4 +, +R5 +) + +23 + `STM1 + ( +R12 +) + +24 +LDI + #0 +x01 +, +R4 + ; +S‘ + +FLASH + +to + 16B +™ + +»ad +/ +wr™e + +Mode + + +25 +LDI + #0 +x04 +, +R5 + ; +Go + 4 +times + +through + +d–ay + + `loÝ + (64 +MHz + +CLKB +) + +26 +LDI + #0 +xBF60 +, +R12 + + +27 +CALL + @ +R12 + + +28 + `LDM1 + ( +R12 +) + +29 + `LDM0 + ( +R4 +, +R5 +) + +30 +LD + @ +R15 ++, +RP + + +31 #´agm¨ +’dasm + + +36 +FMWT_ATD + = 1; + +37 +FMWT_WEXH + = 0; + +38 +FMWT_WTC + = 8; + +39 + } +} + +41  + $FLASH_P»·»R—dMode +() + +45 #´agm¨ +asm + + +46 +ST + +RP +,@- +R15 + + +47 + `STM0 + ( +R4 +, +R5 +) + +48 + `STM1 + ( +R12 +) + +49 +LDI + #0 +x00 +, +R4 + ; +S‘ + +FLASH + +to + 32B +™ + +»ad +/ +wr™e + +Mode + + +50 +LDI + #0 +x04 +, +R5 + ; +Go + 4 +times + +through + +d–ay + + `loÝ + (64 +MHz + +CLKB +) + +51 +LDI + #0 +xBF60 +, +R12 + + +52 +CALL + @ +R12 + + +53 + `LDM1 + ( +R12 +) + +54 + `LDM0 + ( +R4 +, +R5 +) + +55 +LD + @ +R15 ++, +RP + + +56 #´agm¨ +’dasm + + +61 +FMWT_ATD + = 1; + +62 +FMWT_EQ + = 3; + +63 +FMWT_WTC + = 4; + +64 + } +} + +67  + $FLASH_SeùÜE¿£ +( +£ÿdr +) + +69  +æag + = 0; + +70 vÞ©ž +v®ue + = 0; + +73 +IFÏg + = + `FLASH_SaveDi§bËIÁ”ru±FÏg +(); + +76 + `FLASH_P»·»Wr™eH®fWÜdMode +(); + +78 +£ÿdr + |= 0x0003; + +81 * +h£q_1 + = 0x00AA; + +82 * +h£q_2 + = 0x0055; + +83 * +h£q_1 + = 0x0080; + +84 * +h£q_1 + = 0x00AA; + +85 * +h£q_2 + = 0x0055; + +86 *(*) +£ÿdr + = 0x0030; + +89  !Ð*(*) +£ÿdr + & +SETIMR + ) ) + +92 +HWWD_CL + = 0; + +95 ifÐ + `FLASH_CheckP’dšgIÁ”ru± +() ) + +98 + `FLASH_Su¥’dSeùÜE¿£ +( +£ÿdr +); + +101 + `FLASH_P»·»R—dMode +(); + +104 + `FLASH_Re¡ÜeIÁ”ru±FÏg +( +IFÏg +); + +107  + `FLASH_CheckP’dšgIÁ”ru± +(èè +HWWD_CL + = 0; + +110 +IFÏg + = + `FLASH_SaveDi§bËIÁ”ru±FÏg +(); + +113 + `FLASH_P»·»Wr™eH®fWÜdMode +(); + +116 + `FLASH_ResumeSeùÜE¿£ +( +£ÿdr +); + +121  +æag + == 0 ) + +124 +HWWD_CL + = 0; + +127 ifÐ + `FLASH_CheckP’dšgIÁ”ru± +() ) + +130 + `FLASH_Su¥’dSeùÜE¿£ +( +£ÿdr +); + +133 + `FLASH_P»·»R—dMode +(); + +136 + `FLASH_Re¡ÜeIÁ”ru±FÏg +( +IFÏg +); + +139  + `FLASH_CheckP’dšgIÁ”ru± +(èè +HWWD_CL + = 0; + +142 +IFÏg + = + `FLASH_SaveDi§bËIÁ”ru±FÏg +(); + +145 + `FLASH_P»·»Wr™eH®fWÜdMode +(); + +148 + `FLASH_ResumeSeùÜE¿£ +( +£ÿdr +); + +153 ifÐÐ*(*) +£ÿdr + & +DPOLL + ) ) + +155 +æag + = 1; + +157 ifÐÐ*(*) +£ÿdr + & +TLOVER + ) ) + +159 ifÐÐ*(*) +£ÿdr + & +DPOLL + ) ) + +161 +æag + = 1; + +166 + `FLASH_R—dRe£t +(); + +168 +æag + = 2; + +175 + `FLASH_Re¡ÜeIÁ”ru±FÏg +( +IFÏg +); + +178 + `FLASH_P»·»R—dMode +(); + +180  +æag +; + +181 + } +} + +183  + $FLASH_SeùÜBÏnkCheck +( +£ÿddr +,  +size +) + +185  +couÁ +; + +186  +em±y_æag + = 0; + +187  +addr + = +£ÿddr +; + +190 +FMCS_FIXE + = 0; + +192  +couÁ + = 0; couÁ < +size +; count ++) + +195 +HWWD_CL + = 0; + +196 ifÐ*(*) +addr + !ð0xFFFFFFFF ) +em±y_æag + = 1; + +197 +addr + += 4; + +201 +FMCS_FIXE + = 1; + +203 ifÐ +em±y_æag + != 0 ) + +209 + } +} + +211  + $FLASH_Wr™eH®fWÜd +( +adr +,  +d©a +) + +213  +æag + = 0; + +216 +IFÏg + = + `FLASH_SaveDi§bËIÁ”ru±FÏg +(); + +219 + `FLASH_P»·»Wr™eH®fWÜdMode +(); + +222 * +h£q_1 + = 0x00AA; + +223 * +h£q_2 + = 0x0055; + +224 * +h£q_1 + = 0x00A0; + +225 *((vÞ©ž*) +adr +èð +d©a +; + +228  +æag + == 0 ) + +231 +HWWD_CL + = 0; + +233 ifÐÐ*(vÞ©ž*) +adr + & +DPOLL + ) =ð( +d©a + & DPOLL) ) + +235 +æag + = 1; + +237 ifÐÐ*(vÞ©ž*) +adr + & +TLOVER + ) == TLOVER ) + +239 ifÐÐ*(vÞ©ž*) +adr + & +DPOLL + ) =ð( +d©a + & DPOLL) ) + +241 +æag + = 1; + +246 * +h£q_1 + = 0x00F0; + +248 +æag + = 2; + +254 + `FLASH_P»·»R—dMode +(); + +257 + `FLASH_Re¡ÜeIÁ”ru±FÏg +( +IFÏg +); + +259  +æag +; + +260 + } +} + +263  + $FLASH_R—dRe£t +() + +265 * +h£q_1 + = 0x00F0; + +268 + } +} + +270 #´agm¨ +asm + + +271 + g_FLASH_SaveDi§bËIÁ”ru±FÏg +: + +272 + $STM0 + ( +R0 +) + +273 +MOV + +PS +, +R4 + + +274 +LDI + #0 +x00000010 +, +R0 + + +275 +AND + +R0 +, +R4 + ; +StÜe + +Origš® + +FÏg + + +276 +ANDCCR + #0 +xFFFFFFEF + ; +Cˬ + +IÁ”ru± + +FÏg + + +277 + $LDM0 + ( +R0 +) + +278 +RET + + +279 #´agm¨ +’dasm + + +282 #´agm¨ +asm + + +283 +_FLASH_Re¡ÜeIÁ”ru±FÏg +: + +284 + $STM0 + ( +R0 +) + +285 +MOV + +PS +, +R0 + ; +G‘ + +cu¼’t + PS + +286 +OR + +R4 +, +R0 + ; +S‘ + +FÏg + +as + +§ved + + +287 +MOV + +R0 +, +PS + ; +Wr™e + +back + PS + +288 + $LDM0 + ( +R0 +) + +289 +RET + + +290 #´agm¨ +’dasm + + +293  + $FLASH_Su¥’dSeùÜE¿£ +( +£ÿddr +) + +296 *(vÞ©ž*) +£ÿddr + = 0x00B0; + +299 !(*(*) +£ÿddr + & +DPOLL +è&& (*(*)£ÿdd¸ & +SETIMR +)) + +301 +HWWD_CL +=0; + +305 + } +} + +307  + $FLASH_ResumeSeùÜE¿£ +( +£ÿddr +) + +310 *(vÞ©ž*) +£ÿddr + = 0x0030; + +313 (*(*) +£ÿddr + & +DPOLL +è&& !(*(*)£ÿdd¸ & +SETIMR +)) + +315 +HWWD_CL +=0; + +319 + } +} + +321  + $FLASH_CheckP’dšgIÁ”ru± +() + +324 if( +TMCSR0_UF +)  1; + +328 + } +} + + @Flash.h + +8 #iâdeà +__FLASH_H__ + + +9  + #__FLASH_H__ + + + ) + +11  + ~"MB91465K.H +" + +13  + #h£q_1 + ((vÞ©ž*)0x000A1557) + + ) + +14  + #h£q_2 + ((vÞ©ž*)0x000A0AAF) + + ) + +17  + #DPOLL + 0x0080 + + ) + +18  + #TLOVER + 0x0020 + + ) + +19  + #SETIMR + 0x0008 + + ) + +21  +FLASH_P»·»Wr™eH®fWÜdMode +(); + +22  +FLASH_P»·»R—dMode +(); + +23  +FLASH_Wr™eH®fWÜd +( +adr +,  +d©a +); + +24  +FLASH_SeùÜE¿£ +( +£c_adr +); + +25  +FLASH_ChE¿£ +(); + +26  +FLASH_SeùÜBÏnkCheck +( +£ÿddr +,  +size +); + +27  +FLASH_R—dRe£t +(); + +28  +FLASH_Su¥’dSeùÜE¿£ +( +£ÿddr +); + +29  +FLASH_ResumeSeùÜE¿£ +( +£ÿddr +); + +30  +FLASH_SaveDi§bËIÁ”ru±FÏg +(); + +31  +FLASH_Re¡ÜeIÁ”ru±FÏg +( +æag +); + +32  +FLASH_CheckP’dšgIÁ”ru± +(); + + @MAIN.c + +15  + ~"mb91465k.h +" + +16  + ~"veùÜs.h +" + +17  + ~"RLT.h +" + +18  + ~"FÏsh.h +" + +39  + $maš +() + +41  +”rÜ + = 0; + +42  +glob®_”rÜ + = 0; + +43  +i +; + +46 +CSCFG_MONCKI + = 1; + +47 +CMCFG + = 0x0D; + +49 + `__EI +(); + +50 + `__£t_ž +(31); + +51 + `In™IrqLev–s +(); + +53 +PORTEN + = 0x3; + +58 +DDR27 + = 0xFF; + +59 +PDR27 + = 0x00; + +62 + `RLT_In™ŸlizeTim” +(0, +RLT_RUMMODE_RELOAD +, +RLT_CLOCKMODE_DIV32 +, +RLT_TRIGGER_SOFTWARE +, +RLT_OUTOUTMODE_HIGHLEVEL +); + +63 + `RLT_S‘R–ßdV®ue +(0,0x1388); + +64 + `RLT_EÇbËIÁ”ru± +(0); + +65 + `RLT_Trigg”Tim” +(0); + +68 + `In™U¬t4 +(); + +71 + `Puts4 +(" \n\n"); + +72 + `Puts4 +("\n\n********** Welcomeo FUJITSU FLASH Programming Demo **********\n"); + +75 + `Puts4 +("Blank Check of FLASH Sector‡t 0xA0000 ... "); + +76 +”rÜ + = + `FLASH_SeùÜBÏnkCheck +(0xA0000, 0x4000); + +77 ifÐ +”rÜ + == 1 ) + +79 + `Puts4 +("done.\n"); + +83 + `Puts4 +("failed.\n"); + +87 +i +=0; + +88 + `Puts4 +("\nCurrent Content of FLASH‡t 0xA0000 ... 0xA001F:\n"); + +89  +i + < 0x20) + +91 + `Puts4 +("0x"); + `Puthex4 +Ð*(*)(0xA0000 + +i +), 2); Puts4(" "); + +92 +i +++; + +93 ifÐ( +i + % 0x10è=ð0 ) + `Puts4 +("\n"); + +95 + `Puts4 +("\n"); + +98 + `Puts4 +("Sector Erase of 0xA0000 ... "); + +99 +”rÜ + = + `FLASH_SeùÜE¿£ +(0xA0000); + +100 +”rÜ + = + `FLASH_SeùÜE¿£ +(0xA0004); + +101 ifÐ +”rÜ + == 1 ) + +103 + `Puts4 +("done.\n"); + +107 +glob®_”rÜ + = 1; + +108 + `Puts4 +("failed.\n"); + +112 + `Puts4 +("Blank Check of FLASH Sector‡t 0xA0000 ... "); + +113 +”rÜ + = + `FLASH_SeùÜBÏnkCheck +(0xA0000, 0x4000); + +114 ifÐ +”rÜ + == 1 ) + +116 + `Puts4 +("done.\n"); + +120 +glob®_”rÜ + = 1; + +121 + `Puts4 +("failed.\n"); + +125 +i +=0; + +126 + `Puts4 +("\nCurrent Content of FLASH‡t 0xA0000 ... 0xA001F:\n"); + +127  +i + < 0x20) + +129 + `Puts4 +("0x"); + `Puthex4 +Ð*(*)(0xA0000 + +i +), 2); Puts4(" "); + +130 +i +++; + +131 ifÐ( +i + % 0x10è=ð0 ) + `Puts4 +("\n"); + +133 + `Puts4 +("\n"); + +136 + `Puts4 +("Write 0x55AAo 0xA0002 ... "); + +137 +”rÜ + = + `FLASH_Wr™eH®fWÜd +(0xA0002,0x55AA); + +138 ifÐ +”rÜ + == 1 ) + +140 + `Puts4 +("done.\n"); + +144 +glob®_”rÜ + = 1; + +145 + `Puts4 +("failed.\n"); + +149 + `Puts4 +("Write 0x33CCo 0xA0004 ... "); + +150 +”rÜ + = + `FLASH_Wr™eH®fWÜd +(0xA0004,0x33CC); + +151 ifÐ +”rÜ + == 1 ) + +153 + `Puts4 +("done.\n"); + +157 +glob®_”rÜ + = 1; + +158 + `Puts4 +("failed.\n"); + +162 +i +=0; + +163 + `Puts4 +("\nCurrent Content of FLASH‡t 0xA0000 ... 0xA001F:\n"); + +164  +i + < 0x20) + +166 + `Puts4 +("0x"); + `Puthex4 +Ð*(*)(0xA0000 + +i +), 2); Puts4(" "); + +167 +i +++; + +168 ifÐ( +i + % 0x10è=ð0 ) + `Puts4 +("\n"); + +170 + `Puts4 +("\n"); + +174 ifÐ +glob®_”rÜ + != 0 ) + +176 + `Puts4 +("\n********* FLASH Programming Demo failed **********\n"); + +180 + `Puts4 +("\n********* FLASH Programming Demo done **********\n"); + +186 +HWWD_CL + = 0; + +195 + } +} + + @RLT.c + +8  + ~"RLT.h +" + +10  + $RLT_In™ŸlizeTim” +( +chªÃl +,  +runmode +,  +þockmode +,  +Œigg”mode +,  +ouutmode +) + +12  +£tv®ue + = 0x00; + +15 +£tv®ue + |ðÐ( +þockmode + << 10è| ( +Œigg”mode + << 7è| (( +ouutmode + & 0x01è<< 5è| (( +runmode + & 0x01) << 4) | 0x02 ); + +18  +chªÃl +) + +22 +TMCSR0 + = +£tv®ue +; + +27 +TMCSR1 + = +£tv®ue +; + +32 +TMCSR2 + = +£tv®ue +; + +37 +TMCSR3 + = +£tv®ue +; + +42 +TMCSR4 + = +£tv®ue +; + +47 +TMCSR5 + = +£tv®ue +; + +52 +TMCSR6 + = +£tv®ue +; + +57 +TMCSR7 + = +£tv®ue +; + +61 + } +} + +63  + $RLT_S‘R–ßdV®ue +( +chªÃl +,  +v®ue +) + +65  +chªÃl +) + +69 +TMRLR0 + = +v®ue +; + +74 +TMRLR1 + = +v®ue +; + +79 +TMRLR2 + = +v®ue +; + +84 +TMRLR3 + = +v®ue +; + +89 +TMRLR4 + = +v®ue +; + +94 +TMRLR5 + = +v®ue +; + +99 +TMRLR6 + = +v®ue +; + +104 +TMRLR7 + = +v®ue +; + +108 + } +} + +110  + $RLT_Trigg”Tim” +( +chªÃl +) + +112  +chªÃl +) + +116 +TMCSR0_TRG + = 1; + +121 +TMCSR1_TRG + = 1; + +126 +TMCSR2_TRG + = 1; + +131 +TMCSR3_TRG + = 1; + +136 +TMCSR4_TRG + = 1; + +141 +TMCSR5_TRG + = 1; + +146 +TMCSR6_TRG + = 1; + +151 +TMCSR7_TRG + = 1; + +155 + } +} + +157  + $RLT_EÇbËIÁ”ru± +( +chªÃl +) + +159  +chªÃl +) + +164 +TMCSR0_UF + = 0; + +167 +TMCSR0_INTE + = 1; + +173 +TMCSR1_UF + = 0; + +176 +TMCSR1_INTE + = 1; + +182 +TMCSR2_UF + = 0; + +185 +TMCSR2_INTE + = 1; + +191 +TMCSR3_UF + = 0; + +194 +TMCSR3_INTE + = 1; + +200 +TMCSR4_UF + = 0; + +203 +TMCSR4_INTE + = 1; + +209 +TMCSR5_UF + = 0; + +212 +TMCSR5_INTE + = 1; + +218 +TMCSR6_UF + = 0; + +221 +TMCSR6_INTE + = 1; + +227 +TMCSR7_UF + = 0; + +230 +TMCSR7_INTE + = 1; + +234 + } +} + +236 +__š‹¼u± +  + $RLT_ChªÃl0_ISR +() + +239 +TMCSR0_UF + = 0; + +242 +PDR27 +++; + +243 + } +} + +245 +__š‹¼u± +  + $RLT_ChªÃl1_ISR +() + +248 +TMCSR1_UF + = 0; + +251 + } +} + +253 +__š‹¼u± +  + $RLT_ChªÃl2_ISR +() + +256 +TMCSR2_UF + = 0; + +259 + } +} + +261 +__š‹¼u± +  + $RLT_ChªÃl3_ISR +() + +264 +TMCSR3_UF + = 0; + +267 + } +} + +269 +__š‹¼u± +  + $RLT_ChªÃl4_ISR +() + +272 +TMCSR4_UF + = 0; + +275 + } +} + +277 +__š‹¼u± +  + $RLT_ChªÃl5_ISR +() + +280 +TMCSR5_UF + = 0; + +283 + } +} + +285 +__š‹¼u± +  + $RLT_ChªÃl6_ISR +() + +288 +TMCSR6_UF + = 0; + +291 + } +} + +293 +__š‹¼u± +  + $RLT_ChªÃl7_ISR +() + +296 +TMCSR7_UF + = 0; + +299 + } +} + + @RLT.h + +8 #iâdeà +__RLT_H__ + + +9  + #__RLT_H__ + + + ) + +11  + ~"MB91465K.h +" + +13  + #RLT_RUNMODE_ONESHOT + 0x00 + + ) + +14  + #RLT_RUMMODE_RELOAD + 0x01 + + ) + +16  + #RLT_CLOCKMODE_DIV2 + 0x00 + + ) + +17  + #RLT_CLOCKMODE_DIV8 + 0x01 + + ) + +18  + #RLT_CLOCKMODE_DIV32 + 0x02 + + ) + +19  + #RLT_CLOCKMODE_EXT + 0x03 + + ) + +20  + #RLT_CLOCKMODE_DIV64 + 0x05 + + ) + +21  + #RLT_CLOCKMODE_DIV128 + 0x06 + + ) + +23  + #RLT_TRIGGER_SOFTWARE + 0x00 + + ) + +24  + #RLT_TRIGGER_EXT_FALLINGEDGE + 0x01 + + ) + +25  + #RLT_TRIGGER_EXT_RISINGEDGE + 0x02 + + ) + +26  + #RLT_TRIGGER_BOTHEDGES + 0x03 + + ) + +28  + #RLT_OUTOUTMODE_HIGHLEVEL + 0x00 + + ) + +29  + #RLT_OUTPUTMODE_LOWLEVEL + 0x01 + + ) + +31  +RLT_In™ŸlizeTim” +( +chªÃl +,  +runmode +,  +þockmode +,  +Œigg”mode +,  +ouutmode +); + +32  +RLT_S‘R–ßdV®ue +( +chªÃl +,  +v®ue +); + +33  +RLT_EÇbËIÁ”ru± +( +chªÃl +); + +34  +RLT_Trigg”Tim” +( +chªÃl +); + +36 +__š‹¼u± +  +RLT_ChªÃl0_ISR +(); + +37 +__š‹¼u± +  +RLT_ChªÃl1_ISR +(); + +38 +__š‹¼u± +  +RLT_ChªÃl2_ISR +(); + +39 +__š‹¼u± +  +RLT_ChªÃl3_ISR +(); + +40 +__š‹¼u± +  +RLT_ChªÃl4_ISR +(); + +41 +__š‹¼u± +  +RLT_ChªÃl5_ISR +(); + +42 +__š‹¼u± +  +RLT_ChªÃl6_ISR +(); + +43 +__š‹¼u± +  +RLT_ChªÃl7_ISR +(); + + @mb91465k.h + +32 #ifdeà +__IO_DEFINE + + +33  + #__IO_EXTERN + + + ) + +35  + #__IO_EXTERN + vÞ©že + + ) + +37 #ifdeà +__IO_DEFINE + + +38 #´agm¨ +asm + + +39 . +GLOBAL + +_pdr14 +, +_pdr15 +, +_pdr16 +, +_pdr17 +, +_pdr18 +, +_pdr19 + + +40 . +GLOBAL + +_pdr20 +, +_pdr21 +, +_pdr22 +, +_pdr24 +, +_pdr26 +, +_pdr27 + + +41 . +GLOBAL + +_pdr28 +, +_pdr29 +, +_eœr0 +, +_’œ0 +, +_–vr0 +, +_eœr1 + + +42 . +GLOBAL + +_’œ1 +, +_–vr1 +, +_diü +, +_hrþ +, +_rbsync +, +_sü00 + + +43 . +GLOBAL + +_smr00 +, +_s¤00 +, +_rdr00 +, +_tdr00 +, +_esü00 +, +_ecü00 + + +44 . +GLOBAL + +_sü01 +, +_smr01 +, +_s¤01 +, +_rdr01 +, +_tdr01 +, +_esü01 + + +45 . +GLOBAL + +_ecü01 +, +_sü02 +, +_smr02 +, +_s¤02 +, +_rdr02 +, +_tdr02 + + +46 . +GLOBAL + +_esü02 +, +_ecü02 +, +_sü03 +, +_smr03 +, +_s¤03 +, +_rdr03 + + +47 . +GLOBAL + +_tdr03 +, +_esü03 +, +_ecü03 +, +_sü04 +, +_smr04 +, +_s¤04 + + +48 . +GLOBAL + +_rdr04 +, +_tdr04 +, +_esü04 +, +_ecü04 +, +_f¤04 +, +_fü04 + + +49 . +GLOBAL + +_bgr00 +, +_bgr100 +, +_bgr000 +, +_bgr01 +, +_bgr101 +, +_bgr001 + + +50 . +GLOBAL + +_bgr02 +, +_bgr102 +, +_bgr002 +, +_bgr03 +, +_bgr103 +, +_bgr003 + + +51 . +GLOBAL + +_bgr04 +, +_bgr104 +, +_bgr004 +, +_ibü0 +, +_ib¤0 +, +_™ba0 + + +52 . +GLOBAL + +_™bah0 +, +_™b®0 +, +_™mk0 +, +_™mkh0 +, +_™mkl0 +, +_ismk0 + + +53 . +GLOBAL + +_isba0 +, +_id¬0 +, +_icü0 +, +_gú10 +, +_gú20 +, +_gú11 + + +54 . +GLOBAL + +_gú21 +, +_gú12 +, +_gú22 +, +_±mr00 +, +_pc¤00 +, +_pdut00 + + +55 . +GLOBAL + +_pú00 +, +_púh00 +, +_púl00 +, +_±mr01 +, +_pc¤01 +, +_pdut01 + + +56 . +GLOBAL + +_pú01 +, +_púh01 +, +_púl01 +, +_±mr02 +, +_pc¤02 +, +_pdut02 + + +57 . +GLOBAL + +_pú02 +, +_púh02 +, +_púl02 +, +_±mr03 +, +_pc¤03 +, +_pdut03 + + +58 . +GLOBAL + +_pú03 +, +_púh03 +, +_púl03 +, +_±mr04 +, +_pc¤04 +, +_pdut04 + + +59 . +GLOBAL + +_pú04 +, +_púh04 +, +_púl04 +, +_±mr05 +, +_pc¤05 +, +_pdut05 + + +60 . +GLOBAL + +_pú05 +, +_púh05 +, +_púl05 +, +_±mr06 +, +_pc¤06 +, +_pdut06 + + +61 . +GLOBAL + +_pú06 +, +_púh06 +, +_púl06 +, +_±mr07 +, +_pc¤07 +, +_pdut07 + + +62 . +GLOBAL + +_pú07 +, +_púh07 +, +_púl07 +, +_±mr08 +, +_pc¤08 +, +_pdut08 + + +63 . +GLOBAL + +_pú08 +, +_púh08 +, +_púl08 +, +_±mr09 +, +_pc¤09 +, +_pdut09 + + +64 . +GLOBAL + +_pú09 +, +_púh09 +, +_púl09 +, +_±mr10 +, +_pc¤10 +, +_pdut10 + + +65 . +GLOBAL + +_pú10 +, +_púh10 +, +_púl10 +, +_±mr11 +, +_pc¤11 +, +_pdut11 + + +66 . +GLOBAL + +_pú11 +, +_púh11 +, +_púl11 +, +_ics01 +, +_ics23 +, +_ý0 + + +67 . +GLOBAL + +_ý1 +, +_ý2 +, +_ý3 +, +_ocs01 +, +_ocs23 +, +_ocý0 + + +68 . +GLOBAL + +_ocý1 +, +_ocý2 +, +_ocý3 +, +_ad”h +, +_ad”l +, +_ad” + + +69 . +GLOBAL + +_adcs1 +, +_adcs0 +, +_adcs +, +_adü1 +, +_adü0 +, +_adü + + +70 . +GLOBAL + +_adù1 +, +_adù0 +, +_adù +, +_adsch +, +_adech +, +_tm¾r0 + + +71 . +GLOBAL + +_tmr0 +, +_tmc¤0 +, +_tmc¤h0 +, +_tmc¤l0 +, +_tm¾r1 +, +_tmr1 + + +72 . +GLOBAL + +_tmc¤1 +, +_tmc¤h1 +, +_tmc¤l1 +, +_tm¾r2 +, +_tmr2 +, +_tmc¤2 + + +73 . +GLOBAL + +_tmc¤h2 +, +_tmc¤l2 +, +_tm¾r3 +, +_tmr3 +, +_tmc¤3 +, +_tmc¤h3 + + +74 . +GLOBAL + +_tmc¤l3 +, +_tm¾r4 +, +_tmr4 +, +_tmc¤4 +, +_tmc¤h4 +, +_tmc¤l4 + + +75 . +GLOBAL + +_tm¾r5 +, +_tmr5 +, +_tmc¤5 +, +_tmc¤h5 +, +_tmc¤l5 +, +_tm¾r6 + + +76 . +GLOBAL + +_tmr6 +, +_tmc¤6 +, +_tmc¤h6 +, +_tmc¤l6 +, +_tm¾r7 +, +_tmr7 + + +77 . +GLOBAL + +_tmc¤7 +, +_tmc¤h7 +, +_tmc¤l7 +, +_tcdt0 +, +_tccs0 +, +_tcdt1 + + +78 . +GLOBAL + +_tccs1 +, +_tcdt2 +, +_tccs2 +, +_tcdt3 +, +_tccs3 +, +_dmaÿ0 + + +79 . +GLOBAL + +_dmacb0 +, +_dmaÿ1 +, +_dmacb1 +, +_dmaÿ2 +, +_dmacb2 +, +_dmaÿ3 + + +80 . +GLOBAL + +_dmacb3 +, +_dmaÿ4 +, +_dmacb4 +, +_dmaü +, +_ics45 +, +_ics67 + + +81 . +GLOBAL + +_ý4 +, +_ý5 +, +_ý6 +, +_ý7 +, +_ocs45 +, +_ocs67 + + +82 . +GLOBAL + +_ocý4 +, +_ocý5 +, +_ocý6 +, +_ocý7 +, +_tcdt4 +, +_tccs4 + + +83 . +GLOBAL + +_tcdt5 +, +_tccs5 +, +_tcdt6 +, +_tccs6 +, +_tcdt7 +, +_tccs7 + + +84 . +GLOBAL + +_roms +, +_bsd0 +, +_bsd1 +, +_bsdc +, +_b¤r +, +_iü00 + + +85 . +GLOBAL + +_iü01 +, +_iü02 +, +_iü03 +, +_iü04 +, +_iü05 +, +_iü06 + + +86 . +GLOBAL + +_iü07 +, +_iü08 +, +_iü09 +, +_iü10 +, +_iü11 +, +_iü12 + + +87 . +GLOBAL + +_iü13 +, +_iü14 +, +_iü15 +, +_iü16 +, +_iü17 +, +_iü18 + + +88 . +GLOBAL + +_iü19 +, +_iü20 +, +_iü21 +, +_iü22 +, +_iü23 +, +_iü24 + + +89 . +GLOBAL + +_iü25 +, +_iü26 +, +_iü27 +, +_iü28 +, +_iü29 +, +_iü30 + + +90 . +GLOBAL + +_iü31 +, +_iü32 +, +_iü33 +, +_iü34 +, +_iü35 +, +_iü36 + + +91 . +GLOBAL + +_iü37 +, +_iü38 +, +_iü39 +, +_iü40 +, +_iü41 +, +_iü42 + + +92 . +GLOBAL + +_iü43 +, +_iü44 +, +_iü45 +, +_iü46 +, +_iü47 +, +_iü48 + + +93 . +GLOBAL + +_iü49 +, +_iü50 +, +_iü51 +, +_iü52 +, +_iü53 +, +_iü54 + + +94 . +GLOBAL + +_iü55 +, +_iü56 +, +_iü57 +, +_iü58 +, +_iü59 +, +_iü60 + + +95 . +GLOBAL + +_iü61 +, +_iü62 +, +_iü63 +, +_r¤r +, +_¡ü +, +_tbü + + +96 . +GLOBAL + +_ùbr +, +_þkr +, +_w´ +, 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+_iü54 + + +1440 . +IMPORT + +_iü55 +, +_iü56 +, +_iü57 +, +_iü58 +, +_iü59 +, +_iü60 + + +1441 . +IMPORT + +_iü61 +, +_iü62 +, +_iü63 +, +_r¤r +, +_¡ü +, +_tbü + + +1442 . +IMPORT + +_ùbr +, +_þkr +, +_w´ +, +_divr0 +, +_divr1 +, +_¶ldivm + + +1443 . +IMPORT + +_¶ldivn +, +_¶ldivg +, +_¶lmulg +, +_¶lù¾ +, +_oscc1 +, +_oscs1 + + +1444 . +IMPORT + +_oscc2 +, +_oscs2 +, +_p܋n +, +_wtûr +, +_wtü +, +_wtbr + + +1445 . +IMPORT + +_wthr +, +_wtmr +, +_wt¤ +, +_csvŒ +, +_csvü +, +_cscfg + + +1446 . +IMPORT + +_cmcfg +, +_cuü +, +_cutd +, +_cuŒ1 +, +_cuŒ2 +, +_cm´ + + +1447 . +IMPORT + +_cmü +, +_cmt1 +, +_cmt2 +, +_ÿÅ» +, +_ÿnckd +, +_lv£l + + +1448 . +IMPORT + +_lvd‘ +, +_hwwde +, +_hwwd +, +_osüh +, +_osül +, +_wpüh + + +1449 . +IMPORT + +_wpül +, +_oscü +, +_»g£l +, +_»gùr +, +_modr +, +_pdrd14 + + +1450 . +IMPORT + +_pdrd15 +, +_pdrd16 +, +_pdrd17 +, +_pdrd18 +, +_pdrd19 +, +_pdrd20 + + +1451 . +IMPORT + +_pdrd21 +, +_pdrd22 +, +_pdrd24 +, +_pdrd26 +, +_pdrd27 +, +_pdrd28 + + +1452 . +IMPORT + +_pdrd29 +, +_ddr14 +, +_ddr15 +, +_ddr16 +, +_ddr17 +, +_ddr18 + + +1453 . +IMPORT + +_ddr19 +, +_ddr20 +, +_ddr21 +, +_ddr22 +, +_ddr24 +, +_ddr26 + + +1454 . +IMPORT + +_ddr27 +, +_ddr28 +, +_ddr29 +, +_pä14 +, +_pä15 +, +_pä16 + + +1455 . +IMPORT + +_pä17 +, +_pä18 +, +_pä19 +, +_pä20 +, +_pä21 +, +_pä22 + + +1456 . +IMPORT + +_pä24 +, +_pä26 +, +_pä27 +, +_pä28 +, +_pä29 +, +_•ä14 + + +1457 . +IMPORT + +_•ä15 +, +_•ä16 +, +_•ä17 +, +_•ä18 +, +_•ä19 +, +_•ä20 + + +1458 . +IMPORT + +_•ä21 +, +_•ä22 +, +_•ä24 +, +_•ä26 +, +_•ä27 +, +_•ä29 + + +1459 . +IMPORT + +_podr14 +, +_podr15 +, +_podr16 +, +_podr17 +, +_podr18 +, +_podr19 + + +1460 . +IMPORT + +_podr20 +, +_podr21 +, +_podr22 +, +_podr24 +, +_podr26 +, +_podr27 + + +1461 . +IMPORT + +_podr28 +, +_podr29 +, +_pžr14 +, +_pžr15 +, +_pžr16 +, +_pžr17 + + +1462 . +IMPORT + +_pžr18 +, +_pžr19 +, +_pžr20 +, +_pžr21 +, +_pžr22 +, +_pžr24 + + +1463 . +IMPORT + +_pžr26 +, +_pžr27 +, +_pžr28 +, +_pžr29 +, +_•žr14 +, +_•žr15 + + +1464 . +IMPORT + +_•žr16 +, +_•žr17 +, +_•žr18 +, +_•žr19 +, +_•žr20 +, +_•žr21 + + +1465 . +IMPORT + +_•žr22 +, +_•žr24 +, +_•žr26 +, +_•žr27 +, +_•žr28 +, +_•žr29 + + +1466 . +IMPORT + +_µ”14 +, +_µ”15 +, +_µ”16 +, +_µ”17 +, +_µ”18 +, +_µ”19 + + +1467 . +IMPORT + +_µ”20 +, +_µ”21 +, +_µ”22 +, +_µ”24 +, +_µ”26 +, +_µ”27 + + +1468 . +IMPORT + +_µ”28 +, +_µ”29 +, +_µü14 +, +_µü15 +, +_µü16 +, +_µü17 + + +1469 . +IMPORT + +_µü18 +, +_µü19 +, +_µü20 +, +_µü21 +, +_µü22 +, +_µü24 + + +1470 . +IMPORT + +_µü26 +, +_µü27 +, +_µü28 +, +_µü29 +, +_dma§0 +, +_dmada0 + + +1471 . +IMPORT + +_dma§1 +, +_dmada1 +, +_dma§2 +, +_dmada2 +, +_dma§3 +, +_dmada3 + + +1472 . +IMPORT + +_dma§4 +, +_dmada4 +, +_fmcs +, +_fmü +, +_fchü +, +_fmwt + + +1473 . +IMPORT + +_fmwt2 +, +_fmps +, +_fmac +, +_fcha0 +, +_fcha1 +, +_fsü0 + + +1474 . +IMPORT + +_fsü1 +, +_ù¾r4 +, +_¡©r4 +, +_”rút4 +, +_bŒ4 +, +_šŒ4 + + +1475 . +IMPORT + +_‹¡r4 +, +_b½”4 +, +_b½e4 +, +_if1üeq4 +, +_if1cmsk4 +, +_if1msk124 + + +1476 . +IMPORT + +_if1msk24 +, +_if1msk14 +, +_if1¬b124 +, +_if1¬b24 +, +_if1¬b14 +, +_if1mùr4 + + +1477 . +IMPORT + +_if1d124 +, +_if1d14 +, +_if1d24 +, +_if1dtb124 +, +_if1dtb14 +, +_if1dtb24 + + +1478 . +IMPORT + +_if1d_swp124 +, +_if1d_swp24 +, +_if1d_swp14 +, +_if1dtb_swp124 +, +_if1dtb_swp24 +, +_if1dtb_swp14 + + +1479 . +IMPORT + +_if2üeq4 +, +_if2cmsk4 +, +_if2msk124 +, +_if2msk24 +, +_if2msk14 +, +_if2¬b124 + + +1480 . +IMPORT + +_if2¬b24 +, +_if2¬b14 +, +_if2mùr4 +, +_if2d124 +, +_if2d14 +, +_if2d24 + + +1481 . +IMPORT + +_if2dtb124 +, +_if2dtb14 +, +_if2dtb24 +, +_if2d_swp124 +, +_if2d_swp24 +, +_if2d_swp14 + + +1482 . +IMPORT + +_if2dtb_swp124 +, +_if2dtb_swp24 +, +_if2dtb_swp14 +, +_Œeqr124 +, +_Œeqr24 +, +_Œeqr14 + + +1483 . +IMPORT + +_Œeqr344 +, +_Ãwdt124 +, +_Ãwdt24 +, +_Ãwdt14 +, +_šnd124 +, +_šnd24 + + +1484 . +IMPORT + +_šnd14 +, +_msgv®124 +, +_msgv®24 +, +_msgv®14 +, +_bù¾ +, +_b¡© + + +1485 . +IMPORT + +_bŸc +, +_bßc +, +_bœq +, +_bü0 +, +_bü1 +, +_bad0 + + +1486 . +IMPORT + +_bad1 +, +_bad2 +, +_bad3 +, +_bad4 +, +_bad5 +, +_bad6 + + +1487 . +IMPORT + +_bad7 +, +_fsv1 +, +_bsv1 +, +_fsv2 +, +_bsv2 + + +1488 #´agm¨ +’dasm + + +1514  + tIO_BYTE +; + +1515  + tIO_WORD +; + +1516  + tIO_LWORD +; + +1517 cÚ¡  + tIO_WORD_READ +; + +1520 +IO_BYTE + + mby‹ +; + +1522 +IO_BYTE + + m_D7 + :1; + +1523 +IO_BYTE + + m_D6 + :1; + +1524 +IO_BYTE + + m_D5 + :1; + +1525 +IO_BYTE + + m_D4 + :1; + +1526 +IO_BYTE + + m_D3 + :1; + +1527 +IO_BYTE + + m_D2 + :1; + +1528 +IO_BYTE + + m_D1 + :1; + +1529 +IO_BYTE + + m_D0 + :1; + +1530 } + mb™ +; + +1531 } + tPDR14STR +; + +1533 +IO_BYTE + + mby‹ +; + +1535 +IO_BYTE + + m_D7 + :1; + +1536 +IO_BYTE + + m_D6 + :1; + +1537 +IO_BYTE + + m_D5 + :1; + +1538 +IO_BYTE + + m_D4 + :1; + +1539 +IO_BYTE + + m_D3 + :1; + +1540 +IO_BYTE + + m_D2 + :1; + +1541 +IO_BYTE + + m_D1 + :1; + +1542 +IO_BYTE + + m_D0 + :1; + +1543 } + mb™ +; + +1544 } + tPDR15STR +; + +1546 +IO_BYTE + + mby‹ +; + +1548 +IO_BYTE + + m_D7 + :1; + +1549 +IO_BYTE + + m_D6 + :1; + +1550 +IO_BYTE + + m_D5 + :1; + +1551 +IO_BYTE + + m_D4 + :1; + +1552 +IO_BYTE + + m_D3 + :1; + +1553 +IO_BYTE + + m_D2 + :1; + +1554 +IO_BYTE + + m_D1 + :1; + +1555 +IO_BYTE + + m_D0 + :1; + +1556 } + mb™ +; + +1557 } + tPDR16STR +; + +1559 +IO_BYTE + + mby‹ +; + +1561 +IO_BYTE + + m_D7 + :1; + +1562 +IO_BYTE + + m_D6 + :1; + +1563 +IO_BYTE + + m_D5 + :1; + +1564 +IO_BYTE + + m_D4 + :1; + +1565 +IO_BYTE + + m_D3 + :1; + +1566 +IO_BYTE + + m_D2 + :1; + +1567 +IO_BYTE + + m_D1 + :1; + +1568 +IO_BYTE + + m_D0 + :1; + +1569 } + mb™ +; + +1570 } + tPDR17STR +; + +1572 +IO_BYTE + + mby‹ +; + +1574 + mIO_BYTE + :1; + +1575 +IO_BYTE + + m_D6 + :1; + +1576 + mIO_BYTE + :1; + +1577 + mIO_BYTE + :1; + +1578 + mIO_BYTE + :1; + +1579 +IO_BYTE + + m_D2 + :1; + +1580 + mIO_BYTE + :1; + +1581 + mIO_BYTE + :1; + +1582 } + mb™ +; + +1583 } + tPDR18STR +; + +1585 +IO_BYTE + + mby‹ +; + +1587 + mIO_BYTE + :1; + +1588 +IO_BYTE + + m_D6 + :1; + +1589 + mIO_BYTE + :1; + +1590 + mIO_BYTE + :1; + +1591 + mIO_BYTE + :1; + +1592 +IO_BYTE + + m_D2 + :1; + +1593 +IO_BYTE + + m_D1 + :1; + +1594 +IO_BYTE + + m_D0 + :1; + +1595 } + mb™ +; + +1596 } + tPDR19STR +; + +1598 +IO_BYTE + + mby‹ +; + +1600 +IO_BYTE + + m_D7 + :1; + +1601 +IO_BYTE + + m_D6 + :1; + +1602 +IO_BYTE + + m_D5 + :1; + +1603 +IO_BYTE + + m_D4 + :1; + +1604 +IO_BYTE + + m_D3 + :1; + +1605 +IO_BYTE + + m_D2 + :1; + +1606 +IO_BYTE + + m_D1 + :1; + +1607 +IO_BYTE + + m_D0 + :1; + +1608 } + mb™ +; + +1609 } + tPDR20STR +; + +1611 +IO_BYTE + + mby‹ +; + +1613 +IO_BYTE + + m_D7 + :1; + +1614 +IO_BYTE + + m_D6 + :1; + +1615 +IO_BYTE + + m_D5 + :1; + +1616 +IO_BYTE + + m_D4 + :1; + +1617 +IO_BYTE + + m_D3 + :1; + +1618 +IO_BYTE + + m_D2 + :1; + +1619 +IO_BYTE + + m_D1 + :1; + +1620 +IO_BYTE + + m_D0 + :1; + +1621 } + mb™ +; + +1622 } + tPDR21STR +; + +1624 +IO_BYTE + + mby‹ +; + +1626 + mIO_BYTE + :1; + +1627 + mIO_BYTE + :1; + +1628 +IO_BYTE + + m_D5 + :1; + +1629 +IO_BYTE + + m_D4 + :1; + +1630 + mIO_BYTE + :1; + +1631 + mIO_BYTE + :1; + +1632 +IO_BYTE + + m_D1 + :1; + +1633 +IO_BYTE + + m_D0 + :1; + +1634 } + mb™ +; + +1635 } + tPDR22STR +; + +1637 +IO_BYTE + + mby‹ +; + +1639 +IO_BYTE + + m_D7 + :1; + +1640 +IO_BYTE + + m_D6 + :1; + +1641 +IO_BYTE + + m_D5 + :1; + +1642 +IO_BYTE + + m_D4 + :1; + +1643 +IO_BYTE + + m_D3 + :1; + +1644 +IO_BYTE + + m_D2 + :1; + +1645 +IO_BYTE + + m_D1 + :1; + +1646 +IO_BYTE + + m_D0 + :1; + +1647 } + mb™ +; + +1648 } + tPDR24STR +; + +1650 +IO_BYTE + + mby‹ +; + +1652 + mIO_BYTE + :1; + +1653 + mIO_BYTE + :1; + +1654 + mIO_BYTE + :1; + +1655 + mIO_BYTE + :1; + +1656 + mIO_BYTE + :1; + +1657 + mIO_BYTE + :1; + +1658 +IO_BYTE + + m_D1 + :1; + +1659 +IO_BYTE + + m_D0 + :1; + +1660 } + mb™ +; + +1661 } + tPDR26STR +; + +1663 +IO_BYTE + + mby‹ +; + +1665 +IO_BYTE + + m_D7 + :1; + +1666 +IO_BYTE + + m_D6 + :1; + +1667 +IO_BYTE + + m_D5 + :1; + +1668 +IO_BYTE + + m_D4 + :1; + +1669 +IO_BYTE + + m_D3 + :1; + +1670 +IO_BYTE + + m_D2 + :1; + +1671 +IO_BYTE + + m_D1 + :1; + +1672 +IO_BYTE + + m_D0 + :1; + +1673 } + mb™ +; + +1674 } + tPDR27STR +; + +1676 +IO_BYTE + + mby‹ +; + +1678 +IO_BYTE + + m_D7 + :1; + +1679 +IO_BYTE + + m_D6 + :1; + +1680 +IO_BYTE + + m_D5 + :1; + +1681 +IO_BYTE + + m_D4 + :1; + +1682 +IO_BYTE + + m_D3 + :1; + +1683 +IO_BYTE + + m_D2 + :1; + +1684 +IO_BYTE + + m_D1 + :1; + +1685 +IO_BYTE + + m_D0 + :1; + +1686 } + mb™ +; + +1687 } + tPDR28STR +; + +1689 +IO_BYTE + + mby‹ +; + +1691 +IO_BYTE + + m_D7 + :1; + +1692 +IO_BYTE + + m_D6 + :1; + +1693 +IO_BYTE + + m_D5 + :1; + +1694 +IO_BYTE + + m_D4 + :1; + +1695 +IO_BYTE + + m_D3 + :1; + +1696 +IO_BYTE + + m_D2 + :1; + +1697 +IO_BYTE + + m_D1 + :1; + +1698 +IO_BYTE + + m_D0 + :1; + +1699 } + mb™ +; + +1700 } + tPDR29STR +; + +1702 +IO_BYTE + + mby‹ +; + +1704 +IO_BYTE + + m_ER7 + :1; + +1705 +IO_BYTE + + m_ER6 + :1; + +1706 +IO_BYTE + + m_ER5 + :1; + +1707 +IO_BYTE + + m_ER4 + :1; + +1708 +IO_BYTE + + m_ER3 + :1; + +1709 +IO_BYTE + + m_ER2 + :1; + +1710 +IO_BYTE + + m_ER1 + :1; + +1711 +IO_BYTE + + m_ER0 + :1; + +1712 } + mb™ +; + +1713 } + tEIRR0STR +; + +1715 +IO_BYTE + + mby‹ +; + +1717 +IO_BYTE + + m_EN7 + :1; + +1718 +IO_BYTE + + m_EN6 + :1; + +1719 +IO_BYTE + + m_EN5 + :1; + +1720 +IO_BYTE + + m_EN4 + :1; + +1721 +IO_BYTE + + m_EN3 + :1; + +1722 +IO_BYTE + + m_EN2 + :1; + +1723 +IO_BYTE + + m_EN1 + :1; + +1724 +IO_BYTE + + m_EN0 + :1; + +1725 } + mb™ +; + +1726 } + tENIR0STR +; + +1728 +IO_WORD + + mwÜd +; + +1730 +IO_WORD + + m_LB7 + :1; + +1731 +IO_WORD + + m_LA7 + :1; + +1732 +IO_WORD + + m_LB6 + :1; + +1733 +IO_WORD + + m_LA6 + :1; + +1734 +IO_WORD + + m_LB5 + :1; + +1735 +IO_WORD + + m_LA5 + :1; + +1736 +IO_WORD + + m_LB4 + :1; + +1737 +IO_WORD + + m_LA4 + :1; + +1738 +IO_WORD + + m_LB3 + :1; + +1739 +IO_WORD + + m_LA3 + :1; + +1740 +IO_WORD + + m_LB2 + :1; + +1741 +IO_WORD + + m_LA2 + :1; + +1742 +IO_WORD + + m_LB1 + :1; + +1743 +IO_WORD + + m_LA1 + :1; + +1744 +IO_WORD + + m_LB0 + :1; + +1745 +IO_WORD + + m_LA0 + :1; + +1746 } + mb™ +; + +1747 } + tELVR0STR +; + +1749 +IO_BYTE + + mby‹ +; + +1751 +IO_BYTE + + m_ER15 + :1; + +1752 +IO_BYTE + + m_ER14 + :1; + +1753 +IO_BYTE + + m_ER13 + :1; + +1754 +IO_BYTE + + m_ER12 + :1; + +1755 +IO_BYTE + + m_ER11 + :1; + +1756 +IO_BYTE + + m_ER10 + :1; + +1757 +IO_BYTE + + m_ER9 + :1; + +1758 +IO_BYTE + + m_ER8 + :1; + +1759 } + mb™ +; + +1760 } + tEIRR1STR +; + +1762 +IO_BYTE + + mby‹ +; + +1764 +IO_BYTE + + m_EN15 + :1; + +1765 +IO_BYTE + + m_EN14 + :1; + +1766 +IO_BYTE + + m_EN13 + :1; + +1767 +IO_BYTE + + m_EN12 + :1; + +1768 +IO_BYTE + + m_EN11 + :1; + +1769 +IO_BYTE + + m_EN10 + :1; + +1770 +IO_BYTE + + m_EN9 + :1; + +1771 +IO_BYTE + + m_EN8 + :1; + +1772 } + mb™ +; + +1773 } + tENIR1STR +; + +1775 +IO_WORD + + mwÜd +; + +1777 +IO_WORD + + m_LB15 + :1; + +1778 +IO_WORD + + m_LA15 + :1; + +1779 +IO_WORD + + m_LB14 + :1; + +1780 +IO_WORD + + m_LA14 + :1; + +1781 +IO_WORD + + m_LB13 + :1; + +1782 +IO_WORD + + m_LA13 + :1; + +1783 +IO_WORD + + m_LB12 + :1; + +1784 +IO_WORD + + m_LA12 + :1; + +1785 +IO_WORD + + m_LB11 + :1; + +1786 +IO_WORD + + m_LA11 + :1; + +1787 +IO_WORD + + m_LB10 + :1; + +1788 +IO_WORD + + m_LA10 + :1; + +1789 +IO_WORD + + m_LB9 + :1; + +1790 +IO_WORD + + m_LA9 + :1; + +1791 +IO_WORD + + m_LB8 + :1; + +1792 +IO_WORD + + m_LA8 + :1; + +1793 } + mb™ +; + +1794 } + tELVR1STR +; + +1796 +IO_BYTE + + mby‹ +; + +1798 + mIO_BYTE + :1; + +1799 + mIO_BYTE + :1; + +1800 + mIO_BYTE + :1; + +1801 + mIO_BYTE + :1; + +1802 + mIO_BYTE + :1; + +1803 + mIO_BYTE + :1; + +1804 + mIO_BYTE + :1; + +1805 +IO_BYTE + + m_DLYI + :1; + +1806 } + mb™ +; + +1807 } + tDICRSTR +; + +1809 +IO_BYTE + + mby‹ +; + +1811 +IO_BYTE + + m_MHALTI + :1; + +1812 + mIO_BYTE + :1; + +1813 + mIO_BYTE + :1; + +1814 +IO_BYTE + + m_LVL4 + :1; + +1815 +IO_BYTE + + m_LVL3 + :1; + +1816 +IO_BYTE + + m_LVL2 + :1; + +1817 +IO_BYTE + + m_LVL1 + :1; + +1818 +IO_BYTE + + m_LVL0 + :1; + +1819 } + mb™ +; + +1821 + mIO_BYTE + :1; + +1822 + mIO_BYTE + :1; + +1823 + mIO_BYTE + :1; + +1824 +IO_BYTE + + m_LVL + :5; + +1825 } + mb™c +; + +1826 } + tHRCLSTR +; + +1828 +IO_BYTE + + mby‹ +; + +1830 +IO_BYTE + + m_PEN + :1; + +1831 +IO_BYTE + + m_P + :1; + +1832 +IO_BYTE + + m_SBL + :1; + +1833 +IO_BYTE + + m_CL + :1; + +1834 +IO_BYTE + + m_AD + :1; + +1835 +IO_BYTE + + m_CRE + :1; + +1836 +IO_BYTE + + m_RXE + :1; + +1837 +IO_BYTE + + m_TXE + :1; + +1838 } + mb™ +; + +1839 } + tSCR00STR +; + +1841 +IO_BYTE + + mby‹ +; + +1843 +IO_BYTE + + m_MD1 + :1; + +1844 +IO_BYTE + + m_MD0 + :1; + +1845 +IO_BYTE + + m_OTO + :1; + +1846 +IO_BYTE + + m_EXT + :1; + +1847 +IO_BYTE + + m_REST + :1; + +1848 +IO_BYTE + + m_UPCL + :1; + +1849 +IO_BYTE + + m_SCKE + :1; + +1850 +IO_BYTE + + m_SOE + :1; + +1851 } + mb™ +; + +1853 +IO_BYTE + + m_MD + :2; + +1854 } + mb™c +; + +1855 } + tSMR00STR +; + +1857 +IO_BYTE + + mby‹ +; + +1859 +IO_BYTE + + m_PE + :1; + +1860 +IO_BYTE + + m_ORE + :1; + +1861 +IO_BYTE + + m_FRE + :1; + +1862 +IO_BYTE + + m_RDRF + :1; + +1863 +IO_BYTE + + m_TDRE + :1; + +1864 +IO_BYTE + + m_BDS + :1; + +1865 +IO_BYTE + + m_RIE + :1; + +1866 +IO_BYTE + + m_TIE + :1; + +1867 } + mb™ +; + +1868 } + tSSR00STR +; + +1870 +IO_BYTE + + mby‹ +; + +1872 +IO_BYTE + + m_LBIE + :1; + +1873 +IO_BYTE + + m_LBD + :1; + +1874 +IO_BYTE + + m_LBL1 + :1; + +1875 +IO_BYTE + + m_LBL0 + :1; + +1876 +IO_BYTE + + m_SOPE + :1; + +1877 +IO_BYTE + + m_SIOP + :1; + +1878 +IO_BYTE + + m_CCO + :1; + +1879 +IO_BYTE + + m_SCES + :1; + +1880 } + mb™ +; + +1882 + mIO_BYTE + :1; + +1883 + mIO_BYTE + :1; + +1884 +IO_BYTE + + m_LBL + :2; + +1885 } + mb™c +; + +1886 } + tESCR00STR +; + +1888 +IO_BYTE + + mby‹ +; + +1890 +IO_BYTE + + m_INV + :1; + +1891 +IO_BYTE + + m_LBR + :1; + +1892 +IO_BYTE + + m_MS + :1; + +1893 +IO_BYTE + + m_SCDE + :1; + +1894 +IO_BYTE + + m_SSM + :1; + +1895 +IO_BYTE + + m_BIE + :1; + +1896 +IO_BYTE + + m_RBI + :1; + +1897 +IO_BYTE + + m_TBI + :1; + +1898 } + mb™ +; + +1899 } + tECCR00STR +; + +1901 +IO_BYTE + + mby‹ +; + +1903 +IO_BYTE + + m_PEN + :1; + +1904 +IO_BYTE + + m_P + :1; + +1905 +IO_BYTE + + m_SBL + :1; + +1906 +IO_BYTE + + m_CL + :1; + +1907 +IO_BYTE + + m_AD + :1; + +1908 +IO_BYTE + + m_CRE + :1; + +1909 +IO_BYTE + + m_RXE + :1; + +1910 +IO_BYTE + + m_TXE + :1; + +1911 } + mb™ +; + +1912 } + tSCR01STR +; + +1914 +IO_BYTE + + mby‹ +; + +1916 +IO_BYTE + + m_MD1 + :1; + +1917 +IO_BYTE + + m_MD0 + :1; + +1918 +IO_BYTE + + m_OTO + :1; + +1919 +IO_BYTE + + m_EXT + :1; + +1920 +IO_BYTE + + m_REST + :1; + +1921 +IO_BYTE + + m_UPCL + :1; + +1922 +IO_BYTE + + m_SCKE + :1; + +1923 +IO_BYTE + + m_SOE + :1; + +1924 } + mb™ +; + +1926 +IO_BYTE + + m_MD + :2; + +1927 } + mb™c +; + +1928 } + tSMR01STR +; + +1930 +IO_BYTE + + mby‹ +; + +1932 +IO_BYTE + + m_PE + :1; + +1933 +IO_BYTE + + m_ORE + :1; + +1934 +IO_BYTE + + m_FRE + :1; + +1935 +IO_BYTE + + m_RDRF + :1; + +1936 +IO_BYTE + + m_TDRE + :1; + +1937 +IO_BYTE + + m_BDS + :1; + +1938 +IO_BYTE + + m_RIE + :1; + +1939 +IO_BYTE + + m_TIE + :1; + +1940 } + mb™ +; + +1941 } + tSSR01STR +; + +1943 +IO_BYTE + + mby‹ +; + +1945 +IO_BYTE + + m_LBIE + :1; + +1946 +IO_BYTE + + m_LBD + :1; + +1947 +IO_BYTE + + m_LBL1 + :1; + +1948 +IO_BYTE + + m_LBL0 + :1; + +1949 +IO_BYTE + + m_SOPE + :1; + +1950 +IO_BYTE + + m_SIOP + :1; + +1951 +IO_BYTE + + m_CCO + :1; + +1952 +IO_BYTE + + m_SCES + :1; + +1953 } + mb™ +; + +1955 + mIO_BYTE + :1; + +1956 + mIO_BYTE + :1; + +1957 +IO_BYTE + + m_LBL + :2; + +1958 } + mb™c +; + +1959 } + tESCR01STR +; + +1961 +IO_BYTE + + mby‹ +; + +1963 +IO_BYTE + + m_INV + :1; + +1964 +IO_BYTE + + m_LBR + :1; + +1965 +IO_BYTE + + m_MS + :1; + +1966 +IO_BYTE + + m_SCDE + :1; + +1967 +IO_BYTE + + m_SSM + :1; + +1968 +IO_BYTE + + m_BIE + :1; + +1969 +IO_BYTE + + m_RBI + :1; + +1970 +IO_BYTE + + m_TBI + :1; + +1971 } + mb™ +; + +1972 } + tECCR01STR +; + +1974 +IO_BYTE + + mby‹ +; + +1976 +IO_BYTE + + m_PEN + :1; + +1977 +IO_BYTE + + m_P + :1; + +1978 +IO_BYTE + + m_SBL + :1; + +1979 +IO_BYTE + + m_CL + :1; + +1980 +IO_BYTE + + m_AD + :1; + +1981 +IO_BYTE + + m_CRE + :1; + +1982 +IO_BYTE + + m_RXE + :1; + +1983 +IO_BYTE + + m_TXE + :1; + +1984 } + mb™ +; + +1985 } + tSCR02STR +; + +1987 +IO_BYTE + + mby‹ +; + +1989 +IO_BYTE + + m_MD1 + :1; + +1990 +IO_BYTE + + m_MD0 + :1; + +1991 +IO_BYTE + + m_OTO + :1; + +1992 +IO_BYTE + + m_EXT + :1; + +1993 +IO_BYTE + + m_REST + :1; + +1994 +IO_BYTE + + m_UPCL + :1; + +1995 +IO_BYTE + + m_SCKE + :1; + +1996 +IO_BYTE + + m_SOE + :1; + +1997 } + mb™ +; + +1999 +IO_BYTE + + m_MD + :2; + +2000 } + mb™c +; + +2001 } + tSMR02STR +; + +2003 +IO_BYTE + + mby‹ +; + +2005 +IO_BYTE + + m_PE + :1; + +2006 +IO_BYTE + + m_ORE + :1; + +2007 +IO_BYTE + + m_FRE + :1; + +2008 +IO_BYTE + + m_RDRF + :1; + +2009 +IO_BYTE + + m_TDRE + :1; + +2010 +IO_BYTE + + m_BDS + :1; + +2011 +IO_BYTE + + m_RIE + :1; + +2012 +IO_BYTE + + m_TIE + :1; + +2013 } + mb™ +; + +2014 } + tSSR02STR +; + +2016 +IO_BYTE + + mby‹ +; + +2018 +IO_BYTE + + m_LBIE + :1; + +2019 +IO_BYTE + + m_LBD + :1; + +2020 +IO_BYTE + + m_LBL1 + :1; + +2021 +IO_BYTE + + m_LBL0 + :1; + +2022 +IO_BYTE + + m_SOPE + :1; + +2023 +IO_BYTE + + m_SIOP + :1; + +2024 +IO_BYTE + + m_CCO + :1; + +2025 +IO_BYTE + + m_SCES + :1; + +2026 } + mb™ +; + +2028 + mIO_BYTE + :1; + +2029 + mIO_BYTE + :1; + +2030 +IO_BYTE + + m_LBL + :2; + +2031 } + mb™c +; + +2032 } + tESCR02STR +; + +2034 +IO_BYTE + + mby‹ +; + +2036 +IO_BYTE + + m_INV + :1; + +2037 +IO_BYTE + + m_LBR + :1; + +2038 +IO_BYTE + + m_MS + :1; + +2039 +IO_BYTE + + m_SCDE + :1; + +2040 +IO_BYTE + + m_SSM + :1; + +2041 +IO_BYTE + + m_BIE + :1; + +2042 +IO_BYTE + + m_RBI + :1; + +2043 +IO_BYTE + + m_TBI + :1; + +2044 } + mb™ +; + +2045 } + tECCR02STR +; + +2047 +IO_BYTE + + mby‹ +; + +2049 +IO_BYTE + + m_PEN + :1; + +2050 +IO_BYTE + + m_P + :1; + +2051 +IO_BYTE + + m_SBL + :1; + +2052 +IO_BYTE + + m_CL + :1; + +2053 +IO_BYTE + + m_AD + :1; + +2054 +IO_BYTE + + m_CRE + :1; + +2055 +IO_BYTE + + m_RXE + :1; + +2056 +IO_BYTE + + m_TXE + :1; + +2057 } + mb™ +; + +2058 } + tSCR03STR +; + +2060 +IO_BYTE + + mby‹ +; + +2062 +IO_BYTE + + m_MD1 + :1; + +2063 +IO_BYTE + + m_MD0 + :1; + +2064 +IO_BYTE + + m_OTO + :1; + +2065 +IO_BYTE + + m_EXT + :1; + +2066 +IO_BYTE + + m_REST + :1; + +2067 +IO_BYTE + + m_UPCL + :1; + +2068 +IO_BYTE + + m_SCKE + :1; + +2069 +IO_BYTE + + m_SOE + :1; + +2070 } + mb™ +; + +2072 +IO_BYTE + + m_MD + :2; + +2073 } + mb™c +; + +2074 } + tSMR03STR +; + +2076 +IO_BYTE + + mby‹ +; + +2078 +IO_BYTE + + m_PE + :1; + +2079 +IO_BYTE + + m_ORE + :1; + +2080 +IO_BYTE + + m_FRE + :1; + +2081 +IO_BYTE + + m_RDRF + :1; + +2082 +IO_BYTE + + m_TDRE + :1; + +2083 +IO_BYTE + + m_BDS + :1; + +2084 +IO_BYTE + + m_RIE + :1; + +2085 +IO_BYTE + + m_TIE + :1; + +2086 } + mb™ +; + +2087 } + tSSR03STR +; + +2089 +IO_BYTE + + mby‹ +; + +2091 +IO_BYTE + + m_LBIE + :1; + +2092 +IO_BYTE + + m_LBD + :1; + +2093 +IO_BYTE + + m_LBL1 + :1; + +2094 +IO_BYTE + + m_LBL0 + :1; + +2095 +IO_BYTE + + m_SOPE + :1; + +2096 +IO_BYTE + + m_SIOP + :1; + +2097 +IO_BYTE + + m_CCO + :1; + +2098 +IO_BYTE + + m_SCES + :1; + +2099 } + mb™ +; + +2101 + mIO_BYTE + :1; + +2102 + mIO_BYTE + :1; + +2103 +IO_BYTE + + m_LBL + :2; + +2104 } + mb™c +; + +2105 } + tESCR03STR +; + +2107 +IO_BYTE + + mby‹ +; + +2109 +IO_BYTE + + m_INV + :1; + +2110 +IO_BYTE + + m_LBR + :1; + +2111 +IO_BYTE + + m_MS + :1; + +2112 +IO_BYTE + + m_SCDE + :1; + +2113 +IO_BYTE + + m_SSM + :1; + +2114 +IO_BYTE + + m_BIE + :1; + +2115 +IO_BYTE + + m_RBI + :1; + +2116 +IO_BYTE + + m_TBI + :1; + +2117 } + mb™ +; + +2118 } + tECCR03STR +; + +2120 +IO_BYTE + + mby‹ +; + +2122 +IO_BYTE + + m_PEN + :1; + +2123 +IO_BYTE + + m_P + :1; + +2124 +IO_BYTE + + m_SBL + :1; + +2125 +IO_BYTE + + m_CL + :1; + +2126 +IO_BYTE + + m_AD + :1; + +2127 +IO_BYTE + + m_CRE + :1; + +2128 +IO_BYTE + + m_RXE + :1; + +2129 +IO_BYTE + + m_TXE + :1; + +2130 } + mb™ +; + +2131 } + tSCR04STR +; + +2133 +IO_BYTE + + mby‹ +; + +2135 +IO_BYTE + + m_MD1 + :1; + +2136 +IO_BYTE + + m_MD0 + :1; + +2137 +IO_BYTE + + m_OTO + :1; + +2138 +IO_BYTE + + m_EXT + :1; + +2139 +IO_BYTE + + m_REST + :1; + +2140 +IO_BYTE + + m_UPCL + :1; + +2141 +IO_BYTE + + m_SCKE + :1; + +2142 +IO_BYTE + + m_SOE + :1; + +2143 } + mb™ +; + +2145 +IO_BYTE + + m_MD + :2; + +2146 } + mb™c +; + +2147 } + tSMR04STR +; + +2149 +IO_BYTE + + mby‹ +; + +2151 +IO_BYTE + + m_PE + :1; + +2152 +IO_BYTE + + m_ORE + :1; + +2153 +IO_BYTE + + m_FRE + :1; + +2154 +IO_BYTE + + m_RDRF + :1; + +2155 +IO_BYTE + + m_TDRE + :1; + +2156 +IO_BYTE + + m_BDS + :1; + +2157 +IO_BYTE + + m_RIE + :1; + +2158 +IO_BYTE + + m_TIE + :1; + +2159 } + mb™ +; + +2160 } + tSSR04STR +; + +2162 +IO_BYTE + + mby‹ +; + +2164 +IO_BYTE + + m_LBIE + :1; + +2165 +IO_BYTE + + m_LBD + :1; + +2166 +IO_BYTE + + m_LBL1 + :1; + +2167 +IO_BYTE + + m_LBL0 + :1; + +2168 +IO_BYTE + + m_SOPE + :1; + +2169 +IO_BYTE + + m_SIOP + :1; + +2170 +IO_BYTE + + m_CCO + :1; + +2171 +IO_BYTE + + m_SCES + :1; + +2172 } + mb™ +; + +2174 + mIO_BYTE + :1; + +2175 + mIO_BYTE + :1; + +2176 +IO_BYTE + + m_LBL + :2; + +2177 } + mb™c +; + +2178 } + tESCR04STR +; + +2180 +IO_BYTE + + mby‹ +; + +2182 +IO_BYTE + + m_INV + :1; + +2183 +IO_BYTE + + m_LBR + :1; + +2184 +IO_BYTE + + m_MS + :1; + +2185 +IO_BYTE + + m_SCDE + :1; + +2186 +IO_BYTE + + m_SSM + :1; + +2187 +IO_BYTE + + m_BIE + :1; + +2188 +IO_BYTE + + m_RBI + :1; + +2189 +IO_BYTE + + m_TBI + :1; + +2190 } + mb™ +; + +2191 } + tECCR04STR +; + +2193 +IO_BYTE + + mby‹ +; + +2195 +IO_BYTE + + m_RXL3 + :1; + +2196 +IO_BYTE + + m_RXL2 + :1; + +2197 +IO_BYTE + + m_RXL1 + :1; + +2198 +IO_BYTE + + m_RXL0 + :1; + +2199 + mIO_BYTE + :1; + +2200 +IO_BYTE + + m_ERX + :1; + +2201 +IO_BYTE + + m_ETX + :1; + +2202 +IO_BYTE + + m_SVD + :1; + +2203 } + mb™ +; + +2205 +IO_BYTE + + m_RXL + :4; + +2206 } + mb™c +; + +2207 } + tFCR04STR +; + +2209 +IO_BYTE + + mby‹ +; + +2211 +IO_BYTE + + m_BER + :1; + +2212 +IO_BYTE + + m_BEIE + :1; + +2213 +IO_BYTE + + m_SCC + :1; + +2214 +IO_BYTE + + m_MSS + :1; + +2215 +IO_BYTE + + m_ACK + :1; + +2216 +IO_BYTE + + m_GCAA + :1; + +2217 +IO_BYTE + + m_INTE + :1; + +2218 +IO_BYTE + + m_INT + :1; + +2219 } + mb™ +; + +2220 } + tIBCR0STR +; + +2222 +IO_BYTE + + mby‹ +; + +2224 +IO_BYTE + + m_BB + :1; + +2225 +IO_BYTE + + m_RSC + :1; + +2226 +IO_BYTE + + m_AL + :1; + +2227 +IO_BYTE + + m_LRB + :1; + +2228 +IO_BYTE + + m_TRX + :1; + +2229 +IO_BYTE + + m_AAS + :1; + +2230 +IO_BYTE + + m_GCA + :1; + +2231 +IO_BYTE + + m_ADT + :1; + +2232 } + mb™ +; + +2233 } + tIBSR0STR +; + +2235 +IO_WORD + + mwÜd +; + +2237 + mIO_WORD + :1; + +2238 + mIO_WORD + :1; + +2239 + mIO_WORD + :1; + +2240 + mIO_WORD + :1; + +2241 + mIO_WORD + :1; + +2242 + mIO_WORD + :1; + +2243 +IO_WORD + + m_TA9 + :1; + +2244 +IO_WORD + + m_TA8 + :1; + +2245 +IO_WORD + + m_TA7 + :1; + +2246 +IO_WORD + + m_TA6 + :1; + +2247 +IO_WORD + + m_TA5 + :1; + +2248 +IO_WORD + + m_TA4 + :1; + +2249 +IO_WORD + + m_TA3 + :1; + +2250 +IO_WORD + + m_TA2 + :1; + +2251 +IO_WORD + + m_TA1 + :1; + +2252 +IO_WORD + + m_TA0 + :1; + +2253 } + mb™ +; + +2254 } + tITBA0STR +; + +2256 +IO_BYTE + + mby‹ +; + +2258 + mIO_BYTE + :1; + +2259 + mIO_BYTE + :1; + +2260 + mIO_BYTE + :1; + +2261 + mIO_BYTE + :1; + +2262 + mIO_BYTE + :1; + +2263 + mIO_BYTE + :1; + +2264 +IO_BYTE + + m_TA9 + :1; + +2265 +IO_BYTE + + m_TA8 + :1; + +2266 } + mb™ +; + +2267 } + tITBAH0STR +; + +2269 +IO_BYTE + + mby‹ +; + +2271 +IO_BYTE + + m_TA7 + :1; + +2272 +IO_BYTE + + m_TA6 + :1; + +2273 +IO_BYTE + + m_TA5 + :1; + +2274 +IO_BYTE + + m_TA4 + :1; + +2275 +IO_BYTE + + m_TA3 + :1; + +2276 +IO_BYTE + + m_TA2 + :1; + +2277 +IO_BYTE + + m_TA1 + :1; + +2278 +IO_BYTE + + m_TA0 + :1; + +2279 } + mb™ +; + +2280 } + tITBAL0STR +; + +2282 +IO_WORD + + mwÜd +; + +2284 +IO_WORD + + m_ENTB + :1; + +2285 +IO_WORD + + m_RAL + :1; + +2286 + mIO_WORD + :1; + +2287 + mIO_WORD + :1; + +2288 + mIO_WORD + :1; + +2289 + mIO_WORD + :1; + +2290 +IO_WORD + + m_TM9 + :1; + +2291 +IO_WORD + + m_TM8 + :1; + +2292 +IO_WORD + + m_TM7 + :1; + +2293 +IO_WORD + + m_TM6 + :1; + +2294 +IO_WORD + + m_TM5 + :1; + +2295 +IO_WORD + + m_TM4 + :1; + +2296 +IO_WORD + + m_TM3 + :1; + +2297 +IO_WORD + + m_TM2 + :1; + +2298 +IO_WORD + + m_TM1 + :1; + +2299 +IO_WORD + + m_TM0 + :1; + +2300 } + mb™ +; + +2301 } + tITMK0STR +; + +2303 +IO_BYTE + + mby‹ +; + +2305 +IO_BYTE + + m_ENTB + :1; + +2306 +IO_BYTE + + m_RAL + :1; + +2307 + mIO_BYTE + :1; + +2308 + mIO_BYTE + :1; + +2309 + mIO_BYTE + :1; + +2310 + mIO_BYTE + :1; + +2311 +IO_BYTE + + m_TM9 + :1; + +2312 +IO_BYTE + + m_TM8 + :1; + +2313 } + mb™ +; + +2314 } + tITMKH0STR +; + +2316 +IO_BYTE + + mby‹ +; + +2318 +IO_BYTE + + m_TM7 + :1; + +2319 +IO_BYTE + + m_TM6 + :1; + +2320 +IO_BYTE + + m_TM5 + :1; + +2321 +IO_BYTE + + m_TM4 + :1; + +2322 +IO_BYTE + + m_TM3 + :1; + +2323 +IO_BYTE + + m_TM2 + :1; + +2324 +IO_BYTE + + m_TM1 + :1; + +2325 +IO_BYTE + + m_TM0 + :1; + +2326 } + mb™ +; + +2327 } + tITMKL0STR +; + +2329 +IO_BYTE + + mby‹ +; + +2331 +IO_BYTE + + m_ENSB + :1; + +2332 +IO_BYTE + + m_SM6 + :1; + +2333 +IO_BYTE + + m_SM5 + :1; + +2334 +IO_BYTE + + m_SM4 + :1; + +2335 +IO_BYTE + + m_SM3 + :1; + +2336 +IO_BYTE + + m_SM2 + :1; + +2337 +IO_BYTE + + m_SM1 + :1; + +2338 +IO_BYTE + + m_SM0 + :1; + +2339 } + mb™ +; + +2340 } + tISMK0STR +; + +2342 +IO_BYTE + + mby‹ +; + +2344 + mIO_BYTE + :1; + +2345 +IO_BYTE + + m_SA6 + :1; + +2346 +IO_BYTE + + m_SA5 + :1; + +2347 +IO_BYTE + + m_SA4 + :1; + +2348 +IO_BYTE + + m_SA3 + :1; + +2349 +IO_BYTE + + m_SA2 + :1; + +2350 +IO_BYTE + + m_SA1 + :1; + +2351 +IO_BYTE + + m_SA0 + :1; + +2352 } + mb™ +; + +2353 } + tISBA0STR +; + +2355 +IO_BYTE + + mby‹ +; + +2357 +IO_BYTE + + m_D7 + :1; + +2358 +IO_BYTE + + m_D6 + :1; + +2359 +IO_BYTE + + m_D5 + :1; + +2360 +IO_BYTE + + m_D4 + :1; + +2361 +IO_BYTE + + m_D3 + :1; + +2362 +IO_BYTE + + m_D2 + :1; + +2363 +IO_BYTE + + m_D1 + :1; + +2364 +IO_BYTE + + m_D0 + :1; + +2365 } + mb™ +; + +2366 } + tIDAR0STR +; + +2368 +IO_BYTE + + mby‹ +; + +2370 + mIO_BYTE + :1; + +2371 +IO_BYTE + + m_NSF + :1; + +2372 +IO_BYTE + + m_EN + :1; + +2373 +IO_BYTE + + m_CS4 + :1; + +2374 +IO_BYTE + + m_CS3 + :1; + +2375 +IO_BYTE + + m_CS2 + :1; + +2376 +IO_BYTE + + m_CS1 + :1; + +2377 +IO_BYTE + + m_CS0 + :1; + +2378 } + mb™ +; + +2380 + mIO_BYTE + :1; + +2381 + mIO_BYTE + :1; + +2382 + mIO_BYTE + :1; + +2383 +IO_BYTE + + m_CS + :5; + +2384 } + mb™c +; + +2385 } + tICCR0STR +; + +2387 +IO_WORD + + mwÜd +; + +2389 +IO_WORD + + m_TSEL33 + :1; + +2390 +IO_WORD + + m_TSEL32 + :1; + +2391 +IO_WORD + + m_TSEL31 + :1; + +2392 +IO_WORD + + m_TSEL30 + :1; + +2393 +IO_WORD + + m_TSEL23 + :1; + +2394 +IO_WORD + + m_TSEL22 + :1; + +2395 +IO_WORD + + m_TSEL21 + :1; + +2396 +IO_WORD + + m_TSEL20 + :1; + +2397 +IO_WORD + + m_TSEL13 + :1; + +2398 +IO_WORD + + m_TSEL12 + :1; + +2399 +IO_WORD + + m_TSEL11 + :1; + +2400 +IO_WORD + + m_TSEL10 + :1; + +2401 +IO_WORD + + m_TSEL03 + :1; + +2402 +IO_WORD + + m_TSEL02 + :1; + +2403 +IO_WORD + + m_TSEL01 + :1; + +2404 +IO_WORD + + m_TSEL00 + :1; + +2405 } + mb™ +; + +2406 } + tGCN10STR +; + +2408 +IO_BYTE + + mby‹ +; + +2410 + mIO_BYTE + :1; + +2411 + mIO_BYTE + :1; + +2412 + mIO_BYTE + :1; + +2413 + mIO_BYTE + :1; + +2414 +IO_BYTE + + m_EN3 + :1; + +2415 +IO_BYTE + + m_EN2 + :1; + +2416 +IO_BYTE + + m_EN1 + :1; + +2417 +IO_BYTE + + m_EN0 + :1; + +2418 } + mb™ +; + +2419 } + tGCN20STR +; + +2421 +IO_WORD + + mwÜd +; + +2423 +IO_WORD + + m_TSEL33 + :1; + +2424 +IO_WORD + + m_TSEL32 + :1; + +2425 +IO_WORD + + m_TSEL31 + :1; + +2426 +IO_WORD + + m_TSEL30 + :1; + +2427 +IO_WORD + + m_TSEL23 + :1; + +2428 +IO_WORD + + m_TSEL22 + :1; + +2429 +IO_WORD + + m_TSEL21 + :1; + +2430 +IO_WORD + + m_TSEL20 + :1; + +2431 +IO_WORD + + m_TSEL13 + :1; + +2432 +IO_WORD + + m_TSEL12 + :1; + +2433 +IO_WORD + + m_TSEL11 + :1; + +2434 +IO_WORD + + m_TSEL10 + :1; + +2435 +IO_WORD + + m_TSEL03 + :1; + +2436 +IO_WORD + + m_TSEL02 + :1; + +2437 +IO_WORD + + m_TSEL01 + :1; + +2438 +IO_WORD + + m_TSEL00 + :1; + +2439 } + mb™ +; + +2440 } + tGCN11STR +; + +2442 +IO_BYTE + + mby‹ +; + +2444 + mIO_BYTE + :1; + +2445 + mIO_BYTE + :1; + +2446 + mIO_BYTE + :1; + +2447 + mIO_BYTE + :1; + +2448 +IO_BYTE + + m_EN3 + :1; + +2449 +IO_BYTE + + m_EN2 + :1; + +2450 +IO_BYTE + + m_EN1 + :1; + +2451 +IO_BYTE + + m_EN0 + :1; + +2452 } + mb™ +; + +2453 } + tGCN21STR +; + +2455 +IO_WORD + + mwÜd +; + +2457 +IO_WORD + + m_TSEL33 + :1; + +2458 +IO_WORD + + m_TSEL32 + :1; + +2459 +IO_WORD + + m_TSEL31 + :1; + +2460 +IO_WORD + + m_TSEL30 + :1; + +2461 +IO_WORD + + m_TSEL23 + :1; + +2462 +IO_WORD + + m_TSEL22 + :1; + +2463 +IO_WORD + + m_TSEL21 + :1; + +2464 +IO_WORD + + m_TSEL20 + :1; + +2465 +IO_WORD + + m_TSEL13 + :1; + +2466 +IO_WORD + + m_TSEL12 + :1; + +2467 +IO_WORD + + m_TSEL11 + :1; + +2468 +IO_WORD + + m_TSEL10 + :1; + +2469 +IO_WORD + + m_TSEL03 + :1; + +2470 +IO_WORD + + m_TSEL02 + :1; + +2471 +IO_WORD + + m_TSEL01 + :1; + +2472 +IO_WORD + + m_TSEL00 + :1; + +2473 } + mb™ +; + +2474 } + tGCN12STR +; + +2476 +IO_BYTE + + mby‹ +; + +2478 + mIO_BYTE + :1; + +2479 + mIO_BYTE + :1; + +2480 + mIO_BYTE + :1; + +2481 + mIO_BYTE + :1; + +2482 +IO_BYTE + + m_EN3 + :1; + +2483 +IO_BYTE + + m_EN2 + :1; + +2484 +IO_BYTE + + m_EN1 + :1; + +2485 +IO_BYTE + + m_EN0 + :1; + +2486 } + mb™ +; + +2487 } + tGCN22STR +; + +2489 +IO_WORD + + mwÜd +; + +2491 +IO_WORD + + m_CNTE + :1; + +2492 +IO_WORD + + m_STGR + :1; + +2493 +IO_WORD + + m_MDSE + :1; + +2494 +IO_WORD + + m_RTRG + :1; + +2495 +IO_WORD + + m_CKS1 + :1; + +2496 +IO_WORD + + m_CKS0 + :1; + +2497 +IO_WORD + + m_PGMS + :1; + +2498 + mIO_WORD + :1; + +2499 +IO_WORD + + m_EGS1 + :1; + +2500 +IO_WORD + + m_EGS0 + :1; + +2501 +IO_WORD + + m_IREN + :1; + +2502 +IO_WORD + + m_IRQF + :1; + +2503 +IO_WORD + + m_IRS1 + :1; + +2504 +IO_WORD + + m_IRS0 + :1; + +2505 + mIO_WORD + :1; + +2506 +IO_WORD + + m_OSEL + :1; + +2507 } + mb™ +; + +2509 + mIO_WORD + :1; + +2510 + mIO_WORD + :1; + +2511 + mIO_WORD + :1; + +2512 + mIO_WORD + :1; + +2513 +IO_WORD + + m_CKS + :2; + +2514 + mIO_WORD + :1; + +2515 + mIO_WORD + :1; + +2516 +IO_WORD + + m_EGS + :2; + +2517 + mIO_WORD + :1; + +2518 + mIO_WORD + :1; + +2519 +IO_WORD + + m_IRS + :2; + +2520 } + mb™c +; + +2521 } + tPCN00STR +; + +2523 +IO_BYTE + + mby‹ +; + +2525 +IO_BYTE + + m_CNTE + :1; + +2526 +IO_BYTE + + m_STGR + :1; + +2527 +IO_BYTE + + m_MDSE + :1; + +2528 +IO_BYTE + + m_RTRG + :1; + +2529 +IO_BYTE + + m_CKS1 + :1; + +2530 +IO_BYTE + + m_CKS0 + :1; + +2531 +IO_BYTE + + m_PGMS + :1; + +2532 + mIO_BYTE + :1; + +2533 } + mb™ +; + +2535 + mIO_BYTE + :1; + +2536 + mIO_BYTE + :1; + +2537 + mIO_BYTE + :1; + +2538 + mIO_BYTE + :1; + +2539 +IO_BYTE + + m_CKS + :2; + +2540 } + mb™c +; + +2541 } + tPCNH00STR +; + +2543 +IO_BYTE + + mby‹ +; + +2545 +IO_BYTE + + m_EGS1 + :1; + +2546 +IO_BYTE + + m_EGS0 + :1; + +2547 +IO_BYTE + + m_IREN + :1; + +2548 +IO_BYTE + + m_IRQF + :1; + +2549 +IO_BYTE + + m_IRS1 + :1; + +2550 +IO_BYTE + + m_IRS0 + :1; + +2551 + mIO_BYTE + :1; + +2552 +IO_BYTE + + m_OSEL + :1; + +2553 } + mb™ +; + +2555 +IO_BYTE + + m_EGS + :2; + +2556 + mIO_BYTE + :1; + +2557 + mIO_BYTE + :1; + +2558 +IO_BYTE + + m_IRS + :2; + +2559 } + mb™c +; + +2560 } + tPCNL00STR +; + +2562 +IO_WORD + + mwÜd +; + +2564 +IO_WORD + + m_CNTE + :1; + +2565 +IO_WORD + + m_STGR + :1; + +2566 +IO_WORD + + m_MDSE + :1; + +2567 +IO_WORD + + m_RTRG + :1; + +2568 +IO_WORD + + m_CKS1 + :1; + +2569 +IO_WORD + + m_CKS0 + :1; + +2570 +IO_WORD + + m_PGMS + :1; + +2571 + mIO_WORD + :1; + +2572 +IO_WORD + + m_EGS1 + :1; + +2573 +IO_WORD + + m_EGS0 + :1; + +2574 +IO_WORD + + m_IREN + :1; + +2575 +IO_WORD + + m_IRQF + :1; + +2576 +IO_WORD + + m_IRS1 + :1; + +2577 +IO_WORD + + m_IRS0 + :1; + +2578 + mIO_WORD + :1; + +2579 +IO_WORD + + m_OSEL + :1; + +2580 } + mb™ +; + +2582 + mIO_WORD + :1; + +2583 + mIO_WORD + :1; + +2584 + mIO_WORD + :1; + +2585 + mIO_WORD + :1; + +2586 +IO_WORD + + m_CKS + :2; + +2587 + mIO_WORD + :1; + +2588 + mIO_WORD + :1; + +2589 +IO_WORD + + m_EGS + :2; + +2590 + mIO_WORD + :1; + +2591 + mIO_WORD + :1; + +2592 +IO_WORD + + m_IRS + :2; + +2593 } + mb™c +; + +2594 } + tPCN01STR +; + +2596 +IO_BYTE + + mby‹ +; + +2598 +IO_BYTE + + m_CNTE + :1; + +2599 +IO_BYTE + + m_STGR + :1; + +2600 +IO_BYTE + + m_MDSE + :1; + +2601 +IO_BYTE + + m_RTRG + :1; + +2602 +IO_BYTE + + m_CKS1 + :1; + +2603 +IO_BYTE + + m_CKS0 + :1; + +2604 +IO_BYTE + + m_PGMS + :1; + +2605 + mIO_BYTE + :1; + +2606 } + mb™ +; + +2608 + mIO_BYTE + :1; + +2609 + mIO_BYTE + :1; + +2610 + mIO_BYTE + :1; + +2611 + mIO_BYTE + :1; + +2612 +IO_BYTE + + m_CKS + :2; + +2613 } + mb™c +; + +2614 } + tPCNH01STR +; + +2616 +IO_BYTE + + mby‹ +; + +2618 +IO_BYTE + + m_EGS1 + :1; + +2619 +IO_BYTE + + m_EGS0 + :1; + +2620 +IO_BYTE + + m_IREN + :1; + +2621 +IO_BYTE + + m_IRQF + :1; + +2622 +IO_BYTE + + m_IRS1 + :1; + +2623 +IO_BYTE + + m_IRS0 + :1; + +2624 + mIO_BYTE + :1; + +2625 +IO_BYTE + + m_OSEL + :1; + +2626 } + mb™ +; + +2628 +IO_BYTE + + m_EGS + :2; + +2629 + mIO_BYTE + :1; + +2630 + mIO_BYTE + :1; + +2631 +IO_BYTE + + m_IRS + :2; + +2632 } + mb™c +; + +2633 } + tPCNL01STR +; + +2635 +IO_WORD + + mwÜd +; + +2637 +IO_WORD + + m_CNTE + :1; + +2638 +IO_WORD + + m_STGR + :1; + +2639 +IO_WORD + + m_MDSE + :1; + +2640 +IO_WORD + + m_RTRG + :1; + +2641 +IO_WORD + + m_CKS1 + :1; + +2642 +IO_WORD + + m_CKS0 + :1; + +2643 +IO_WORD + + m_PGMS + :1; + +2644 + mIO_WORD + :1; + +2645 +IO_WORD + + m_EGS1 + :1; + +2646 +IO_WORD + + m_EGS0 + :1; + +2647 +IO_WORD + + m_IREN + :1; + +2648 +IO_WORD + + m_IRQF + :1; + +2649 +IO_WORD + + m_IRS1 + :1; + +2650 +IO_WORD + + m_IRS0 + :1; + +2651 + mIO_WORD + :1; + +2652 +IO_WORD + + m_OSEL + :1; + +2653 } + mb™ +; + +2655 + mIO_WORD + :1; + +2656 + mIO_WORD + :1; + +2657 + mIO_WORD + :1; + +2658 + mIO_WORD + :1; + +2659 +IO_WORD + + m_CKS + :2; + +2660 + mIO_WORD + :1; + +2661 + mIO_WORD + :1; + +2662 +IO_WORD + + m_EGS + :2; + +2663 + mIO_WORD + :1; + +2664 + mIO_WORD + :1; + +2665 +IO_WORD + + m_IRS + :2; + +2666 } + mb™c +; + +2667 } + tPCN02STR +; + +2669 +IO_BYTE + + mby‹ +; + +2671 +IO_BYTE + + m_CNTE + :1; + +2672 +IO_BYTE + + m_STGR + :1; + +2673 +IO_BYTE + + m_MDSE + :1; + +2674 +IO_BYTE + + m_RTRG + :1; + +2675 +IO_BYTE + + m_CKS1 + :1; + +2676 +IO_BYTE + + m_CKS0 + :1; + +2677 +IO_BYTE + + m_PGMS + :1; + +2678 + mIO_BYTE + :1; + +2679 } + mb™ +; + +2681 + mIO_BYTE + :1; + +2682 + mIO_BYTE + :1; + +2683 + mIO_BYTE + :1; + +2684 + mIO_BYTE + :1; + +2685 +IO_BYTE + + m_CKS + :2; + +2686 } + mb™c +; + +2687 } + tPCNH02STR +; + +2689 +IO_BYTE + + mby‹ +; + +2691 +IO_BYTE + + m_EGS1 + :1; + +2692 +IO_BYTE + + m_EGS0 + :1; + +2693 +IO_BYTE + + m_IREN + :1; + +2694 +IO_BYTE + + m_IRQF + :1; + +2695 +IO_BYTE + + m_IRS1 + :1; + +2696 +IO_BYTE + + m_IRS0 + :1; + +2697 + mIO_BYTE + :1; + +2698 +IO_BYTE + + m_OSEL + :1; + +2699 } + mb™ +; + +2701 +IO_BYTE + + m_EGS + :2; + +2702 + mIO_BYTE + :1; + +2703 + mIO_BYTE + :1; + +2704 +IO_BYTE + + m_IRS + :2; + +2705 } + mb™c +; + +2706 } + tPCNL02STR +; + +2708 +IO_WORD + + mwÜd +; + +2710 +IO_WORD + + m_CNTE + :1; + +2711 +IO_WORD + + m_STGR + :1; + +2712 +IO_WORD + + m_MDSE + :1; + +2713 +IO_WORD + + m_RTRG + :1; + +2714 +IO_WORD + + m_CKS1 + :1; + +2715 +IO_WORD + + m_CKS0 + :1; + +2716 +IO_WORD + + m_PGMS + :1; + +2717 + mIO_WORD + :1; + +2718 +IO_WORD + + m_EGS1 + :1; + +2719 +IO_WORD + + m_EGS0 + :1; + +2720 +IO_WORD + + m_IREN + :1; + +2721 +IO_WORD + + m_IRQF + :1; + +2722 +IO_WORD + + m_IRS1 + :1; + +2723 +IO_WORD + + m_IRS0 + :1; + +2724 + mIO_WORD + :1; + +2725 +IO_WORD + + m_OSEL + :1; + +2726 } + mb™ +; + +2728 + mIO_WORD + :1; + +2729 + mIO_WORD + :1; + +2730 + mIO_WORD + :1; + +2731 + mIO_WORD + :1; + +2732 +IO_WORD + + m_CKS + :2; + +2733 + mIO_WORD + :1; + +2734 + mIO_WORD + :1; + +2735 +IO_WORD + + m_EGS + :2; + +2736 + mIO_WORD + :1; + +2737 + mIO_WORD + :1; + +2738 +IO_WORD + + m_IRS + :2; + +2739 } + mb™c +; + +2740 } + tPCN03STR +; + +2742 +IO_BYTE + + mby‹ +; + +2744 +IO_BYTE + + m_CNTE + :1; + +2745 +IO_BYTE + + m_STGR + :1; + +2746 +IO_BYTE + + m_MDSE + :1; + +2747 +IO_BYTE + + m_RTRG + :1; + +2748 +IO_BYTE + + m_CKS1 + :1; + +2749 +IO_BYTE + + m_CKS0 + :1; + +2750 +IO_BYTE + + m_PGMS + :1; + +2751 + mIO_BYTE + :1; + +2752 } + mb™ +; + +2754 + mIO_BYTE + :1; + +2755 + mIO_BYTE + :1; + +2756 + mIO_BYTE + :1; + +2757 + mIO_BYTE + :1; + +2758 +IO_BYTE + + m_CKS + :2; + +2759 } + mb™c +; + +2760 } + tPCNH03STR +; + +2762 +IO_BYTE + + mby‹ +; + +2764 +IO_BYTE + + m_EGS1 + :1; + +2765 +IO_BYTE + + m_EGS0 + :1; + +2766 +IO_BYTE + + m_IREN + :1; + +2767 +IO_BYTE + + m_IRQF + :1; + +2768 +IO_BYTE + + m_IRS1 + :1; + +2769 +IO_BYTE + + m_IRS0 + :1; + +2770 + mIO_BYTE + :1; + +2771 +IO_BYTE + + m_OSEL + :1; + +2772 } + mb™ +; + +2774 +IO_BYTE + + m_EGS + :2; + +2775 + mIO_BYTE + :1; + +2776 + mIO_BYTE + :1; + +2777 +IO_BYTE + + m_IRS + :2; + +2778 } + mb™c +; + +2779 } + tPCNL03STR +; + +2781 +IO_WORD + + mwÜd +; + +2783 +IO_WORD + + m_CNTE + :1; + +2784 +IO_WORD + + m_STGR + :1; + +2785 +IO_WORD + + m_MDSE + :1; + +2786 +IO_WORD + + m_RTRG + :1; + +2787 +IO_WORD + + m_CKS1 + :1; + +2788 +IO_WORD + + m_CKS0 + :1; + +2789 +IO_WORD + + m_PGMS + :1; + +2790 + mIO_WORD + :1; + +2791 +IO_WORD + + m_EGS1 + :1; + +2792 +IO_WORD + + m_EGS0 + :1; + +2793 +IO_WORD + + m_IREN + :1; + +2794 +IO_WORD + + m_IRQF + :1; + +2795 +IO_WORD + + m_IRS1 + :1; + +2796 +IO_WORD + + m_IRS0 + :1; + +2797 + mIO_WORD + :1; + +2798 +IO_WORD + + m_OSEL + :1; + +2799 } + mb™ +; + +2801 + mIO_WORD + :1; + +2802 + mIO_WORD + :1; + +2803 + mIO_WORD + :1; + +2804 + mIO_WORD + :1; + +2805 +IO_WORD + + m_CKS + :2; + +2806 + mIO_WORD + :1; + +2807 + mIO_WORD + :1; + +2808 +IO_WORD + + m_EGS + :2; + +2809 + mIO_WORD + :1; + +2810 + mIO_WORD + :1; + +2811 +IO_WORD + + m_IRS + :2; + +2812 } + mb™c +; + +2813 } + tPCN04STR +; + +2815 +IO_BYTE + + mby‹ +; + +2817 +IO_BYTE + + m_CNTE + :1; + +2818 +IO_BYTE + + m_STGR + :1; + +2819 +IO_BYTE + + m_MDSE + :1; + +2820 +IO_BYTE + + m_RTRG + :1; + +2821 +IO_BYTE + + m_CKS1 + :1; + +2822 +IO_BYTE + + m_CKS0 + :1; + +2823 +IO_BYTE + + m_PGMS + :1; + +2824 + mIO_BYTE + :1; + +2825 } + mb™ +; + +2827 + mIO_BYTE + :1; + +2828 + mIO_BYTE + :1; + +2829 + mIO_BYTE + :1; + +2830 + mIO_BYTE + :1; + +2831 +IO_BYTE + + m_CKS + :2; + +2832 } + mb™c +; + +2833 } + tPCNH04STR +; + +2835 +IO_BYTE + + mby‹ +; + +2837 +IO_BYTE + + m_EGS1 + :1; + +2838 +IO_BYTE + + m_EGS0 + :1; + +2839 +IO_BYTE + + m_IREN + :1; + +2840 +IO_BYTE + + m_IRQF + :1; + +2841 +IO_BYTE + + m_IRS1 + :1; + +2842 +IO_BYTE + + m_IRS0 + :1; + +2843 + mIO_BYTE + :1; + +2844 +IO_BYTE + + m_OSEL + :1; + +2845 } + mb™ +; + +2847 +IO_BYTE + + m_EGS + :2; + +2848 + mIO_BYTE + :1; + +2849 + mIO_BYTE + :1; + +2850 +IO_BYTE + + m_IRS + :2; + +2851 } + mb™c +; + +2852 } + tPCNL04STR +; + +2854 +IO_WORD + + mwÜd +; + +2856 +IO_WORD + + m_CNTE + :1; + +2857 +IO_WORD + + m_STGR + :1; + +2858 +IO_WORD + + m_MDSE + :1; + +2859 +IO_WORD + + m_RTRG + :1; + +2860 +IO_WORD + + m_CKS1 + :1; + +2861 +IO_WORD + + m_CKS0 + :1; + +2862 +IO_WORD + + m_PGMS + :1; + +2863 + mIO_WORD + :1; + +2864 +IO_WORD + + m_EGS1 + :1; + +2865 +IO_WORD + + m_EGS0 + :1; + +2866 +IO_WORD + + m_IREN + :1; + +2867 +IO_WORD + + m_IRQF + :1; + +2868 +IO_WORD + + m_IRS1 + :1; + +2869 +IO_WORD + + m_IRS0 + :1; + +2870 + mIO_WORD + :1; + +2871 +IO_WORD + + m_OSEL + :1; + +2872 } + mb™ +; + +2874 + mIO_WORD + :1; + +2875 + mIO_WORD + :1; + +2876 + mIO_WORD + :1; + +2877 + mIO_WORD + :1; + +2878 +IO_WORD + + m_CKS + :2; + +2879 + mIO_WORD + :1; + +2880 + mIO_WORD + :1; + +2881 +IO_WORD + + m_EGS + :2; + +2882 + mIO_WORD + :1; + +2883 + mIO_WORD + :1; + +2884 +IO_WORD + + m_IRS + :2; + +2885 } + mb™c +; + +2886 } + tPCN05STR +; + +2888 +IO_BYTE + + mby‹ +; + +2890 +IO_BYTE + + m_CNTE + :1; + +2891 +IO_BYTE + + m_STGR + :1; + +2892 +IO_BYTE + + m_MDSE + :1; + +2893 +IO_BYTE + + m_RTRG + :1; + +2894 +IO_BYTE + + m_CKS1 + :1; + +2895 +IO_BYTE + + m_CKS0 + :1; + +2896 +IO_BYTE + + m_PGMS + :1; + +2897 + mIO_BYTE + :1; + +2898 } + mb™ +; + +2900 + mIO_BYTE + :1; + +2901 + mIO_BYTE + :1; + +2902 + mIO_BYTE + :1; + +2903 + mIO_BYTE + :1; + +2904 +IO_BYTE + + m_CKS + :2; + +2905 } + mb™c +; + +2906 } + tPCNH05STR +; + +2908 +IO_BYTE + + mby‹ +; + +2910 +IO_BYTE + + m_EGS1 + :1; + +2911 +IO_BYTE + + m_EGS0 + :1; + +2912 +IO_BYTE + + m_IREN + :1; + +2913 +IO_BYTE + + m_IRQF + :1; + +2914 +IO_BYTE + + m_IRS1 + :1; + +2915 +IO_BYTE + + m_IRS0 + :1; + +2916 + mIO_BYTE + :1; + +2917 +IO_BYTE + + m_OSEL + :1; + +2918 } + mb™ +; + +2920 +IO_BYTE + + m_EGS + :2; + +2921 + mIO_BYTE + :1; + +2922 + mIO_BYTE + :1; + +2923 +IO_BYTE + + m_IRS + :2; + +2924 } + mb™c +; + +2925 } + tPCNL05STR +; + +2927 +IO_WORD + + mwÜd +; + +2929 +IO_WORD + + m_CNTE + :1; + +2930 +IO_WORD + + m_STGR + :1; + +2931 +IO_WORD + + m_MDSE + :1; + +2932 +IO_WORD + + m_RTRG + :1; + +2933 +IO_WORD + + m_CKS1 + :1; + +2934 +IO_WORD + + m_CKS0 + :1; + +2935 +IO_WORD + + m_PGMS + :1; + +2936 + mIO_WORD + :1; + +2937 +IO_WORD + + m_EGS1 + :1; + +2938 +IO_WORD + + m_EGS0 + :1; + +2939 +IO_WORD + + m_IREN + :1; + +2940 +IO_WORD + + m_IRQF + :1; + +2941 +IO_WORD + + m_IRS1 + :1; + +2942 +IO_WORD + + m_IRS0 + :1; + +2943 + mIO_WORD + :1; + +2944 +IO_WORD + + m_OSEL + :1; + +2945 } + mb™ +; + +2947 + mIO_WORD + :1; + +2948 + mIO_WORD + :1; + +2949 + mIO_WORD + :1; + +2950 + mIO_WORD + :1; + +2951 +IO_WORD + + m_CKS + :2; + +2952 + mIO_WORD + :1; + +2953 + mIO_WORD + :1; + +2954 +IO_WORD + + m_EGS + :2; + +2955 + mIO_WORD + :1; + +2956 + mIO_WORD + :1; + +2957 +IO_WORD + + m_IRS + :2; + +2958 } + mb™c +; + +2959 } + tPCN06STR +; + +2961 +IO_BYTE + + mby‹ +; + +2963 +IO_BYTE + + m_CNTE + :1; + +2964 +IO_BYTE + + m_STGR + :1; + +2965 +IO_BYTE + + m_MDSE + :1; + +2966 +IO_BYTE + + m_RTRG + :1; + +2967 +IO_BYTE + + m_CKS1 + :1; + +2968 +IO_BYTE + + m_CKS0 + :1; + +2969 +IO_BYTE + + m_PGMS + :1; + +2970 + mIO_BYTE + :1; + +2971 } + mb™ +; + +2973 + mIO_BYTE + :1; + +2974 + mIO_BYTE + :1; + +2975 + mIO_BYTE + :1; + +2976 + mIO_BYTE + :1; + +2977 +IO_BYTE + + m_CKS + :2; + +2978 } + mb™c +; + +2979 } + tPCNH06STR +; + +2981 +IO_BYTE + + mby‹ +; + +2983 +IO_BYTE + + m_EGS1 + :1; + +2984 +IO_BYTE + + m_EGS0 + :1; + +2985 +IO_BYTE + + m_IREN + :1; + +2986 +IO_BYTE + + m_IRQF + :1; + +2987 +IO_BYTE + + m_IRS1 + :1; + +2988 +IO_BYTE + + m_IRS0 + :1; + +2989 + mIO_BYTE + :1; + +2990 +IO_BYTE + + m_OSEL + :1; + +2991 } + mb™ +; + +2993 +IO_BYTE + + m_EGS + :2; + +2994 + mIO_BYTE + :1; + +2995 + mIO_BYTE + :1; + +2996 +IO_BYTE + + m_IRS + :2; + +2997 } + mb™c +; + +2998 } + tPCNL06STR +; + +3000 +IO_WORD + + mwÜd +; + +3002 +IO_WORD + + m_CNTE + :1; + +3003 +IO_WORD + + m_STGR + :1; + +3004 +IO_WORD + + m_MDSE + :1; + +3005 +IO_WORD + + m_RTRG + :1; + +3006 +IO_WORD + + m_CKS1 + :1; + +3007 +IO_WORD + + m_CKS0 + :1; + +3008 +IO_WORD + + m_PGMS + :1; + +3009 + mIO_WORD + :1; + +3010 +IO_WORD + + m_EGS1 + :1; + +3011 +IO_WORD + + m_EGS0 + :1; + +3012 +IO_WORD + + m_IREN + :1; + +3013 +IO_WORD + + m_IRQF + :1; + +3014 +IO_WORD + + m_IRS1 + :1; + +3015 +IO_WORD + + m_IRS0 + :1; + +3016 + mIO_WORD + :1; + +3017 +IO_WORD + + m_OSEL + :1; + +3018 } + mb™ +; + +3020 + mIO_WORD + :1; + +3021 + mIO_WORD + :1; + +3022 + mIO_WORD + :1; + +3023 + mIO_WORD + :1; + +3024 +IO_WORD + + m_CKS + :2; + +3025 + mIO_WORD + :1; + +3026 + mIO_WORD + :1; + +3027 +IO_WORD + + m_EGS + :2; + +3028 + mIO_WORD + :1; + +3029 + mIO_WORD + :1; + +3030 +IO_WORD + + m_IRS + :2; + +3031 } + mb™c +; + +3032 } + tPCN07STR +; + +3034 +IO_BYTE + + mby‹ +; + +3036 +IO_BYTE + + m_CNTE + :1; + +3037 +IO_BYTE + + m_STGR + :1; + +3038 +IO_BYTE + + m_MDSE + :1; + +3039 +IO_BYTE + + m_RTRG + :1; + +3040 +IO_BYTE + + m_CKS1 + :1; + +3041 +IO_BYTE + + m_CKS0 + :1; + +3042 +IO_BYTE + + m_PGMS + :1; + +3043 + mIO_BYTE + :1; + +3044 } + mb™ +; + +3046 + mIO_BYTE + :1; + +3047 + mIO_BYTE + :1; + +3048 + mIO_BYTE + :1; + +3049 + mIO_BYTE + :1; + +3050 +IO_BYTE + + m_CKS + :2; + +3051 } + mb™c +; + +3052 } + tPCNH07STR +; + +3054 +IO_BYTE + + mby‹ +; + +3056 +IO_BYTE + + m_EGS1 + :1; + +3057 +IO_BYTE + + m_EGS0 + :1; + +3058 +IO_BYTE + + m_IREN + :1; + +3059 +IO_BYTE + + m_IRQF + :1; + +3060 +IO_BYTE + + m_IRS1 + :1; + +3061 +IO_BYTE + + m_IRS0 + :1; + +3062 + mIO_BYTE + :1; + +3063 +IO_BYTE + + m_OSEL + :1; + +3064 } + mb™ +; + +3066 +IO_BYTE + + m_EGS + :2; + +3067 + mIO_BYTE + :1; + +3068 + mIO_BYTE + :1; + +3069 +IO_BYTE + + m_IRS + :2; + +3070 } + mb™c +; + +3071 } + tPCNL07STR +; + +3073 +IO_WORD + + mwÜd +; + +3075 +IO_WORD + + m_CNTE + :1; + +3076 +IO_WORD + + m_STGR + :1; + +3077 +IO_WORD + + m_MDSE + :1; + +3078 +IO_WORD + + m_RTRG + :1; + +3079 +IO_WORD + + m_CKS1 + :1; + +3080 +IO_WORD + + m_CKS0 + :1; + +3081 +IO_WORD + + m_PGMS + :1; + +3082 + mIO_WORD + :1; + +3083 +IO_WORD + + m_EGS1 + :1; + +3084 +IO_WORD + + m_EGS0 + :1; + +3085 +IO_WORD + + m_IREN + :1; + +3086 +IO_WORD + + m_IRQF + :1; + +3087 +IO_WORD + + m_IRS1 + :1; + +3088 +IO_WORD + + m_IRS0 + :1; + +3089 + mIO_WORD + :1; + +3090 +IO_WORD + + m_OSEL + :1; + +3091 } + mb™ +; + +3093 + mIO_WORD + :1; + +3094 + mIO_WORD + :1; + +3095 + mIO_WORD + :1; + +3096 + mIO_WORD + :1; + +3097 +IO_WORD + + m_CKS + :2; + +3098 + mIO_WORD + :1; + +3099 + mIO_WORD + :1; + +3100 +IO_WORD + + m_EGS + :2; + +3101 + mIO_WORD + :1; + +3102 + mIO_WORD + :1; + +3103 +IO_WORD + + m_IRS + :2; + +3104 } + mb™c +; + +3105 } + tPCN08STR +; + +3107 +IO_BYTE + + mby‹ +; + +3109 +IO_BYTE + + m_CNTE + :1; + +3110 +IO_BYTE + + m_STGR + :1; + +3111 +IO_BYTE + + m_MDSE + :1; + +3112 +IO_BYTE + + m_RTRG + :1; + +3113 +IO_BYTE + + m_CKS1 + :1; + +3114 +IO_BYTE + + m_CKS0 + :1; + +3115 +IO_BYTE + + m_PGMS + :1; + +3116 + mIO_BYTE + :1; + +3117 } + mb™ +; + +3119 + mIO_BYTE + :1; + +3120 + mIO_BYTE + :1; + +3121 + mIO_BYTE + :1; + +3122 + mIO_BYTE + :1; + +3123 +IO_BYTE + + m_CKS + :2; + +3124 } + mb™c +; + +3125 } + tPCNH08STR +; + +3127 +IO_BYTE + + mby‹ +; + +3129 +IO_BYTE + + m_EGS1 + :1; + +3130 +IO_BYTE + + m_EGS0 + :1; + +3131 +IO_BYTE + + m_IREN + :1; + +3132 +IO_BYTE + + m_IRQF + :1; + +3133 +IO_BYTE + + m_IRS1 + :1; + +3134 +IO_BYTE + + m_IRS0 + :1; + +3135 + mIO_BYTE + :1; + +3136 +IO_BYTE + + m_OSEL + :1; + +3137 } + mb™ +; + +3139 +IO_BYTE + + m_EGS + :2; + +3140 + mIO_BYTE + :1; + +3141 + mIO_BYTE + :1; + +3142 +IO_BYTE + + m_IRS + :2; + +3143 } + mb™c +; + +3144 } + tPCNL08STR +; + +3146 +IO_WORD + + mwÜd +; + +3148 +IO_WORD + + m_CNTE + :1; + +3149 +IO_WORD + + m_STGR + :1; + +3150 +IO_WORD + + m_MDSE + :1; + +3151 +IO_WORD + + m_RTRG + :1; + +3152 +IO_WORD + + m_CKS1 + :1; + +3153 +IO_WORD + + m_CKS0 + :1; + +3154 +IO_WORD + + m_PGMS + :1; + +3155 + mIO_WORD + :1; + +3156 +IO_WORD + + m_EGS1 + :1; + +3157 +IO_WORD + + m_EGS0 + :1; + +3158 +IO_WORD + + m_IREN + :1; + +3159 +IO_WORD + + m_IRQF + :1; + +3160 +IO_WORD + + m_IRS1 + :1; + +3161 +IO_WORD + + m_IRS0 + :1; + +3162 + mIO_WORD + :1; + +3163 +IO_WORD + + m_OSEL + :1; + +3164 } + mb™ +; + +3166 + mIO_WORD + :1; + +3167 + mIO_WORD + :1; + +3168 + mIO_WORD + :1; + +3169 + mIO_WORD + :1; + +3170 +IO_WORD + + m_CKS + :2; + +3171 + mIO_WORD + :1; + +3172 + mIO_WORD + :1; + +3173 +IO_WORD + + m_EGS + :2; + +3174 + mIO_WORD + :1; + +3175 + mIO_WORD + :1; + +3176 +IO_WORD + + m_IRS + :2; + +3177 } + mb™c +; + +3178 } + tPCN09STR +; + +3180 +IO_BYTE + + mby‹ +; + +3182 +IO_BYTE + + m_CNTE + :1; + +3183 +IO_BYTE + + m_STGR + :1; + +3184 +IO_BYTE + + m_MDSE + :1; + +3185 +IO_BYTE + + m_RTRG + :1; + +3186 +IO_BYTE + + m_CKS1 + :1; + +3187 +IO_BYTE + + m_CKS0 + :1; + +3188 +IO_BYTE + + m_PGMS + :1; + +3189 + mIO_BYTE + :1; + +3190 } + mb™ +; + +3192 + mIO_BYTE + :1; + +3193 + mIO_BYTE + :1; + +3194 + mIO_BYTE + :1; + +3195 + mIO_BYTE + :1; + +3196 +IO_BYTE + + m_CKS + :2; + +3197 } + mb™c +; + +3198 } + tPCNH09STR +; + +3200 +IO_BYTE + + mby‹ +; + +3202 +IO_BYTE + + m_EGS1 + :1; + +3203 +IO_BYTE + + m_EGS0 + :1; + +3204 +IO_BYTE + + m_IREN + :1; + +3205 +IO_BYTE + + m_IRQF + :1; + +3206 +IO_BYTE + + m_IRS1 + :1; + +3207 +IO_BYTE + + m_IRS0 + :1; + +3208 + mIO_BYTE + :1; + +3209 +IO_BYTE + + m_OSEL + :1; + +3210 } + mb™ +; + +3212 +IO_BYTE + + m_EGS + :2; + +3213 + mIO_BYTE + :1; + +3214 + mIO_BYTE + :1; + +3215 +IO_BYTE + + m_IRS + :2; + +3216 } + mb™c +; + +3217 } + tPCNL09STR +; + +3219 +IO_WORD + + mwÜd +; + +3221 +IO_WORD + + m_CNTE + :1; + +3222 +IO_WORD + + m_STGR + :1; + +3223 +IO_WORD + + m_MDSE + :1; + +3224 +IO_WORD + + m_RTRG + :1; + +3225 +IO_WORD + + m_CKS1 + :1; + +3226 +IO_WORD + + m_CKS0 + :1; + +3227 +IO_WORD + + m_PGMS + :1; + +3228 + mIO_WORD + :1; + +3229 +IO_WORD + + m_EGS1 + :1; + +3230 +IO_WORD + + m_EGS0 + :1; + +3231 +IO_WORD + + m_IREN + :1; + +3232 +IO_WORD + + m_IRQF + :1; + +3233 +IO_WORD + + m_IRS1 + :1; + +3234 +IO_WORD + + m_IRS0 + :1; + +3235 + mIO_WORD + :1; + +3236 +IO_WORD + + m_OSEL + :1; + +3237 } + mb™ +; + +3239 + mIO_WORD + :1; + +3240 + mIO_WORD + :1; + +3241 + mIO_WORD + :1; + +3242 + mIO_WORD + :1; + +3243 +IO_WORD + + m_CKS + :2; + +3244 + mIO_WORD + :1; + +3245 + mIO_WORD + :1; + +3246 +IO_WORD + + m_EGS + :2; + +3247 + mIO_WORD + :1; + +3248 + mIO_WORD + :1; + +3249 +IO_WORD + + m_IRS + :2; + +3250 } + mb™c +; + +3251 } + tPCN10STR +; + +3253 +IO_BYTE + + mby‹ +; + +3255 +IO_BYTE + + m_CNTE + :1; + +3256 +IO_BYTE + + m_STGR + :1; + +3257 +IO_BYTE + + m_MDSE + :1; + +3258 +IO_BYTE + + m_RTRG + :1; + +3259 +IO_BYTE + + m_CKS1 + :1; + +3260 +IO_BYTE + + m_CKS0 + :1; + +3261 +IO_BYTE + + m_PGMS + :1; + +3262 + mIO_BYTE + :1; + +3263 } + mb™ +; + +3265 + mIO_BYTE + :1; + +3266 + mIO_BYTE + :1; + +3267 + mIO_BYTE + :1; + +3268 + mIO_BYTE + :1; + +3269 +IO_BYTE + + m_CKS + :2; + +3270 } + mb™c +; + +3271 } + tPCNH10STR +; + +3273 +IO_BYTE + + mby‹ +; + +3275 +IO_BYTE + + m_EGS1 + :1; + +3276 +IO_BYTE + + m_EGS0 + :1; + +3277 +IO_BYTE + + m_IREN + :1; + +3278 +IO_BYTE + + m_IRQF + :1; + +3279 +IO_BYTE + + m_IRS1 + :1; + +3280 +IO_BYTE + + m_IRS0 + :1; + +3281 + mIO_BYTE + :1; + +3282 +IO_BYTE + + m_OSEL + :1; + +3283 } + mb™ +; + +3285 +IO_BYTE + + m_EGS + :2; + +3286 + mIO_BYTE + :1; + +3287 + mIO_BYTE + :1; + +3288 +IO_BYTE + + m_IRS + :2; + +3289 } + mb™c +; + +3290 } + tPCNL10STR +; + +3292 +IO_WORD + + mwÜd +; + +3294 +IO_WORD + + m_CNTE + :1; + +3295 +IO_WORD + + m_STGR + :1; + +3296 +IO_WORD + + m_MDSE + :1; + +3297 +IO_WORD + + m_RTRG + :1; + +3298 +IO_WORD + + m_CKS1 + :1; + +3299 +IO_WORD + + m_CKS0 + :1; + +3300 +IO_WORD + + m_PGMS + :1; + +3301 + mIO_WORD + :1; + +3302 +IO_WORD + + m_EGS1 + :1; + +3303 +IO_WORD + + m_EGS0 + :1; + +3304 +IO_WORD + + m_IREN + :1; + +3305 +IO_WORD + + m_IRQF + :1; + +3306 +IO_WORD + + m_IRS1 + :1; + +3307 +IO_WORD + + m_IRS0 + :1; + +3308 + mIO_WORD + :1; + +3309 +IO_WORD + + m_OSEL + :1; + +3310 } + mb™ +; + +3312 + mIO_WORD + :1; + +3313 + mIO_WORD + :1; + +3314 + mIO_WORD + :1; + +3315 + mIO_WORD + :1; + +3316 +IO_WORD + + m_CKS + :2; + +3317 + mIO_WORD + :1; + +3318 + mIO_WORD + :1; + +3319 +IO_WORD + + m_EGS + :2; + +3320 + mIO_WORD + :1; + +3321 + mIO_WORD + :1; + +3322 +IO_WORD + + m_IRS + :2; + +3323 } + mb™c +; + +3324 } + tPCN11STR +; + +3326 +IO_BYTE + + mby‹ +; + +3328 +IO_BYTE + + m_CNTE + :1; + +3329 +IO_BYTE + + m_STGR + :1; + +3330 +IO_BYTE + + m_MDSE + :1; + +3331 +IO_BYTE + + m_RTRG + :1; + +3332 +IO_BYTE + + m_CKS1 + :1; + +3333 +IO_BYTE + + m_CKS0 + :1; + +3334 +IO_BYTE + + m_PGMS + :1; + +3335 + mIO_BYTE + :1; + +3336 } + mb™ +; + +3338 + mIO_BYTE + :1; + +3339 + mIO_BYTE + :1; + +3340 + mIO_BYTE + :1; + +3341 + mIO_BYTE + :1; + +3342 +IO_BYTE + + m_CKS + :2; + +3343 } + mb™c +; + +3344 } + tPCNH11STR +; + +3346 +IO_BYTE + + mby‹ +; + +3348 +IO_BYTE + + m_EGS1 + :1; + +3349 +IO_BYTE + + m_EGS0 + :1; + +3350 +IO_BYTE + + m_IREN + :1; + +3351 +IO_BYTE + + m_IRQF + :1; + +3352 +IO_BYTE + + m_IRS1 + :1; + +3353 +IO_BYTE + + m_IRS0 + :1; + +3354 + mIO_BYTE + :1; + +3355 +IO_BYTE + + m_OSEL + :1; + +3356 } + mb™ +; + +3358 +IO_BYTE + + m_EGS + :2; + +3359 + mIO_BYTE + :1; + +3360 + mIO_BYTE + :1; + +3361 +IO_BYTE + + m_IRS + :2; + +3362 } + mb™c +; + +3363 } + tPCNL11STR +; + +3365 +IO_BYTE + + mby‹ +; + +3367 +IO_BYTE + + m_ICP1 + :1; + +3368 +IO_BYTE + + m_ICP0 + :1; + +3369 +IO_BYTE + + m_ICE1 + :1; + +3370 +IO_BYTE + + m_ICE0 + :1; + +3371 +IO_BYTE + + m_EG11 + :1; + +3372 +IO_BYTE + + m_EG10 + :1; + +3373 +IO_BYTE + + m_EG01 + :1; + +3374 +IO_BYTE + + m_EG00 + :1; + +3375 } + mb™ +; + +3377 + mIO_BYTE + :1; + +3378 + mIO_BYTE + :1; + +3379 + mIO_BYTE + :1; + +3380 + mIO_BYTE + :1; + +3381 +IO_BYTE + + m_EG1 + :2; + +3382 +IO_BYTE + + m_EG0 + :2; + +3383 } + mb™c +; + +3384 } + tICS01STR +; + +3386 +IO_BYTE + + mby‹ +; + +3388 +IO_BYTE + + m_ICP3 + :1; + +3389 +IO_BYTE + + m_ICP2 + :1; + +3390 +IO_BYTE + + m_ICE3 + :1; + +3391 +IO_BYTE + + m_ICE2 + :1; + +3392 +IO_BYTE + + m_EG31 + :1; + +3393 +IO_BYTE + + m_EG30 + :1; + +3394 +IO_BYTE + + m_EG21 + :1; + +3395 +IO_BYTE + + m_EG20 + :1; + +3396 } + mb™ +; + +3398 + mIO_BYTE + :1; + +3399 + mIO_BYTE + :1; + +3400 + mIO_BYTE + :1; + +3401 + mIO_BYTE + :1; + +3402 +IO_BYTE + + m_EG3 + :2; + +3403 +IO_BYTE + + m_EG2 + :2; + +3404 } + mb™c +; + +3405 } + tICS23STR +; + +3407 +IO_WORD + + mwÜd +; + +3409 +IO_WORD + + m_CP15 + :1; + +3410 +IO_WORD + + m_CP14 + :1; + +3411 +IO_WORD + + m_CP13 + :1; + +3412 +IO_WORD + + m_CP12 + :1; + +3413 +IO_WORD + + m_CP11 + :1; + +3414 +IO_WORD + + m_CP10 + :1; + +3415 +IO_WORD + + m_CP9 + :1; + +3416 +IO_WORD + + m_CP8 + :1; + +3417 +IO_WORD + + m_CP7 + :1; + +3418 +IO_WORD + + m_CP6 + :1; + +3419 +IO_WORD + + m_CP5 + :1; + +3420 +IO_WORD + + m_CP4 + :1; + +3421 +IO_WORD + + m_CP3 + :1; + +3422 +IO_WORD + + m_CP2 + :1; + +3423 +IO_WORD + + m_CP1 + :1; + +3424 +IO_WORD + + m_CP0 + :1; + +3425 } + mb™ +; + +3426 } + tIPCP0STR +; + +3428 +IO_WORD + + mwÜd +; + +3430 +IO_WORD + + m_CP15 + :1; + +3431 +IO_WORD + + m_CP14 + :1; + +3432 +IO_WORD + + m_CP13 + :1; + +3433 +IO_WORD + + m_CP12 + :1; + +3434 +IO_WORD + + m_CP11 + :1; + +3435 +IO_WORD + + m_CP10 + :1; + +3436 +IO_WORD + + m_CP9 + :1; + +3437 +IO_WORD + + m_CP8 + :1; + +3438 +IO_WORD + + m_CP7 + :1; + +3439 +IO_WORD + + m_CP6 + :1; + +3440 +IO_WORD + + m_CP5 + :1; + +3441 +IO_WORD + + m_CP4 + :1; + +3442 +IO_WORD + + m_CP3 + :1; + +3443 +IO_WORD + + m_CP2 + :1; + +3444 +IO_WORD + + m_CP1 + :1; + +3445 +IO_WORD + + m_CP0 + :1; + +3446 } + mb™ +; + +3447 } + tIPCP1STR +; + +3449 +IO_WORD + + mwÜd +; + +3451 +IO_WORD + + m_CP15 + :1; + +3452 +IO_WORD + + m_CP14 + :1; + +3453 +IO_WORD + + m_CP13 + :1; + +3454 +IO_WORD + + m_CP12 + :1; + +3455 +IO_WORD + + m_CP11 + :1; + +3456 +IO_WORD + + m_CP10 + :1; + +3457 +IO_WORD + + m_CP9 + :1; + +3458 +IO_WORD + + m_CP8 + :1; + +3459 +IO_WORD + + m_CP7 + :1; + +3460 +IO_WORD + + m_CP6 + :1; + +3461 +IO_WORD + + m_CP5 + :1; + +3462 +IO_WORD + + m_CP4 + :1; + +3463 +IO_WORD + + m_CP3 + :1; + +3464 +IO_WORD + + m_CP2 + :1; + +3465 +IO_WORD + + m_CP1 + :1; + +3466 +IO_WORD + + m_CP0 + :1; + +3467 } + mb™ +; + +3468 } + tIPCP2STR +; + +3470 +IO_WORD + + mwÜd +; + +3472 +IO_WORD + + m_CP15 + :1; + +3473 +IO_WORD + + m_CP14 + :1; + +3474 +IO_WORD + + m_CP13 + :1; + +3475 +IO_WORD + + m_CP12 + :1; + +3476 +IO_WORD + + m_CP11 + :1; + +3477 +IO_WORD + + m_CP10 + :1; + +3478 +IO_WORD + + m_CP9 + :1; + +3479 +IO_WORD + + m_CP8 + :1; + +3480 +IO_WORD + + m_CP7 + :1; + +3481 +IO_WORD + + m_CP6 + :1; + +3482 +IO_WORD + + m_CP5 + :1; + +3483 +IO_WORD + + m_CP4 + :1; + +3484 +IO_WORD + + m_CP3 + :1; + +3485 +IO_WORD + + m_CP2 + :1; + +3486 +IO_WORD + + m_CP1 + :1; + +3487 +IO_WORD + + m_CP0 + :1; + +3488 } + mb™ +; + +3489 } + tIPCP3STR +; + +3491 +IO_WORD + + mwÜd +; + +3493 + mIO_WORD + :1; + +3494 + mIO_WORD + :1; + +3495 + mIO_WORD + :1; + +3496 +IO_WORD + + m_CMOD + :1; + +3497 + mIO_WORD + :1; + +3498 + mIO_WORD + :1; + +3499 +IO_WORD + + m_OTD1 + :1; + +3500 +IO_WORD + + m_OTD0 + :1; + +3501 +IO_WORD + + m_ICP1 + :1; + +3502 +IO_WORD + + m_ICP0 + :1; + +3503 +IO_WORD + + m_ICE1 + :1; + +3504 +IO_WORD + + m_ICE0 + :1; + +3505 + mIO_WORD + :1; + +3506 + mIO_WORD + :1; + +3507 +IO_WORD + + m_CST1 + :1; + +3508 +IO_WORD + + m_CST0 + :1; + +3509 } + mb™ +; + +3510 } + tOCS01STR +; + +3512 +IO_WORD + + mwÜd +; + +3514 + mIO_WORD + :1; + +3515 + mIO_WORD + :1; + +3516 + mIO_WORD + :1; + +3517 +IO_WORD + + m_CMOD + :1; + +3518 + mIO_WORD + :1; + +3519 + mIO_WORD + :1; + +3520 +IO_WORD + + m_OTD3 + :1; + +3521 +IO_WORD + + m_OTD2 + :1; + +3522 +IO_WORD + + m_ICP3 + :1; + +3523 +IO_WORD + + m_ICP2 + :1; + +3524 +IO_WORD + + m_ICE3 + :1; + +3525 +IO_WORD + + m_ICE2 + :1; + +3526 + mIO_WORD + :1; + +3527 + mIO_WORD + :1; + +3528 +IO_WORD + + m_CST3 + :1; + +3529 +IO_WORD + + m_CST2 + :1; + +3530 } + mb™ +; + +3531 } + tOCS23STR +; + +3533 +IO_WORD + + mwÜd +; + +3535 +IO_WORD + + m_C15 + :1; + +3536 +IO_WORD + + m_C14 + :1; + +3537 +IO_WORD + + m_C13 + :1; + +3538 +IO_WORD + + m_C12 + :1; + +3539 +IO_WORD + + m_C11 + :1; + +3540 +IO_WORD + + m_C10 + :1; + +3541 +IO_WORD + + m_C9 + :1; + +3542 +IO_WORD + + m_C8 + :1; + +3543 +IO_WORD + + m_C7 + :1; + +3544 +IO_WORD + + m_C6 + :1; + +3545 +IO_WORD + + m_C5 + :1; + +3546 +IO_WORD + + m_C4 + :1; + +3547 +IO_WORD + + m_C3 + :1; + +3548 +IO_WORD + + m_C2 + :1; + +3549 +IO_WORD + + m_C1 + :1; + +3550 +IO_WORD + + m_C0 + :1; + +3551 } + mb™ +; + +3552 } + tOCCP0STR +; + +3554 +IO_WORD + + mwÜd +; + +3556 +IO_WORD + + m_C15 + :1; + +3557 +IO_WORD + + m_C14 + :1; + +3558 +IO_WORD + + m_C13 + :1; + +3559 +IO_WORD + + m_C12 + :1; + +3560 +IO_WORD + + m_C11 + :1; + +3561 +IO_WORD + + m_C10 + :1; + +3562 +IO_WORD + + m_C9 + :1; + +3563 +IO_WORD + + m_C8 + :1; + +3564 +IO_WORD + + m_C7 + :1; + +3565 +IO_WORD + + m_C6 + :1; + +3566 +IO_WORD + + m_C5 + :1; + +3567 +IO_WORD + + m_C4 + :1; + +3568 +IO_WORD + + m_C3 + :1; + +3569 +IO_WORD + + m_C2 + :1; + +3570 +IO_WORD + + m_C1 + :1; + +3571 +IO_WORD + + m_C0 + :1; + +3572 } + mb™ +; + +3573 } + tOCCP1STR +; + +3575 +IO_WORD + + mwÜd +; + +3577 +IO_WORD + + m_C15 + :1; + +3578 +IO_WORD + + m_C14 + :1; + +3579 +IO_WORD + + m_C13 + :1; + +3580 +IO_WORD + + m_C12 + :1; + +3581 +IO_WORD + + m_C11 + :1; + +3582 +IO_WORD + + m_C10 + :1; + +3583 +IO_WORD + + m_C9 + :1; + +3584 +IO_WORD + + m_C8 + :1; + +3585 +IO_WORD + + m_C7 + :1; + +3586 +IO_WORD + + m_C6 + :1; + +3587 +IO_WORD + + m_C5 + :1; + +3588 +IO_WORD + + m_C4 + :1; + +3589 +IO_WORD + + m_C3 + :1; + +3590 +IO_WORD + + m_C2 + :1; + +3591 +IO_WORD + + m_C1 + :1; + +3592 +IO_WORD + + m_C0 + :1; + +3593 } + mb™ +; + +3594 } + tOCCP2STR +; + +3596 +IO_WORD + + mwÜd +; + +3598 +IO_WORD + + m_C15 + :1; + +3599 +IO_WORD + + m_C14 + :1; + +3600 +IO_WORD + + m_C13 + :1; + +3601 +IO_WORD + + m_C12 + :1; + +3602 +IO_WORD + + m_C11 + :1; + +3603 +IO_WORD + + m_C10 + :1; + +3604 +IO_WORD + + m_C9 + :1; + +3605 +IO_WORD + + m_C8 + :1; + +3606 +IO_WORD + + m_C7 + :1; + +3607 +IO_WORD + + m_C6 + :1; + +3608 +IO_WORD + + m_C5 + :1; + +3609 +IO_WORD + + m_C4 + :1; + +3610 +IO_WORD + + m_C3 + :1; + +3611 +IO_WORD + + m_C2 + :1; + +3612 +IO_WORD + + m_C1 + :1; + +3613 +IO_WORD + + m_C0 + :1; + +3614 } + mb™ +; + +3615 } + tOCCP3STR +; + +3617 +IO_WORD + + mwÜd +; + +3619 +IO_WORD + + m_ADE31 + :1; + +3620 +IO_WORD + + m_ADE30 + :1; + +3621 +IO_WORD + + m_ADE29 + :1; + +3622 +IO_WORD + + m_ADE28 + :1; + +3623 +IO_WORD + + m_ADE27 + :1; + +3624 +IO_WORD + + m_ADE26 + :1; + +3625 +IO_WORD + + m_ADE25 + :1; + +3626 +IO_WORD + + m_ADE24 + :1; + +3627 +IO_WORD + + m_ADE23 + :1; + +3628 +IO_WORD + + m_ADE22 + :1; + +3629 +IO_WORD + + m_ADE21 + :1; + +3630 +IO_WORD + + m_ADE20 + :1; + +3631 +IO_WORD + + m_ADE19 + :1; + +3632 +IO_WORD + + m_ADE18 + :1; + +3633 +IO_WORD + + m_ADE17 + :1; + +3634 +IO_WORD + + m_ADE16 + :1; + +3635 } + mb™ +; + +3636 } + tADERHSTR +; + +3638 +IO_WORD + + mwÜd +; + +3640 +IO_WORD + + m_ADE15 + :1; + +3641 +IO_WORD + + m_ADE14 + :1; + +3642 +IO_WORD + + m_ADE13 + :1; + +3643 +IO_WORD + + m_ADE12 + :1; + +3644 +IO_WORD + + m_ADE11 + :1; + +3645 +IO_WORD + + m_ADE10 + :1; + +3646 +IO_WORD + + m_ADE9 + :1; + +3647 +IO_WORD + + m_ADE8 + :1; + +3648 +IO_WORD + + m_ADE7 + :1; + +3649 +IO_WORD + + m_ADE6 + :1; + +3650 +IO_WORD + + m_ADE5 + :1; + +3651 +IO_WORD + + m_ADE4 + :1; + +3652 +IO_WORD + + m_ADE3 + :1; + +3653 +IO_WORD + + m_ADE2 + :1; + +3654 +IO_WORD + + m_ADE1 + :1; + +3655 +IO_WORD + + m_ADE0 + :1; + +3656 } + mb™ +; + +3657 } + tADERLSTR +; + +3659 +IO_BYTE + + mby‹ +; + +3661 +IO_BYTE + + m_BUSY + :1; + +3662 +IO_BYTE + + m_INT + :1; + +3663 +IO_BYTE + + m_INTE + :1; + +3664 +IO_BYTE + + m_PAUS + :1; + +3665 +IO_BYTE + + m_STS1 + :1; + +3666 +IO_BYTE + + m_STS0 + :1; + +3667 +IO_BYTE + + m_STRT + :1; + +3668 + mIO_BYTE + :1; + +3669 } + mb™ +; + +3671 + mIO_BYTE + :1; + +3672 + mIO_BYTE + :1; + +3673 + mIO_BYTE + :1; + +3674 + mIO_BYTE + :1; + +3675 +IO_BYTE + + m_STS + :2; + +3676 } + mb™c +; + +3677 } + tADCS1STR +; + +3679 +IO_BYTE + + mby‹ +; + +3681 +IO_BYTE + + m_MD1 + :1; + +3682 +IO_BYTE + + m_MD0 + :1; + +3683 +IO_BYTE + + m_S10 + :1; + +3684 +IO_BYTE + + m_ACH4 + :1; + +3685 +IO_BYTE + + m_ACH3 + :1; + +3686 +IO_BYTE + + m_ACH2 + :1; + +3687 +IO_BYTE + + m_ACH1 + :1; + +3688 +IO_BYTE + + m_ACH0 + :1; + +3689 } + mb™ +; + +3691 +IO_BYTE + + m_MD + :2; + +3692 + mIO_BYTE + :1; + +3693 +IO_BYTE + + m_ACH + :5; + +3694 } + mb™c +; + +3695 } + tADCS0STR +; + +3697 +IO_BYTE + + mby‹ +; + +3699 + mIO_BYTE + :1; + +3700 + mIO_BYTE + :1; + +3701 + mIO_BYTE + :1; + +3702 + mIO_BYTE + :1; + +3703 + mIO_BYTE + :1; + +3704 + mIO_BYTE + :1; + +3705 +IO_BYTE + + m_D9 + :1; + +3706 +IO_BYTE + + m_D8 + :1; + +3707 } + mb™ +; + +3708 } + tADCR1STR +; + +3710 +IO_BYTE + + mby‹ +; + +3712 +IO_BYTE + + m_D7 + :1; + +3713 +IO_BYTE + + m_D6 + :1; + +3714 +IO_BYTE + + m_D5 + :1; + +3715 +IO_BYTE + + m_D4 + :1; + +3716 +IO_BYTE + + m_D3 + :1; + +3717 +IO_BYTE + + m_D2 + :1; + +3718 +IO_BYTE + + m_D1 + :1; + +3719 +IO_BYTE + + m_D0 + :1; + +3720 } + mb™ +; + +3721 } + tADCR0STR +; + +3723 +IO_BYTE + + mby‹ +; + +3725 +IO_BYTE + + m_CT5 + :1; + +3726 +IO_BYTE + + m_CT4 + :1; + +3727 +IO_BYTE + + m_CT3 + :1; + +3728 +IO_BYTE + + m_CT2 + :1; + +3729 +IO_BYTE + + m_CT1 + :1; + +3730 +IO_BYTE + + m_CT0 + :1; + +3731 +IO_BYTE + + m_ST9 + :1; + +3732 +IO_BYTE + + m_ST8 + :1; + +3733 } + mb™ +; + +3734 } + tADCT1STR +; + +3736 +IO_BYTE + + mby‹ +; + +3738 +IO_BYTE + + m_ST7 + :1; + +3739 +IO_BYTE + + m_ST6 + :1; + +3740 +IO_BYTE + + m_ST5 + :1; + +3741 +IO_BYTE + + m_ST4 + :1; + +3742 +IO_BYTE + + m_ST3 + :1; + +3743 +IO_BYTE + + m_ST2 + :1; + +3744 +IO_BYTE + + m_ST1 + :1; + +3745 +IO_BYTE + + m_ST0 + :1; + +3746 } + mb™ +; + +3747 } + tADCT0STR +; + +3749 +IO_BYTE + + mby‹ +; + +3751 + mIO_BYTE + :1; + +3752 + mIO_BYTE + :1; + +3753 + mIO_BYTE + :1; + +3754 +IO_BYTE + + m_ANS4 + :1; + +3755 +IO_BYTE + + m_ANS3 + :1; + +3756 +IO_BYTE + + m_ANS2 + :1; + +3757 +IO_BYTE + + m_ANS1 + :1; + +3758 +IO_BYTE + + m_ASN0 + :1; + +3759 } + mb™ +; + +3761 + mIO_BYTE + :1; + +3762 + mIO_BYTE + :1; + +3763 + mIO_BYTE + :1; + +3764 +IO_BYTE + + m_ANS + :5; + +3765 } + mb™c +; + +3766 } + tADSCHSTR +; + +3768 +IO_BYTE + + mby‹ +; + +3770 + mIO_BYTE + :1; + +3771 + mIO_BYTE + :1; + +3772 + mIO_BYTE + :1; + +3773 +IO_BYTE + + m_ANE4 + :1; + +3774 +IO_BYTE + + m_ANE3 + :1; + +3775 +IO_BYTE + + m_ANE2 + :1; + +3776 +IO_BYTE + + m_ANE1 + :1; + +3777 +IO_BYTE + + m_ANE0 + :1; + +3778 } + mb™ +; + +3780 + mIO_BYTE + :1; + +3781 + mIO_BYTE + :1; + +3782 + mIO_BYTE + :1; + +3783 +IO_BYTE + + m_ANE + :5; + +3784 } + mb™c +; + +3785 } + tADECHSTR +; + +3787 +IO_WORD + + mwÜd +; + +3789 +IO_WORD + + m_D15 + :1; + +3790 +IO_WORD + + m_D14 + :1; + +3791 +IO_WORD + + m_D13 + :1; + +3792 +IO_WORD + + m_D12 + :1; + +3793 +IO_WORD + + m_D11 + :1; + +3794 +IO_WORD + + m_D10 + :1; + +3795 +IO_WORD + + m_D9 + :1; + +3796 +IO_WORD + + m_D8 + :1; + +3797 +IO_WORD + + m_D7 + :1; + +3798 +IO_WORD + + m_D6 + :1; + +3799 +IO_WORD + + m_D5 + :1; + +3800 +IO_WORD + + m_D4 + :1; + +3801 +IO_WORD + + m_D3 + :1; + +3802 +IO_WORD + + m_D2 + :1; + +3803 +IO_WORD + + m_D1 + :1; + +3804 +IO_WORD + + m_D0 + :1; + +3805 } + mb™ +; + +3806 } + tTMRLR0STR +; + +3808 +IO_WORD + + mwÜd +; + +3810 +IO_WORD + + m_D15 + :1; + +3811 +IO_WORD + + m_D14 + :1; + +3812 +IO_WORD + + m_D13 + :1; + +3813 +IO_WORD + + m_D12 + :1; + +3814 +IO_WORD + + m_D11 + :1; + +3815 +IO_WORD + + m_D10 + :1; + +3816 +IO_WORD + + m_D9 + :1; + +3817 +IO_WORD + + m_D8 + :1; + +3818 +IO_WORD + + m_D7 + :1; + +3819 +IO_WORD + + m_D6 + :1; + +3820 +IO_WORD + + m_D5 + :1; + +3821 +IO_WORD + + m_D4 + :1; + +3822 +IO_WORD + + m_D3 + :1; + +3823 +IO_WORD + + m_D2 + :1; + +3824 +IO_WORD + + m_D1 + :1; + +3825 +IO_WORD + + m_D0 + :1; + +3826 } + mb™ +; + +3827 } + tTMR0STR +; + +3829 +IO_WORD + + mwÜd +; + +3831 + mIO_WORD + :1; + +3832 + mIO_WORD + :1; + +3833 + mIO_WORD + :1; + +3834 +IO_WORD + + m_CSL2 + :1; + +3835 +IO_WORD + + m_CSL1 + :1; + +3836 +IO_WORD + + m_CSL0 + :1; + +3837 +IO_WORD + + m_MOD2 + :1; + +3838 +IO_WORD + + m_MOD1 + :1; + +3839 +IO_WORD + + m_MOD0 + :1; + +3840 + mIO_WORD + :1; + +3841 +IO_WORD + + m_OULT + :1; + +3842 +IO_WORD + + m_RELD + :1; + +3843 +IO_WORD + + m_INTE + :1; + +3844 +IO_WORD + + m_UF + :1; + +3845 +IO_WORD + + m_CNTE + :1; + +3846 +IO_WORD + + m_TRG + :1; + +3847 } + mb™ +; + +3849 + mIO_WORD + :1; + +3850 + mIO_WORD + :1; + +3851 + mIO_WORD + :1; + +3852 +IO_WORD + + m_CSL + :3; + +3853 +IO_WORD + + m_MOD + :3; + +3854 } + mb™c +; + +3855 } + tTMCSR0STR +; + +3857 +IO_BYTE + + mby‹ +; + +3859 + mIO_BYTE + :1; + +3860 + mIO_BYTE + :1; + +3861 + mIO_BYTE + :1; + +3862 +IO_BYTE + + m_CSL2 + :1; + +3863 +IO_BYTE + + m_CSL1 + :1; + +3864 +IO_BYTE + + m_CSL0 + :1; + +3865 +IO_BYTE + + m_MOD2 + :1; + +3866 +IO_BYTE + + m_MOD1 + :1; + +3867 } + mb™ +; + +3869 + mIO_BYTE + :3; + +3870 +IO_BYTE + + m_CSL + :3; + +3871 } + mb™c +; + +3872 } + tTMCSRH0STR +; + +3874 +IO_BYTE + + mby‹ +; + +3876 +IO_BYTE + + m_MOD0 + :1; + +3877 + mIO_BYTE + :1; + +3878 +IO_BYTE + + m_OULT + :1; + +3879 +IO_BYTE + + m_RELD + :1; + +3880 +IO_BYTE + + m_INTE + :1; + +3881 +IO_BYTE + + m_UF + :1; + +3882 +IO_BYTE + + m_CNTE + :1; + +3883 +IO_BYTE + + m_TRG + :1; + +3884 } + mb™ +; + +3885 } + tTMCSRL0STR +; + +3887 +IO_WORD + + mwÜd +; + +3889 +IO_WORD + + m_D15 + :1; + +3890 +IO_WORD + + m_D14 + :1; + +3891 +IO_WORD + + m_D13 + :1; + +3892 +IO_WORD + + m_D12 + :1; + +3893 +IO_WORD + + m_D11 + :1; + +3894 +IO_WORD + + m_D10 + :1; + +3895 +IO_WORD + + m_D9 + :1; + +3896 +IO_WORD + + m_D8 + :1; + +3897 +IO_WORD + + m_D7 + :1; + +3898 +IO_WORD + + m_D6 + :1; + +3899 +IO_WORD + + m_D5 + :1; + +3900 +IO_WORD + + m_D4 + :1; + +3901 +IO_WORD + + m_D3 + :1; + +3902 +IO_WORD + + m_D2 + :1; + +3903 +IO_WORD + + m_D1 + :1; + +3904 +IO_WORD + + m_D0 + :1; + +3905 } + mb™ +; + +3906 } + tTMRLR1STR +; + +3908 +IO_WORD + + mwÜd +; + +3910 +IO_WORD + + m_D15 + :1; + +3911 +IO_WORD + + m_D14 + :1; + +3912 +IO_WORD + + m_D13 + :1; + +3913 +IO_WORD + + m_D12 + :1; + +3914 +IO_WORD + + m_D11 + :1; + +3915 +IO_WORD + + m_D10 + :1; + +3916 +IO_WORD + + m_D9 + :1; + +3917 +IO_WORD + + m_D8 + :1; + +3918 +IO_WORD + + m_D7 + :1; + +3919 +IO_WORD + + m_D6 + :1; + +3920 +IO_WORD + + m_D5 + :1; + +3921 +IO_WORD + + m_D4 + :1; + +3922 +IO_WORD + + m_D3 + :1; + +3923 +IO_WORD + + m_D2 + :1; + +3924 +IO_WORD + + m_D1 + :1; + +3925 +IO_WORD + + m_D0 + :1; + +3926 } + mb™ +; + +3927 } + tTMR1STR +; + +3929 +IO_WORD + + mwÜd +; + +3931 + mIO_WORD + :1; + +3932 + mIO_WORD + :1; + +3933 + mIO_WORD + :1; + +3934 +IO_WORD + + m_CSL2 + :1; + +3935 +IO_WORD + + m_CSL1 + :1; + +3936 +IO_WORD + + m_CSL0 + :1; + +3937 +IO_WORD + + m_MOD2 + :1; + +3938 +IO_WORD + + m_MOD1 + :1; + +3939 +IO_WORD + + m_MOD0 + :1; + +3940 + mIO_WORD + :1; + +3941 +IO_WORD + + m_OULT + :1; + +3942 +IO_WORD + + m_RELD + :1; + +3943 +IO_WORD + + m_INTE + :1; + +3944 +IO_WORD + + m_UF + :1; + +3945 +IO_WORD + + m_CNTE + :1; + +3946 +IO_WORD + + m_TRG + :1; + +3947 } + mb™ +; + +3949 + mIO_WORD + :1; + +3950 + mIO_WORD + :1; + +3951 + mIO_WORD + :1; + +3952 +IO_WORD + + m_CSL + :3; + +3953 +IO_WORD + + m_MOD + :3; + +3954 } + mb™c +; + +3955 } + tTMCSR1STR +; + +3957 +IO_BYTE + + mby‹ +; + +3959 + mIO_BYTE + :1; + +3960 + mIO_BYTE + :1; + +3961 + mIO_BYTE + :1; + +3962 +IO_BYTE + + m_CSL2 + :1; + +3963 +IO_BYTE + + m_CSL1 + :1; + +3964 +IO_BYTE + + m_CSL0 + :1; + +3965 +IO_BYTE + + m_MOD2 + :1; + +3966 +IO_BYTE + + m_MOD1 + :1; + +3967 } + mb™ +; + +3969 + mIO_BYTE + :3; + +3970 +IO_BYTE + + m_CSL + :3; + +3971 } + mb™c +; + +3972 } + tTMCSRH1STR +; + +3974 +IO_BYTE + + mby‹ +; + +3976 +IO_BYTE + + m_MOD0 + :1; + +3977 + mIO_BYTE + :1; + +3978 +IO_BYTE + + m_OULT + :1; + +3979 +IO_BYTE + + m_RELD + :1; + +3980 +IO_BYTE + + m_INTE + :1; + +3981 +IO_BYTE + + m_UF + :1; + +3982 +IO_BYTE + + m_CNTE + :1; + +3983 +IO_BYTE + + m_TRG + :1; + +3984 } + mb™ +; + +3985 } + tTMCSRL1STR +; + +3987 +IO_WORD + + mwÜd +; + +3989 +IO_WORD + + m_D15 + :1; + +3990 +IO_WORD + + m_D14 + :1; + +3991 +IO_WORD + + m_D13 + :1; + +3992 +IO_WORD + + m_D12 + :1; + +3993 +IO_WORD + + m_D11 + :1; + +3994 +IO_WORD + + m_D10 + :1; + +3995 +IO_WORD + + m_D9 + :1; + +3996 +IO_WORD + + m_D8 + :1; + +3997 +IO_WORD + + m_D7 + :1; + +3998 +IO_WORD + + m_D6 + :1; + +3999 +IO_WORD + + m_D5 + :1; + +4000 +IO_WORD + + m_D4 + :1; + +4001 +IO_WORD + + m_D3 + :1; + +4002 +IO_WORD + + m_D2 + :1; + +4003 +IO_WORD + + m_D1 + :1; + +4004 +IO_WORD + + m_D0 + :1; + +4005 } + mb™ +; + +4006 } + tTMRLR2STR +; + +4008 +IO_WORD + + mwÜd +; + +4010 +IO_WORD + + m_D15 + :1; + +4011 +IO_WORD + + m_D14 + :1; + +4012 +IO_WORD + + m_D13 + :1; + +4013 +IO_WORD + + m_D12 + :1; + +4014 +IO_WORD + + m_D11 + :1; + +4015 +IO_WORD + + m_D10 + :1; + +4016 +IO_WORD + + m_D9 + :1; + +4017 +IO_WORD + + m_D8 + :1; + +4018 +IO_WORD + + m_D7 + :1; + +4019 +IO_WORD + + m_D6 + :1; + +4020 +IO_WORD + + m_D5 + :1; + +4021 +IO_WORD + + m_D4 + :1; + +4022 +IO_WORD + + m_D3 + :1; + +4023 +IO_WORD + + m_D2 + :1; + +4024 +IO_WORD + + m_D1 + :1; + +4025 +IO_WORD + + m_D0 + :1; + +4026 } + mb™ +; + +4027 } + tTMR2STR +; + +4029 +IO_WORD + + mwÜd +; + +4031 + mIO_WORD + :1; + +4032 + mIO_WORD + :1; + +4033 + mIO_WORD + :1; + +4034 +IO_WORD + + m_CSL2 + :1; + +4035 +IO_WORD + + m_CSL1 + :1; + +4036 +IO_WORD + + m_CSL0 + :1; + +4037 +IO_WORD + + m_MOD2 + :1; + +4038 +IO_WORD + + m_MOD1 + :1; + +4039 +IO_WORD + + m_MOD0 + :1; + +4040 + mIO_WORD + :1; + +4041 +IO_WORD + + m_OULT + :1; + +4042 +IO_WORD + + m_RELD + :1; + +4043 +IO_WORD + + m_INTE + :1; + +4044 +IO_WORD + + m_UF + :1; + +4045 +IO_WORD + + m_CNTE + :1; + +4046 +IO_WORD + + m_TRG + :1; + +4047 } + mb™ +; + +4049 + mIO_WORD + :1; + +4050 + mIO_WORD + :1; + +4051 + mIO_WORD + :1; + +4052 +IO_WORD + + m_CSL + :3; + +4053 +IO_WORD + + m_MOD + :3; + +4054 } + mb™c +; + +4055 } + tTMCSR2STR +; + +4057 +IO_BYTE + + mby‹ +; + +4059 + mIO_BYTE + :1; + +4060 + mIO_BYTE + :1; + +4061 + mIO_BYTE + :1; + +4062 +IO_BYTE + + m_CSL2 + :1; + +4063 +IO_BYTE + + m_CSL1 + :1; + +4064 +IO_BYTE + + m_CSL0 + :1; + +4065 +IO_BYTE + + m_MOD2 + :1; + +4066 +IO_BYTE + + m_MOD1 + :1; + +4067 } + mb™ +; + +4069 + mIO_BYTE + :3; + +4070 +IO_BYTE + + m_CSL + :3; + +4071 } + mb™c +; + +4072 } + tTMCSRH2STR +; + +4074 +IO_BYTE + + mby‹ +; + +4076 +IO_BYTE + + m_MOD0 + :1; + +4077 + mIO_BYTE + :1; + +4078 +IO_BYTE + + m_OULT + :1; + +4079 +IO_BYTE + + m_RELD + :1; + +4080 +IO_BYTE + + m_INTE + :1; + +4081 +IO_BYTE + + m_UF + :1; + +4082 +IO_BYTE + + m_CNTE + :1; + +4083 +IO_BYTE + + m_TRG + :1; + +4084 } + mb™ +; + +4085 } + tTMCSRL2STR +; + +4087 +IO_WORD + + mwÜd +; + +4089 +IO_WORD + + m_D15 + :1; + +4090 +IO_WORD + + m_D14 + :1; + +4091 +IO_WORD + + m_D13 + :1; + +4092 +IO_WORD + + m_D12 + :1; + +4093 +IO_WORD + + m_D11 + :1; + +4094 +IO_WORD + + m_D10 + :1; + +4095 +IO_WORD + + m_D9 + :1; + +4096 +IO_WORD + + m_D8 + :1; + +4097 +IO_WORD + + m_D7 + :1; + +4098 +IO_WORD + + m_D6 + :1; + +4099 +IO_WORD + + m_D5 + :1; + +4100 +IO_WORD + + m_D4 + :1; + +4101 +IO_WORD + + m_D3 + :1; + +4102 +IO_WORD + + m_D2 + :1; + +4103 +IO_WORD + + m_D1 + :1; + +4104 +IO_WORD + + m_D0 + :1; + +4105 } + mb™ +; + +4106 } + tTMRLR3STR +; + +4108 +IO_WORD + + mwÜd +; + +4110 +IO_WORD + + m_D15 + :1; + +4111 +IO_WORD + + m_D14 + :1; + +4112 +IO_WORD + + m_D13 + :1; + +4113 +IO_WORD + + m_D12 + :1; + +4114 +IO_WORD + + m_D11 + :1; + +4115 +IO_WORD + + m_D10 + :1; + +4116 +IO_WORD + + m_D9 + :1; + +4117 +IO_WORD + + m_D8 + :1; + +4118 +IO_WORD + + m_D7 + :1; + +4119 +IO_WORD + + m_D6 + :1; + +4120 +IO_WORD + + m_D5 + :1; + +4121 +IO_WORD + + m_D4 + :1; + +4122 +IO_WORD + + m_D3 + :1; + +4123 +IO_WORD + + m_D2 + :1; + +4124 +IO_WORD + + m_D1 + :1; + +4125 +IO_WORD + + m_D0 + :1; + +4126 } + mb™ +; + +4127 } + tTMR3STR +; + +4129 +IO_WORD + + mwÜd +; + +4131 + mIO_WORD + :1; + +4132 + mIO_WORD + :1; + +4133 + mIO_WORD + :1; + +4134 +IO_WORD + + m_CSL2 + :1; + +4135 +IO_WORD + + m_CSL1 + :1; + +4136 +IO_WORD + + m_CSL0 + :1; + +4137 +IO_WORD + + m_MOD2 + :1; + +4138 +IO_WORD + + m_MOD1 + :1; + +4139 +IO_WORD + + m_MOD0 + :1; + +4140 + mIO_WORD + :1; + +4141 +IO_WORD + + m_OULT + :1; + +4142 +IO_WORD + + m_RELD + :1; + +4143 +IO_WORD + + m_INTE + :1; + +4144 +IO_WORD + + m_UF + :1; + +4145 +IO_WORD + + m_CNTE + :1; + +4146 +IO_WORD + + m_TRG + :1; + +4147 } + mb™ +; + +4149 + mIO_WORD + :1; + +4150 + mIO_WORD + :1; + +4151 + mIO_WORD + :1; + +4152 +IO_WORD + + m_CSL + :3; + +4153 +IO_WORD + + m_MOD + :3; + +4154 } + mb™c +; + +4155 } + tTMCSR3STR +; + +4157 +IO_BYTE + + mby‹ +; + +4159 + mIO_BYTE + :1; + +4160 + mIO_BYTE + :1; + +4161 + mIO_BYTE + :1; + +4162 +IO_BYTE + + m_CSL2 + :1; + +4163 +IO_BYTE + + m_CSL1 + :1; + +4164 +IO_BYTE + + m_CSL0 + :1; + +4165 +IO_BYTE + + m_MOD2 + :1; + +4166 +IO_BYTE + + m_MOD1 + :1; + +4167 } + mb™ +; + +4169 + mIO_BYTE + :3; + +4170 +IO_BYTE + + m_CSL + :3; + +4171 } + mb™c +; + +4172 } + tTMCSRH3STR +; + +4174 +IO_BYTE + + mby‹ +; + +4176 +IO_BYTE + + m_MOD0 + :1; + +4177 + mIO_BYTE + :1; + +4178 +IO_BYTE + + m_OULT + :1; + +4179 +IO_BYTE + + m_RELD + :1; + +4180 +IO_BYTE + + m_INTE + :1; + +4181 +IO_BYTE + + m_UF + :1; + +4182 +IO_BYTE + + m_CNTE + :1; + +4183 +IO_BYTE + + m_TRG + :1; + +4184 } + mb™ +; + +4185 } + tTMCSRL3STR +; + +4187 +IO_WORD + + mwÜd +; + +4189 +IO_WORD + + m_D15 + :1; + +4190 +IO_WORD + + m_D14 + :1; + +4191 +IO_WORD + + m_D13 + :1; + +4192 +IO_WORD + + m_D12 + :1; + +4193 +IO_WORD + + m_D11 + :1; + +4194 +IO_WORD + + m_D10 + :1; + +4195 +IO_WORD + + m_D9 + :1; + +4196 +IO_WORD + + m_D8 + :1; + +4197 +IO_WORD + + m_D7 + :1; + +4198 +IO_WORD + + m_D6 + :1; + +4199 +IO_WORD + + m_D5 + :1; + +4200 +IO_WORD + + m_D4 + :1; + +4201 +IO_WORD + + m_D3 + :1; + +4202 +IO_WORD + + m_D2 + :1; + +4203 +IO_WORD + + m_D1 + :1; + +4204 +IO_WORD + + m_D0 + :1; + +4205 } + mb™ +; + +4206 } + tTMRLR4STR +; + +4208 +IO_WORD + + mwÜd +; + +4210 +IO_WORD + + m_D15 + :1; + +4211 +IO_WORD + + m_D14 + :1; + +4212 +IO_WORD + + m_D13 + :1; + +4213 +IO_WORD + + m_D12 + :1; + +4214 +IO_WORD + + m_D11 + :1; + +4215 +IO_WORD + + m_D10 + :1; + +4216 +IO_WORD + + m_D9 + :1; + +4217 +IO_WORD + + m_D8 + :1; + +4218 +IO_WORD + + m_D7 + :1; + +4219 +IO_WORD + + m_D6 + :1; + +4220 +IO_WORD + + m_D5 + :1; + +4221 +IO_WORD + + m_D4 + :1; + +4222 +IO_WORD + + m_D3 + :1; + +4223 +IO_WORD + + m_D2 + :1; + +4224 +IO_WORD + + m_D1 + :1; + +4225 +IO_WORD + + m_D0 + :1; + +4226 } + mb™ +; + +4227 } + tTMR4STR +; + +4229 +IO_WORD + + mwÜd +; + +4231 + mIO_WORD + :1; + +4232 + mIO_WORD + :1; + +4233 + mIO_WORD + :1; + +4234 +IO_WORD + + m_CSL2 + :1; + +4235 +IO_WORD + + m_CSL1 + :1; + +4236 +IO_WORD + + m_CSL0 + :1; + +4237 +IO_WORD + + m_MOD2 + :1; + +4238 +IO_WORD + + m_MOD1 + :1; + +4239 +IO_WORD + + m_MOD0 + :1; + +4240 + mIO_WORD + :1; + +4241 +IO_WORD + + m_OULT + :1; + +4242 +IO_WORD + + m_RELD + :1; + +4243 +IO_WORD + + m_INTE + :1; + +4244 +IO_WORD + + m_UF + :1; + +4245 +IO_WORD + + m_CNTE + :1; + +4246 +IO_WORD + + m_TRG + :1; + +4247 } + mb™ +; + +4249 + mIO_WORD + :1; + +4250 + mIO_WORD + :1; + +4251 + mIO_WORD + :1; + +4252 +IO_WORD + + m_CSL + :3; + +4253 +IO_WORD + + m_MOD + :3; + +4254 } + mb™c +; + +4255 } + tTMCSR4STR +; + +4257 +IO_BYTE + + mby‹ +; + +4259 + mIO_BYTE + :1; + +4260 + mIO_BYTE + :1; + +4261 + mIO_BYTE + :1; + +4262 +IO_BYTE + + m_CSL2 + :1; + +4263 +IO_BYTE + + m_CSL1 + :1; + +4264 +IO_BYTE + + m_CSL0 + :1; + +4265 +IO_BYTE + + m_MOD2 + :1; + +4266 +IO_BYTE + + m_MOD1 + :1; + +4267 } + mb™ +; + +4269 + mIO_BYTE + :3; + +4270 +IO_BYTE + + m_CSL + :3; + +4271 } + mb™c +; + +4272 } + tTMCSRH4STR +; + +4274 +IO_BYTE + + mby‹ +; + +4276 +IO_BYTE + + m_MOD0 + :1; + +4277 + mIO_BYTE + :1; + +4278 +IO_BYTE + + m_OULT + :1; + +4279 +IO_BYTE + + m_RELD + :1; + +4280 +IO_BYTE + + m_INTE + :1; + +4281 +IO_BYTE + + m_UF + :1; + +4282 +IO_BYTE + + m_CNTE + :1; + +4283 +IO_BYTE + + m_TRG + :1; + +4284 } + mb™ +; + +4285 } + tTMCSRL4STR +; + +4287 +IO_WORD + + mwÜd +; + +4289 +IO_WORD + + m_D15 + :1; + +4290 +IO_WORD + + m_D14 + :1; + +4291 +IO_WORD + + m_D13 + :1; + +4292 +IO_WORD + + m_D12 + :1; + +4293 +IO_WORD + + m_D11 + :1; + +4294 +IO_WORD + + m_D10 + :1; + +4295 +IO_WORD + + m_D9 + :1; + +4296 +IO_WORD + + m_D8 + :1; + +4297 +IO_WORD + + m_D7 + :1; + +4298 +IO_WORD + + m_D6 + :1; + +4299 +IO_WORD + + m_D5 + :1; + +4300 +IO_WORD + + m_D4 + :1; + +4301 +IO_WORD + + m_D3 + :1; + +4302 +IO_WORD + + m_D2 + :1; + +4303 +IO_WORD + + m_D1 + :1; + +4304 +IO_WORD + + m_D0 + :1; + +4305 } + mb™ +; + +4306 } + tTMRLR5STR +; + +4308 +IO_WORD + + mwÜd +; + +4310 +IO_WORD + + m_D15 + :1; + +4311 +IO_WORD + + m_D14 + :1; + +4312 +IO_WORD + + m_D13 + :1; + +4313 +IO_WORD + + m_D12 + :1; + +4314 +IO_WORD + + m_D11 + :1; + +4315 +IO_WORD + + m_D10 + :1; + +4316 +IO_WORD + + m_D9 + :1; + +4317 +IO_WORD + + m_D8 + :1; + +4318 +IO_WORD + + m_D7 + :1; + +4319 +IO_WORD + + m_D6 + :1; + +4320 +IO_WORD + + m_D5 + :1; + +4321 +IO_WORD + + m_D4 + :1; + +4322 +IO_WORD + + m_D3 + :1; + +4323 +IO_WORD + + m_D2 + :1; + +4324 +IO_WORD + + m_D1 + :1; + +4325 +IO_WORD + + m_D0 + :1; + +4326 } + mb™ +; + +4327 } + tTMR5STR +; + +4329 +IO_WORD + + mwÜd +; + +4331 + mIO_WORD + :1; + +4332 + mIO_WORD + :1; + +4333 + mIO_WORD + :1; + +4334 +IO_WORD + + m_CSL2 + :1; + +4335 +IO_WORD + + m_CSL1 + :1; + +4336 +IO_WORD + + m_CSL0 + :1; + +4337 +IO_WORD + + m_MOD2 + :1; + +4338 +IO_WORD + + m_MOD1 + :1; + +4339 +IO_WORD + + m_MOD0 + :1; + +4340 + mIO_WORD + :1; + +4341 +IO_WORD + + m_OULT + :1; + +4342 +IO_WORD + + m_RELD + :1; + +4343 +IO_WORD + + m_INTE + :1; + +4344 +IO_WORD + + m_UF + :1; + +4345 +IO_WORD + + m_CNTE + :1; + +4346 +IO_WORD + + m_TRG + :1; + +4347 } + mb™ +; + +4349 + mIO_WORD + :1; + +4350 + mIO_WORD + :1; + +4351 + mIO_WORD + :1; + +4352 +IO_WORD + + m_CSL + :3; + +4353 +IO_WORD + + m_MOD + :3; + +4354 } + mb™c +; + +4355 } + tTMCSR5STR +; + +4357 +IO_BYTE + + mby‹ +; + +4359 + mIO_BYTE + :1; + +4360 + mIO_BYTE + :1; + +4361 + mIO_BYTE + :1; + +4362 +IO_BYTE + + m_CSL2 + :1; + +4363 +IO_BYTE + + m_CSL1 + :1; + +4364 +IO_BYTE + + m_CSL0 + :1; + +4365 +IO_BYTE + + m_MOD2 + :1; + +4366 +IO_BYTE + + m_MOD1 + :1; + +4367 } + mb™ +; + +4369 + mIO_BYTE + :3; + +4370 +IO_BYTE + + m_CSL + :3; + +4371 } + mb™c +; + +4372 } + tTMCSRH5STR +; + +4374 +IO_BYTE + + mby‹ +; + +4376 +IO_BYTE + + m_MOD0 + :1; + +4377 + mIO_BYTE + :1; + +4378 +IO_BYTE + + m_OULT + :1; + +4379 +IO_BYTE + + m_RELD + :1; + +4380 +IO_BYTE + + m_INTE + :1; + +4381 +IO_BYTE + + m_UF + :1; + +4382 +IO_BYTE + + m_CNTE + :1; + +4383 +IO_BYTE + + m_TRG + :1; + +4384 } + mb™ +; + +4385 } + tTMCSRL5STR +; + +4387 +IO_WORD + + mwÜd +; + +4389 +IO_WORD + + m_D15 + :1; + +4390 +IO_WORD + + m_D14 + :1; + +4391 +IO_WORD + + m_D13 + :1; + +4392 +IO_WORD + + m_D12 + :1; + +4393 +IO_WORD + + m_D11 + :1; + +4394 +IO_WORD + + m_D10 + :1; + +4395 +IO_WORD + + m_D9 + :1; + +4396 +IO_WORD + + m_D8 + :1; + +4397 +IO_WORD + + m_D7 + :1; + +4398 +IO_WORD + + m_D6 + :1; + +4399 +IO_WORD + + m_D5 + :1; + +4400 +IO_WORD + + m_D4 + :1; + +4401 +IO_WORD + + m_D3 + :1; + +4402 +IO_WORD + + m_D2 + :1; + +4403 +IO_WORD + + m_D1 + :1; + +4404 +IO_WORD + + m_D0 + :1; + +4405 } + mb™ +; + +4406 } + tTMRLR6STR +; + +4408 +IO_WORD + + mwÜd +; + +4410 +IO_WORD + + m_D15 + :1; + +4411 +IO_WORD + + m_D14 + :1; + +4412 +IO_WORD + + m_D13 + :1; + +4413 +IO_WORD + + m_D12 + :1; + +4414 +IO_WORD + + m_D11 + :1; + +4415 +IO_WORD + + m_D10 + :1; + +4416 +IO_WORD + + m_D9 + :1; + +4417 +IO_WORD + + m_D8 + :1; + +4418 +IO_WORD + + m_D7 + :1; + +4419 +IO_WORD + + m_D6 + :1; + +4420 +IO_WORD + + m_D5 + :1; + +4421 +IO_WORD + + m_D4 + :1; + +4422 +IO_WORD + + m_D3 + :1; + +4423 +IO_WORD + + m_D2 + :1; + +4424 +IO_WORD + + m_D1 + :1; + +4425 +IO_WORD + + m_D0 + :1; + +4426 } + mb™ +; + +4427 } + tTMR6STR +; + +4429 +IO_WORD + + mwÜd +; + +4431 + mIO_WORD + :1; + +4432 + mIO_WORD + :1; + +4433 + mIO_WORD + :1; + +4434 +IO_WORD + + m_CSL2 + :1; + +4435 +IO_WORD + + m_CSL1 + :1; + +4436 +IO_WORD + + m_CSL0 + :1; + +4437 +IO_WORD + + m_MOD2 + :1; + +4438 +IO_WORD + + m_MOD1 + :1; + +4439 +IO_WORD + + m_MOD0 + :1; + +4440 + mIO_WORD + :1; + +4441 +IO_WORD + + m_OULT + :1; + +4442 +IO_WORD + + m_RELD + :1; + +4443 +IO_WORD + + m_INTE + :1; + +4444 +IO_WORD + + m_UF + :1; + +4445 +IO_WORD + + m_CNTE + :1; + +4446 +IO_WORD + + m_TRG + :1; + +4447 } + mb™ +; + +4449 + mIO_WORD + :1; + +4450 + mIO_WORD + :1; + +4451 + mIO_WORD + :1; + +4452 +IO_WORD + + m_CSL + :3; + +4453 +IO_WORD + + m_MOD + :3; + +4454 } + mb™c +; + +4455 } + tTMCSR6STR +; + +4457 +IO_BYTE + + mby‹ +; + +4459 + mIO_BYTE + :1; + +4460 + mIO_BYTE + :1; + +4461 + mIO_BYTE + :1; + +4462 +IO_BYTE + + m_CSL2 + :1; + +4463 +IO_BYTE + + m_CSL1 + :1; + +4464 +IO_BYTE + + m_CSL0 + :1; + +4465 +IO_BYTE + + m_MOD2 + :1; + +4466 +IO_BYTE + + m_MOD1 + :1; + +4467 } + mb™ +; + +4469 + mIO_BYTE + :3; + +4470 +IO_BYTE + + m_CSL + :3; + +4471 } + mb™c +; + +4472 } + tTMCSRH6STR +; + +4474 +IO_BYTE + + mby‹ +; + +4476 +IO_BYTE + + m_MOD0 + :1; + +4477 + mIO_BYTE + :1; + +4478 +IO_BYTE + + m_OULT + :1; + +4479 +IO_BYTE + + m_RELD + :1; + +4480 +IO_BYTE + + m_INTE + :1; + +4481 +IO_BYTE + + m_UF + :1; + +4482 +IO_BYTE + + m_CNTE + :1; + +4483 +IO_BYTE + + m_TRG + :1; + +4484 } + mb™ +; + +4485 } + tTMCSRL6STR +; + +4487 +IO_WORD + + mwÜd +; + +4489 +IO_WORD + + m_D15 + :1; + +4490 +IO_WORD + + m_D14 + :1; + +4491 +IO_WORD + + m_D13 + :1; + +4492 +IO_WORD + + m_D12 + :1; + +4493 +IO_WORD + + m_D11 + :1; + +4494 +IO_WORD + + m_D10 + :1; + +4495 +IO_WORD + + m_D9 + :1; + +4496 +IO_WORD + + m_D8 + :1; + +4497 +IO_WORD + + m_D7 + :1; + +4498 +IO_WORD + + m_D6 + :1; + +4499 +IO_WORD + + m_D5 + :1; + +4500 +IO_WORD + + m_D4 + :1; + +4501 +IO_WORD + + m_D3 + :1; + +4502 +IO_WORD + + m_D2 + :1; + +4503 +IO_WORD + + m_D1 + :1; + +4504 +IO_WORD + + m_D0 + :1; + +4505 } + mb™ +; + +4506 } + tTMRLR7STR +; + +4508 +IO_WORD + + mwÜd +; + +4510 +IO_WORD + + m_D15 + :1; + +4511 +IO_WORD + + m_D14 + :1; + +4512 +IO_WORD + + m_D13 + :1; + +4513 +IO_WORD + + m_D12 + :1; + +4514 +IO_WORD + + m_D11 + :1; + +4515 +IO_WORD + + m_D10 + :1; + +4516 +IO_WORD + + m_D9 + :1; + +4517 +IO_WORD + + m_D8 + :1; + +4518 +IO_WORD + + m_D7 + :1; + +4519 +IO_WORD + + m_D6 + :1; + +4520 +IO_WORD + + m_D5 + :1; + +4521 +IO_WORD + + m_D4 + :1; + +4522 +IO_WORD + + m_D3 + :1; + +4523 +IO_WORD + + m_D2 + :1; + +4524 +IO_WORD + + m_D1 + :1; + +4525 +IO_WORD + + m_D0 + :1; + +4526 } + mb™ +; + +4527 } + tTMR7STR +; + +4529 +IO_WORD + + mwÜd +; + +4531 + mIO_WORD + :1; + +4532 + mIO_WORD + :1; + +4533 + mIO_WORD + :1; + +4534 +IO_WORD + + m_CSL2 + :1; + +4535 +IO_WORD + + m_CSL1 + :1; + +4536 +IO_WORD + + m_CSL0 + :1; + +4537 +IO_WORD + + m_MOD2 + :1; + +4538 +IO_WORD + + m_MOD1 + :1; + +4539 +IO_WORD + + m_MOD0 + :1; + +4540 + mIO_WORD + :1; + +4541 +IO_WORD + + m_OULT + :1; + +4542 +IO_WORD + + m_RELD + :1; + +4543 +IO_WORD + + m_INTE + :1; + +4544 +IO_WORD + + m_UF + :1; + +4545 +IO_WORD + + m_CNTE + :1; + +4546 +IO_WORD + + m_TRG + :1; + +4547 } + mb™ +; + +4549 + mIO_WORD + :1; + +4550 + mIO_WORD + :1; + +4551 + mIO_WORD + :1; + +4552 +IO_WORD + + m_CSL + :3; + +4553 +IO_WORD + + m_MOD + :3; + +4554 } + mb™c +; + +4555 } + tTMCSR7STR +; + +4557 +IO_BYTE + + mby‹ +; + +4559 + mIO_BYTE + :1; + +4560 + mIO_BYTE + :1; + +4561 + mIO_BYTE + :1; + +4562 +IO_BYTE + + m_CSL2 + :1; + +4563 +IO_BYTE + + m_CSL1 + :1; + +4564 +IO_BYTE + + m_CSL0 + :1; + +4565 +IO_BYTE + + m_MOD2 + :1; + +4566 +IO_BYTE + + m_MOD1 + :1; + +4567 } + mb™ +; + +4569 + mIO_BYTE + :3; + +4570 +IO_BYTE + + m_CSL + :3; + +4571 } + mb™c +; + +4572 } + tTMCSRH7STR +; + +4574 +IO_BYTE + + mby‹ +; + +4576 +IO_BYTE + + m_MOD0 + :1; + +4577 + mIO_BYTE + :1; + +4578 +IO_BYTE + + m_OULT + :1; + +4579 +IO_BYTE + + m_RELD + :1; + +4580 +IO_BYTE + + m_INTE + :1; + +4581 +IO_BYTE + + m_UF + :1; + +4582 +IO_BYTE + + m_CNTE + :1; + +4583 +IO_BYTE + + m_TRG + :1; + +4584 } + mb™ +; + +4585 } + tTMCSRL7STR +; + +4587 +IO_WORD + + mwÜd +; + +4589 +IO_WORD + + m_T15 + :1; + +4590 +IO_WORD + + m_T14 + :1; + +4591 +IO_WORD + + m_T13 + :1; + +4592 +IO_WORD + + m_T12 + :1; + +4593 +IO_WORD + + m_T11 + :1; + +4594 +IO_WORD + + m_T10 + :1; + +4595 +IO_WORD + + m_T9 + :1; + +4596 +IO_WORD + + m_T8 + :1; + +4597 +IO_WORD + + m_T7 + :1; + +4598 +IO_WORD + + m_T6 + :1; + +4599 +IO_WORD + + m_T5 + :1; + +4600 +IO_WORD + + m_T4 + :1; + +4601 +IO_WORD + + m_T3 + :1; + +4602 +IO_WORD + + m_T2 + :1; + +4603 +IO_WORD + + m_T1 + :1; + +4604 +IO_WORD + + m_T0 + :1; + +4605 } + mb™ +; + +4606 } + tTCDT0STR +; + +4608 +IO_BYTE + + mby‹ +; + +4610 +IO_BYTE + + m_ECLK + :1; + +4611 +IO_BYTE + + m_IVF + :1; + +4612 +IO_BYTE + + m_IVFE + :1; + +4613 +IO_BYTE + + m_STOP + :1; + +4614 +IO_BYTE + + m_MODE + :1; + +4615 +IO_BYTE + + m_CLR + :1; + +4616 +IO_BYTE + + m_CLK1 + :1; + +4617 +IO_BYTE + + m_CLK0 + :1; + +4618 } + mb™ +; + +4620 + mIO_BYTE + :1; + +4621 + mIO_BYTE + :1; + +4622 + mIO_BYTE + :1; + +4623 + mIO_BYTE + :1; + +4624 + mIO_BYTE + :1; + +4625 + mIO_BYTE + :1; + +4626 +IO_BYTE + + m_CLK + :2; + +4627 } + mb™c +; + +4628 } + tTCCS0STR +; + +4630 +IO_WORD + + mwÜd +; + +4632 +IO_WORD + + m_T15 + :1; + +4633 +IO_WORD + + m_T14 + :1; + +4634 +IO_WORD + + m_T13 + :1; + +4635 +IO_WORD + + m_T12 + :1; + +4636 +IO_WORD + + m_T11 + :1; + +4637 +IO_WORD + + m_T10 + :1; + +4638 +IO_WORD + + m_T9 + :1; + +4639 +IO_WORD + + m_T8 + :1; + +4640 +IO_WORD + + m_T7 + :1; + +4641 +IO_WORD + + m_T6 + :1; + +4642 +IO_WORD + + m_T5 + :1; + +4643 +IO_WORD + + m_T4 + :1; + +4644 +IO_WORD + + m_T3 + :1; + +4645 +IO_WORD + + m_T2 + :1; + +4646 +IO_WORD + + m_T1 + :1; + +4647 +IO_WORD + + m_T0 + :1; + +4648 } + mb™ +; + +4649 } + tTCDT1STR +; + +4651 +IO_BYTE + + mby‹ +; + +4653 +IO_BYTE + + m_ECLK + :1; + +4654 +IO_BYTE + + m_IVF + :1; + +4655 +IO_BYTE + + m_IVFE + :1; + +4656 +IO_BYTE + + m_STOP + :1; + +4657 +IO_BYTE + + m_MODE + :1; + +4658 +IO_BYTE + + m_CLR + :1; + +4659 +IO_BYTE + + m_CLK1 + :1; + +4660 +IO_BYTE + + m_CLK0 + :1; + +4661 } + mb™ +; + +4663 + mIO_BYTE + :1; + +4664 + mIO_BYTE + :1; + +4665 + mIO_BYTE + :1; + +4666 + mIO_BYTE + :1; + +4667 + mIO_BYTE + :1; + +4668 + mIO_BYTE + :1; + +4669 +IO_BYTE + + m_CLK + :2; + +4670 } + mb™c +; + +4671 } + tTCCS1STR +; + +4673 +IO_WORD + + mwÜd +; + +4675 +IO_WORD + + m_T15 + :1; + +4676 +IO_WORD + + m_T14 + :1; + +4677 +IO_WORD + + m_T13 + :1; + +4678 +IO_WORD + + m_T12 + :1; + +4679 +IO_WORD + + m_T11 + :1; + +4680 +IO_WORD + + m_T10 + :1; + +4681 +IO_WORD + + m_T9 + :1; + +4682 +IO_WORD + + m_T8 + :1; + +4683 +IO_WORD + + m_T7 + :1; + +4684 +IO_WORD + + m_T6 + :1; + +4685 +IO_WORD + + m_T5 + :1; + +4686 +IO_WORD + + m_T4 + :1; + +4687 +IO_WORD + + m_T3 + :1; + +4688 +IO_WORD + + m_T2 + :1; + +4689 +IO_WORD + + m_T1 + :1; + +4690 +IO_WORD + + m_T0 + :1; + +4691 } + mb™ +; + +4692 } + tTCDT2STR +; + +4694 +IO_BYTE + + mby‹ +; + +4696 +IO_BYTE + + m_ECLK + :1; + +4697 +IO_BYTE + + m_IVF + :1; + +4698 +IO_BYTE + + m_IVFE + :1; + +4699 +IO_BYTE + + m_STOP + :1; + +4700 +IO_BYTE + + m_MODE + :1; + +4701 +IO_BYTE + + m_CLR + :1; + +4702 +IO_BYTE + + m_CLK1 + :1; + +4703 +IO_BYTE + + m_CLK0 + :1; + +4704 } + mb™ +; + +4706 + mIO_BYTE + :1; + +4707 + mIO_BYTE + :1; + +4708 + mIO_BYTE + :1; + +4709 + mIO_BYTE + :1; + +4710 + mIO_BYTE + :1; + +4711 + mIO_BYTE + :1; + +4712 +IO_BYTE + + m_CLK + :2; + +4713 } + mb™c +; + +4714 } + tTCCS2STR +; + +4716 +IO_WORD + + mwÜd +; + +4718 +IO_WORD + + m_T15 + :1; + +4719 +IO_WORD + + m_T14 + :1; + +4720 +IO_WORD + + m_T13 + :1; + +4721 +IO_WORD + + m_T12 + :1; + +4722 +IO_WORD + + m_T11 + :1; + +4723 +IO_WORD + + m_T10 + :1; + +4724 +IO_WORD + + m_T9 + :1; + +4725 +IO_WORD + + m_T8 + :1; + +4726 +IO_WORD + + m_T7 + :1; + +4727 +IO_WORD + + m_T6 + :1; + +4728 +IO_WORD + + m_T5 + :1; + +4729 +IO_WORD + + m_T4 + :1; + +4730 +IO_WORD + + m_T3 + :1; + +4731 +IO_WORD + + m_T2 + :1; + +4732 +IO_WORD + + m_T1 + :1; + +4733 +IO_WORD + + m_T0 + :1; + +4734 } + mb™ +; + +4735 } + tTCDT3STR +; + +4737 +IO_BYTE + + mby‹ +; + +4739 +IO_BYTE + + m_ECLK + :1; + +4740 +IO_BYTE + + m_IVF + :1; + +4741 +IO_BYTE + + m_IVFE + :1; + +4742 +IO_BYTE + + m_STOP + :1; + +4743 +IO_BYTE + + m_MODE + :1; + +4744 +IO_BYTE + + m_CLR + :1; + +4745 +IO_BYTE + + m_CLK1 + :1; + +4746 +IO_BYTE + + m_CLK0 + :1; + +4747 } + mb™ +; + +4749 + mIO_BYTE + :1; + +4750 + mIO_BYTE + :1; + +4751 + mIO_BYTE + :1; + +4752 + mIO_BYTE + :1; + +4753 + mIO_BYTE + :1; + +4754 + mIO_BYTE + :1; + +4755 +IO_BYTE + + m_CLK + :2; + +4756 } + mb™c +; + +4757 } + tTCCS3STR +; + +4759 +IO_LWORD + + mlwÜd +; + +4761 +IO_LWORD + + m_DENB + :1; + +4762 +IO_LWORD + + m_PAUS + :1; + +4763 +IO_LWORD + + m_STRG + :1; + +4764 +IO_LWORD + + m_IS4 + :1; + +4765 +IO_LWORD + + m_IS3 + :1; + +4766 +IO_LWORD + + m_IS2 + :1; + +4767 +IO_LWORD + + m_IS1 + :1; + +4768 +IO_LWORD + + m_IS0 + :1; + +4769 +IO_LWORD + + m_EIS3 + :1; + +4770 +IO_LWORD + + m_EIS2 + :1; + +4771 +IO_LWORD + + m_EIS1 + :1; + +4772 +IO_LWORD + + m_EIS0 + :1; + +4773 +IO_LWORD + + m_BLK3 + :1; + +4774 +IO_LWORD + + m_BLK2 + :1; + +4775 +IO_LWORD + + m_BLK1 + :1; + +4776 +IO_LWORD + + m_BLK0 + :1; + +4777 +IO_LWORD + + m_DTCF + :1; + +4778 +IO_LWORD + + m_DTCE + :1; + +4779 +IO_LWORD + + m_DTCD + :1; + +4780 +IO_LWORD + + m_DTCC + :1; + +4781 +IO_LWORD + + m_DTCB + :1; + +4782 +IO_LWORD + + m_DTCA + :1; + +4783 +IO_LWORD + + m_DTC9 + :1; + +4784 +IO_LWORD + + m_DTC8 + :1; + +4785 +IO_LWORD + + m_DTC7 + :1; + +4786 +IO_LWORD + + m_DTC6 + :1; + +4787 +IO_LWORD + + m_DTC5 + :1; + +4788 +IO_LWORD + + m_DTC4 + :1; + +4789 +IO_LWORD + + m_DTC3 + :1; + +4790 +IO_LWORD + + m_DTC2 + :1; + +4791 +IO_LWORD + + m_DTC1 + :1; + +4792 +IO_LWORD + + m_DTC0 + :1; + +4793 } + mb™ +; + +4795 + mIO_LWORD + :1; + +4796 + mIO_LWORD + :1; + +4797 + mIO_LWORD + :1; + +4798 +IO_LWORD + + m_IS + :5; + +4799 +IO_LWORD + + m_EIS + :4; + +4800 +IO_LWORD + + m_BLK + :4; + +4801 +IO_LWORD + + m_DTC + :16; + +4802 } + mb™c +; + +4803 } + tDMACA0STR +; + +4805 +IO_LWORD + + mlwÜd +; + +4807 +IO_LWORD + + m_TYPE1 + :1; + +4808 +IO_LWORD + + m_TYPE0 + :1; + +4809 +IO_LWORD + + m_MOD1 + :1; + +4810 +IO_LWORD + + m_MOD0 + :1; + +4811 +IO_LWORD + + m_WS1 + :1; + +4812 +IO_LWORD + + m_WS0 + :1; + +4813 +IO_LWORD + + m_SADM + :1; + +4814 +IO_LWORD + + m_DADM + :1; + +4815 +IO_LWORD + + m_DTCR + :1; + +4816 +IO_LWORD + + m_SADR + :1; + +4817 +IO_LWORD + + m_DADR + :1; + +4818 +IO_LWORD + + m_ERIE + :1; + +4819 +IO_LWORD + + m_EDIE + :1; + +4820 +IO_LWORD + + m_DSS2 + :1; + +4821 +IO_LWORD + + m_DSS1 + :1; + +4822 +IO_LWORD + + m_DSS0 + :1; + +4823 +IO_LWORD + + m_SASZ7 + :1; + +4824 +IO_LWORD + + m_SASZ6 + :1; + +4825 +IO_LWORD + + m_SASZ5 + :1; + +4826 +IO_LWORD + + m_SASZ4 + :1; + +4827 +IO_LWORD + + m_SASZ3 + :1; + +4828 +IO_LWORD + + m_SASZ2 + :1; + +4829 +IO_LWORD + + m_SASZ1 + :1; + +4830 +IO_LWORD + + m_SASZ0 + :1; + +4831 +IO_LWORD + + m_DASZ7 + :1; + +4832 +IO_LWORD + + m_DASZ6 + :1; + +4833 +IO_LWORD + + m_DASZ5 + :1; + +4834 +IO_LWORD + + m_DASZ4 + :1; + +4835 +IO_LWORD + + m_DASZ3 + :1; + +4836 +IO_LWORD + + m_DASZ2 + :1; + +4837 +IO_LWORD + + m_DASZ1 + :1; + +4838 +IO_LWORD + + m_DASZ0 + :1; + +4839 } + mb™ +; + +4841 +IO_LWORD + + m_TYPE + :2; + +4842 +IO_LWORD + + m_MOD + :2; + +4843 +IO_LWORD + + m_WS + :2; + +4844 + mIO_LWORD + :1; + +4845 + mIO_LWORD + :1; + +4846 + mIO_LWORD + :1; + +4847 + mIO_LWORD + :1; + +4848 + mIO_LWORD + :1; + +4849 + mIO_LWORD + :1; + +4850 + mIO_LWORD + :1; + +4851 +IO_LWORD + + m_DSS + :3; + +4852 +IO_LWORD + + m_SASZ + :8; + +4853 +IO_LWORD + + m_DASZ + :8; + +4854 } + mb™c +; + +4855 } + tDMACB0STR +; + +4857 +IO_LWORD + + mlwÜd +; + +4859 +IO_LWORD + + m_DENB + :1; + +4860 +IO_LWORD + + m_PAUS + :1; + +4861 +IO_LWORD + + m_STRG + :1; + +4862 +IO_LWORD + + m_IS4 + :1; + +4863 +IO_LWORD + + m_IS3 + :1; + +4864 +IO_LWORD + + m_IS2 + :1; + +4865 +IO_LWORD + + m_IS1 + :1; + +4866 +IO_LWORD + + m_IS0 + :1; + +4867 +IO_LWORD + + m_EIS3 + :1; + +4868 +IO_LWORD + + m_EIS2 + :1; + +4869 +IO_LWORD + + m_EIS1 + :1; + +4870 +IO_LWORD + + m_EIS0 + :1; + +4871 +IO_LWORD + + m_BLK3 + :1; + +4872 +IO_LWORD + + m_BLK2 + :1; + +4873 +IO_LWORD + + m_BLK1 + :1; + +4874 +IO_LWORD + + m_BLK0 + :1; + +4875 +IO_LWORD + + m_DTCF + :1; + +4876 +IO_LWORD + + m_DTCE + :1; + +4877 +IO_LWORD + + m_DTCD + :1; + +4878 +IO_LWORD + + m_DTCC + :1; + +4879 +IO_LWORD + + m_DTCB + :1; + +4880 +IO_LWORD + + m_DTCA + :1; + +4881 +IO_LWORD + + m_DTC9 + :1; + +4882 +IO_LWORD + + m_DTC8 + :1; + +4883 +IO_LWORD + + m_DTC7 + :1; + +4884 +IO_LWORD + + m_DTC6 + :1; + +4885 +IO_LWORD + + m_DTC5 + :1; + +4886 +IO_LWORD + + m_DTC4 + :1; + +4887 +IO_LWORD + + m_DTC3 + :1; + +4888 +IO_LWORD + + m_DTC2 + :1; + +4889 +IO_LWORD + + m_DTC1 + :1; + +4890 +IO_LWORD + + m_DTC0 + :1; + +4891 } + mb™ +; + +4893 + mIO_LWORD + :1; + +4894 + mIO_LWORD + :1; + +4895 + mIO_LWORD + :1; + +4896 +IO_LWORD + + m_IS + :5; + +4897 +IO_LWORD + + m_EIS + :4; + +4898 +IO_LWORD + + m_BLK + :4; + +4899 +IO_LWORD + + m_DTC + :16; + +4900 } + mb™c +; + +4901 } + tDMACA1STR +; + +4903 +IO_LWORD + + mlwÜd +; + +4905 +IO_LWORD + + m_TYPE1 + :1; + +4906 +IO_LWORD + + m_TYPE0 + :1; + +4907 +IO_LWORD + + m_MOD1 + :1; + +4908 +IO_LWORD + + m_MOD0 + :1; + +4909 +IO_LWORD + + m_WS1 + :1; + +4910 +IO_LWORD + + m_WS0 + :1; + +4911 +IO_LWORD + + m_SADM + :1; + +4912 +IO_LWORD + + m_DADM + :1; + +4913 +IO_LWORD + + m_DTCR + :1; + +4914 +IO_LWORD + + m_SADR + :1; + +4915 +IO_LWORD + + m_DADR + :1; + +4916 +IO_LWORD + + m_ERIE + :1; + +4917 +IO_LWORD + + m_EDIE + :1; + +4918 +IO_LWORD + + m_DSS2 + :1; + +4919 +IO_LWORD + + m_DSS1 + :1; + +4920 +IO_LWORD + + m_DSS0 + :1; + +4921 +IO_LWORD + + m_SASZ7 + :1; + +4922 +IO_LWORD + + m_SASZ6 + :1; + +4923 +IO_LWORD + + m_SASZ5 + :1; + +4924 +IO_LWORD + + m_SASZ4 + :1; + +4925 +IO_LWORD + + m_SASZ3 + :1; + +4926 +IO_LWORD + + m_SASZ2 + :1; + +4927 +IO_LWORD + + m_SASZ1 + :1; + +4928 +IO_LWORD + + m_SASZ0 + :1; + +4929 +IO_LWORD + + m_DASZ7 + :1; + +4930 +IO_LWORD + + m_DASZ6 + :1; + +4931 +IO_LWORD + + m_DASZ5 + :1; + +4932 +IO_LWORD + + m_DASZ4 + :1; + +4933 +IO_LWORD + + m_DASZ3 + :1; + +4934 +IO_LWORD + + m_DASZ2 + :1; + +4935 +IO_LWORD + + m_DASZ1 + :1; + +4936 +IO_LWORD + + m_DASZ0 + :1; + +4937 } + mb™ +; + +4939 +IO_LWORD + + m_TYPE + :2; + +4940 +IO_LWORD + + m_MOD + :2; + +4941 +IO_LWORD + + m_WS + :2; + +4942 + mIO_LWORD + :1; + +4943 + mIO_LWORD + :1; + +4944 + mIO_LWORD + :1; + +4945 + mIO_LWORD + :1; + +4946 + mIO_LWORD + :1; + +4947 + mIO_LWORD + :1; + +4948 + mIO_LWORD + :1; + +4949 +IO_LWORD + + m_DSS + :3; + +4950 +IO_LWORD + + m_SASZ + :8; + +4951 +IO_LWORD + + m_DASZ + :8; + +4952 } + mb™c +; + +4953 } + tDMACB1STR +; + +4955 +IO_LWORD + + mlwÜd +; + +4957 +IO_LWORD + + m_DENB + :1; + +4958 +IO_LWORD + + m_PAUS + :1; + +4959 +IO_LWORD + + m_STRG + :1; + +4960 +IO_LWORD + + m_IS4 + :1; + +4961 +IO_LWORD + + m_IS3 + :1; + +4962 +IO_LWORD + + m_IS2 + :1; + +4963 +IO_LWORD + + m_IS1 + :1; + +4964 +IO_LWORD + + m_IS0 + :1; + +4965 +IO_LWORD + + m_EIS3 + :1; + +4966 +IO_LWORD + + m_EIS2 + :1; + +4967 +IO_LWORD + + m_EIS1 + :1; + +4968 +IO_LWORD + + m_EIS0 + :1; + +4969 +IO_LWORD + + m_BLK3 + :1; + +4970 +IO_LWORD + + m_BLK2 + :1; + +4971 +IO_LWORD + + m_BLK1 + :1; + +4972 +IO_LWORD + + m_BLK0 + :1; + +4973 +IO_LWORD + + m_DTCF + :1; + +4974 +IO_LWORD + + m_DTCE + :1; + +4975 +IO_LWORD + + m_DTCD + :1; + +4976 +IO_LWORD + + m_DTCC + :1; + +4977 +IO_LWORD + + m_DTCB + :1; + +4978 +IO_LWORD + + m_DTCA + :1; + +4979 +IO_LWORD + + m_DTC9 + :1; + +4980 +IO_LWORD + + m_DTC8 + :1; + +4981 +IO_LWORD + + m_DTC7 + :1; + +4982 +IO_LWORD + + m_DTC6 + :1; + +4983 +IO_LWORD + + m_DTC5 + :1; + +4984 +IO_LWORD + + m_DTC4 + :1; + +4985 +IO_LWORD + + m_DTC3 + :1; + +4986 +IO_LWORD + + m_DTC2 + :1; + +4987 +IO_LWORD + + m_DTC1 + :1; + +4988 +IO_LWORD + + m_DTC0 + :1; + +4989 } + mb™ +; + +4991 + mIO_LWORD + :1; + +4992 + mIO_LWORD + :1; + +4993 + mIO_LWORD + :1; + +4994 +IO_LWORD + + m_IS + :5; + +4995 +IO_LWORD + + m_EIS + :4; + +4996 +IO_LWORD + + m_BLK + :4; + +4997 +IO_LWORD + + m_DTC + :16; + +4998 } + mb™c +; + +4999 } + tDMACA2STR +; + +5001 +IO_LWORD + + mlwÜd +; + +5003 +IO_LWORD + + m_TYPE1 + :1; + +5004 +IO_LWORD + + m_TYPE0 + :1; + +5005 +IO_LWORD + + m_MOD1 + :1; + +5006 +IO_LWORD + + m_MOD0 + :1; + +5007 +IO_LWORD + + m_WS1 + :1; + +5008 +IO_LWORD + + m_WS0 + :1; + +5009 +IO_LWORD + + m_SADM + :1; + +5010 +IO_LWORD + + m_DADM + :1; + +5011 +IO_LWORD + + m_DTCR + :1; + +5012 +IO_LWORD + + m_SADR + :1; + +5013 +IO_LWORD + + m_DADR + :1; + +5014 +IO_LWORD + + m_ERIE + :1; + +5015 +IO_LWORD + + m_EDIE + :1; + +5016 +IO_LWORD + + m_DSS2 + :1; + +5017 +IO_LWORD + + m_DSS1 + :1; + +5018 +IO_LWORD + + m_DSS0 + :1; + +5019 +IO_LWORD + + m_SASZ7 + :1; + +5020 +IO_LWORD + + m_SASZ6 + :1; + +5021 +IO_LWORD + + m_SASZ5 + :1; + +5022 +IO_LWORD + + m_SASZ4 + :1; + +5023 +IO_LWORD + + m_SASZ3 + :1; + +5024 +IO_LWORD + + m_SASZ2 + :1; + +5025 +IO_LWORD + + m_SASZ1 + :1; + +5026 +IO_LWORD + + m_SASZ0 + :1; + +5027 +IO_LWORD + + m_DASZ7 + :1; + +5028 +IO_LWORD + + m_DASZ6 + :1; + +5029 +IO_LWORD + + m_DASZ5 + :1; + +5030 +IO_LWORD + + m_DASZ4 + :1; + +5031 +IO_LWORD + + m_DASZ3 + :1; + +5032 +IO_LWORD + + m_DASZ2 + :1; + +5033 +IO_LWORD + + m_DASZ1 + :1; + +5034 +IO_LWORD + + m_DASZ0 + :1; + +5035 } + mb™ +; + +5037 +IO_LWORD + + m_TYPE + :2; + +5038 +IO_LWORD + + m_MOD + :2; + +5039 +IO_LWORD + + m_WS + :2; + +5040 + mIO_LWORD + :1; + +5041 + mIO_LWORD + :1; + +5042 + mIO_LWORD + :1; + +5043 + mIO_LWORD + :1; + +5044 + mIO_LWORD + :1; + +5045 + mIO_LWORD + :1; + +5046 + mIO_LWORD + :1; + +5047 +IO_LWORD + + m_DSS + :3; + +5048 +IO_LWORD + + m_SASZ + :8; + +5049 +IO_LWORD + + m_DASZ + :8; + +5050 } + mb™c +; + +5051 } + tDMACB2STR +; + +5053 +IO_LWORD + + mlwÜd +; + +5055 +IO_LWORD + + m_DENB + :1; + +5056 +IO_LWORD + + m_PAUS + :1; + +5057 +IO_LWORD + + m_STRG + :1; + +5058 +IO_LWORD + + m_IS4 + :1; + +5059 +IO_LWORD + + m_IS3 + :1; + +5060 +IO_LWORD + + m_IS2 + :1; + +5061 +IO_LWORD + + m_IS1 + :1; + +5062 +IO_LWORD + + m_IS0 + :1; + +5063 +IO_LWORD + + m_EIS3 + :1; + +5064 +IO_LWORD + + m_EIS2 + :1; + +5065 +IO_LWORD + + m_EIS1 + :1; + +5066 +IO_LWORD + + m_EIS0 + :1; + +5067 +IO_LWORD + + m_BLK3 + :1; + +5068 +IO_LWORD + + m_BLK2 + :1; + +5069 +IO_LWORD + + m_BLK1 + :1; + +5070 +IO_LWORD + + m_BLK0 + :1; + +5071 +IO_LWORD + + m_DTCF + :1; + +5072 +IO_LWORD + + m_DTCE + :1; + +5073 +IO_LWORD + + m_DTCD + :1; + +5074 +IO_LWORD + + m_DTCC + :1; + +5075 +IO_LWORD + + m_DTCB + :1; + +5076 +IO_LWORD + + m_DTCA + :1; + +5077 +IO_LWORD + + m_DTC9 + :1; + +5078 +IO_LWORD + + m_DTC8 + :1; + +5079 +IO_LWORD + + m_DTC7 + :1; + +5080 +IO_LWORD + + m_DTC6 + :1; + +5081 +IO_LWORD + + m_DTC5 + :1; + +5082 +IO_LWORD + + m_DTC4 + :1; + +5083 +IO_LWORD + + m_DTC3 + :1; + +5084 +IO_LWORD + + m_DTC2 + :1; + +5085 +IO_LWORD + + m_DTC1 + :1; + +5086 +IO_LWORD + + m_DTC0 + :1; + +5087 } + mb™ +; + +5089 + mIO_LWORD + :1; + +5090 + mIO_LWORD + :1; + +5091 + mIO_LWORD + :1; + +5092 +IO_LWORD + + m_IS + :5; + +5093 +IO_LWORD + + m_EIS + :4; + +5094 +IO_LWORD + + m_BLK + :4; + +5095 +IO_LWORD + + m_DTC + :16; + +5096 } + mb™c +; + +5097 } + tDMACA3STR +; + +5099 +IO_LWORD + + mlwÜd +; + +5101 +IO_LWORD + + m_TYPE1 + :1; + +5102 +IO_LWORD + + m_TYPE0 + :1; + +5103 +IO_LWORD + + m_MOD1 + :1; + +5104 +IO_LWORD + + m_MOD0 + :1; + +5105 +IO_LWORD + + m_WS1 + :1; + +5106 +IO_LWORD + + m_WS0 + :1; + +5107 +IO_LWORD + + m_SADM + :1; + +5108 +IO_LWORD + + m_DADM + :1; + +5109 +IO_LWORD + + m_DTCR + :1; + +5110 +IO_LWORD + + m_SADR + :1; + +5111 +IO_LWORD + + m_DADR + :1; + +5112 +IO_LWORD + + m_ERIE + :1; + +5113 +IO_LWORD + + m_EDIE + :1; + +5114 +IO_LWORD + + m_DSS2 + :1; + +5115 +IO_LWORD + + m_DSS1 + :1; + +5116 +IO_LWORD + + m_DSS0 + :1; + +5117 +IO_LWORD + + m_SASZ7 + :1; + +5118 +IO_LWORD + + m_SASZ6 + :1; + +5119 +IO_LWORD + + m_SASZ5 + :1; + +5120 +IO_LWORD + + m_SASZ4 + :1; + +5121 +IO_LWORD + + m_SASZ3 + :1; + +5122 +IO_LWORD + + m_SASZ2 + :1; + +5123 +IO_LWORD + + m_SASZ1 + :1; + +5124 +IO_LWORD + + m_SASZ0 + :1; + +5125 +IO_LWORD + + m_DASZ7 + :1; + +5126 +IO_LWORD + + m_DASZ6 + :1; + +5127 +IO_LWORD + + m_DASZ5 + :1; + +5128 +IO_LWORD + + m_DASZ4 + :1; + +5129 +IO_LWORD + + m_DASZ3 + :1; + +5130 +IO_LWORD + + m_DASZ2 + :1; + +5131 +IO_LWORD + + m_DASZ1 + :1; + +5132 +IO_LWORD + + m_DASZ0 + :1; + +5133 } + mb™ +; + +5135 +IO_LWORD + + m_TYPE + :2; + +5136 +IO_LWORD + + m_MOD + :2; + +5137 +IO_LWORD + + m_WS + :2; + +5138 + mIO_LWORD + :1; + +5139 + mIO_LWORD + :1; + +5140 + mIO_LWORD + :1; + +5141 + mIO_LWORD + :1; + +5142 + mIO_LWORD + :1; + +5143 + mIO_LWORD + :1; + +5144 + mIO_LWORD + :1; + +5145 +IO_LWORD + + m_DSS + :3; + +5146 +IO_LWORD + + m_SASZ + :8; + +5147 +IO_LWORD + + m_DASZ + :8; + +5148 } + mb™c +; + +5149 } + tDMACB3STR +; + +5151 +IO_LWORD + + mlwÜd +; + +5153 +IO_LWORD + + m_DENB + :1; + +5154 +IO_LWORD + + m_PAUS + :1; + +5155 +IO_LWORD + + m_STRG + :1; + +5156 +IO_LWORD + + m_IS4 + :1; + +5157 +IO_LWORD + + m_IS3 + :1; + +5158 +IO_LWORD + + m_IS2 + :1; + +5159 +IO_LWORD + + m_IS1 + :1; + +5160 +IO_LWORD + + m_IS0 + :1; + +5161 +IO_LWORD + + m_EIS3 + :1; + +5162 +IO_LWORD + + m_EIS2 + :1; + +5163 +IO_LWORD + + m_EIS1 + :1; + +5164 +IO_LWORD + + m_EIS0 + :1; + +5165 +IO_LWORD + + m_BLK3 + :1; + +5166 +IO_LWORD + + m_BLK2 + :1; + +5167 +IO_LWORD + + m_BLK1 + :1; + +5168 +IO_LWORD + + m_BLK0 + :1; + +5169 +IO_LWORD + + m_DTCF + :1; + +5170 +IO_LWORD + + m_DTCE + :1; + +5171 +IO_LWORD + + m_DTCD + :1; + +5172 +IO_LWORD + + m_DTCC + :1; + +5173 +IO_LWORD + + m_DTCB + :1; + +5174 +IO_LWORD + + m_DTCA + :1; + +5175 +IO_LWORD + + m_DTC9 + :1; + +5176 +IO_LWORD + + m_DTC8 + :1; + +5177 +IO_LWORD + + m_DTC7 + :1; + +5178 +IO_LWORD + + m_DTC6 + :1; + +5179 +IO_LWORD + + m_DTC5 + :1; + +5180 +IO_LWORD + + m_DTC4 + :1; + +5181 +IO_LWORD + + m_DTC3 + :1; + +5182 +IO_LWORD + + m_DTC2 + :1; + +5183 +IO_LWORD + + m_DTC1 + :1; + +5184 +IO_LWORD + + m_DTC0 + :1; + +5185 } + mb™ +; + +5187 + mIO_LWORD + :1; + +5188 + mIO_LWORD + :1; + +5189 + mIO_LWORD + :1; + +5190 +IO_LWORD + + m_IS + :5; + +5191 +IO_LWORD + + m_EIS + :4; + +5192 +IO_LWORD + + m_BLK + :4; + +5193 +IO_LWORD + + m_DTC + :16; + +5194 } + mb™c +; + +5195 } + tDMACA4STR +; + +5197 +IO_LWORD + + mlwÜd +; + +5199 +IO_LWORD + + m_TYPE1 + :1; + +5200 +IO_LWORD + + m_TYPE0 + :1; + +5201 +IO_LWORD + + m_MOD1 + :1; + +5202 +IO_LWORD + + m_MOD0 + :1; + +5203 +IO_LWORD + + m_WS1 + :1; + +5204 +IO_LWORD + + m_WS0 + :1; + +5205 +IO_LWORD + + m_SADM + :1; + +5206 +IO_LWORD + + m_DADM + :1; + +5207 +IO_LWORD + + m_DTCR + :1; + +5208 +IO_LWORD + + m_SADR + :1; + +5209 +IO_LWORD + + m_DADR + :1; + +5210 +IO_LWORD + + m_ERIE + :1; + +5211 +IO_LWORD + + m_EDIE + :1; + +5212 +IO_LWORD + + m_DSS2 + :1; + +5213 +IO_LWORD + + m_DSS1 + :1; + +5214 +IO_LWORD + + m_DSS0 + :1; + +5215 +IO_LWORD + + m_SASZ7 + :1; + +5216 +IO_LWORD + + m_SASZ6 + :1; + +5217 +IO_LWORD + + m_SASZ5 + :1; + +5218 +IO_LWORD + + m_SASZ4 + :1; + +5219 +IO_LWORD + + m_SASZ3 + :1; + +5220 +IO_LWORD + + m_SASZ2 + :1; + +5221 +IO_LWORD + + m_SASZ1 + :1; + +5222 +IO_LWORD + + m_SASZ0 + :1; + +5223 +IO_LWORD + + m_DASZ7 + :1; + +5224 +IO_LWORD + + m_DASZ6 + :1; + +5225 +IO_LWORD + + m_DASZ5 + :1; + +5226 +IO_LWORD + + m_DASZ4 + :1; + +5227 +IO_LWORD + + m_DASZ3 + :1; + +5228 +IO_LWORD + + m_DASZ2 + :1; + +5229 +IO_LWORD + + m_DASZ1 + :1; + +5230 +IO_LWORD + + m_DASZ0 + :1; + +5231 } + mb™ +; + +5233 +IO_LWORD + + m_TYPE + :2; + +5234 +IO_LWORD + + m_MOD + :2; + +5235 +IO_LWORD + + m_WS + :2; + +5236 + mIO_LWORD + :1; + +5237 + mIO_LWORD + :1; + +5238 + mIO_LWORD + :1; + +5239 + mIO_LWORD + :1; + +5240 + mIO_LWORD + :1; + +5241 + mIO_LWORD + :1; + +5242 + mIO_LWORD + :1; + +5243 +IO_LWORD + + m_DSS + :3; + +5244 +IO_LWORD + + m_SASZ + :8; + +5245 +IO_LWORD + + m_DASZ + :8; + +5246 } + mb™c +; + +5247 } + tDMACB4STR +; + +5249 +IO_BYTE + + mby‹ +; + +5251 +IO_BYTE + + m_DMAE + :1; + +5252 + mIO_BYTE + :1; + +5253 + mIO_BYTE + :1; + +5254 +IO_BYTE + + m_PM01 + :1; + +5255 +IO_BYTE + + m_DMAH3 + :1; + +5256 +IO_BYTE + + m_DMAH2 + :1; + +5257 +IO_BYTE + + m_DMAH1 + :1; + +5258 +IO_BYTE + + m_DMAH0 + :1; + +5259 } + mb™ +; + +5261 + mIO_BYTE + :1; + +5262 + mIO_BYTE + :1; + +5263 + mIO_BYTE + :1; + +5264 + mIO_BYTE + :1; + +5265 +IO_BYTE + + m_DMAH + :4; + +5266 } + mb™c +; + +5267 } + tDMACRSTR +; + +5269 +IO_BYTE + + mby‹ +; + +5271 +IO_BYTE + + m_ICP5 + :1; + +5272 +IO_BYTE + + m_ICP4 + :1; + +5273 +IO_BYTE + + m_ICE5 + :1; + +5274 +IO_BYTE + + m_ICE4 + :1; + +5275 +IO_BYTE + + m_EG51 + :1; + +5276 +IO_BYTE + + m_EG50 + :1; + +5277 +IO_BYTE + + m_EG41 + :1; + +5278 +IO_BYTE + + m_EG40 + :1; + +5279 } + mb™ +; + +5281 + mIO_BYTE + :1; + +5282 + mIO_BYTE + :1; + +5283 + mIO_BYTE + :1; + +5284 + mIO_BYTE + :1; + +5285 +IO_BYTE + + m_EG5 + :2; + +5286 +IO_BYTE + + m_EG4 + :2; + +5287 } + mb™c +; + +5288 } + tICS45STR +; + +5290 +IO_BYTE + + mby‹ +; + +5292 +IO_BYTE + + m_ICP7 + :1; + +5293 +IO_BYTE + + m_ICP6 + :1; + +5294 +IO_BYTE + + m_ICE7 + :1; + +5295 +IO_BYTE + + m_ICE6 + :1; + +5296 +IO_BYTE + + m_EG71 + :1; + +5297 +IO_BYTE + + m_EG70 + :1; + +5298 +IO_BYTE + + m_EG61 + :1; + +5299 +IO_BYTE + + m_EG60 + :1; + +5300 } + mb™ +; + +5302 + mIO_BYTE + :1; + +5303 + mIO_BYTE + :1; + +5304 + mIO_BYTE + :1; + +5305 + mIO_BYTE + :1; + +5306 +IO_BYTE + + m_EG7 + :2; + +5307 +IO_BYTE + + m_EG6 + :2; + +5308 } + mb™c +; + +5309 } + tICS67STR +; + +5311 +IO_WORD + + mwÜd +; + +5313 +IO_WORD + + m_CP15 + :1; + +5314 +IO_WORD + + m_CP14 + :1; + +5315 +IO_WORD + + m_CP13 + :1; + +5316 +IO_WORD + + m_CP12 + :1; + +5317 +IO_WORD + + m_CP11 + :1; + +5318 +IO_WORD + + m_CP10 + :1; + +5319 +IO_WORD + + m_CP9 + :1; + +5320 +IO_WORD + + m_CP8 + :1; + +5321 +IO_WORD + + m_CP7 + :1; + +5322 +IO_WORD + + m_CP6 + :1; + +5323 +IO_WORD + + m_CP5 + :1; + +5324 +IO_WORD + + m_CP4 + :1; + +5325 +IO_WORD + + m_CP3 + :1; + +5326 +IO_WORD + + m_CP2 + :1; + +5327 +IO_WORD + + m_CP1 + :1; + +5328 +IO_WORD + + m_CP0 + :1; + +5329 } + mb™ +; + +5330 } + tIPCP4STR +; + +5332 +IO_WORD + + mwÜd +; + +5334 +IO_WORD + + m_CP15 + :1; + +5335 +IO_WORD + + m_CP14 + :1; + +5336 +IO_WORD + + m_CP13 + :1; + +5337 +IO_WORD + + m_CP12 + :1; + +5338 +IO_WORD + + m_CP11 + :1; + +5339 +IO_WORD + + m_CP10 + :1; + +5340 +IO_WORD + + m_CP9 + :1; + +5341 +IO_WORD + + m_CP8 + :1; + +5342 +IO_WORD + + m_CP7 + :1; + +5343 +IO_WORD + + m_CP6 + :1; + +5344 +IO_WORD + + m_CP5 + :1; + +5345 +IO_WORD + + m_CP4 + :1; + +5346 +IO_WORD + + m_CP3 + :1; + +5347 +IO_WORD + + m_CP2 + :1; + +5348 +IO_WORD + + m_CP1 + :1; + +5349 +IO_WORD + + m_CP0 + :1; + +5350 } + mb™ +; + +5351 } + tIPCP5STR +; + +5353 +IO_WORD + + mwÜd +; + +5355 +IO_WORD + + m_CP15 + :1; + +5356 +IO_WORD + + m_CP14 + :1; + +5357 +IO_WORD + + m_CP13 + :1; + +5358 +IO_WORD + + m_CP12 + :1; + +5359 +IO_WORD + + m_CP11 + :1; + +5360 +IO_WORD + + m_CP10 + :1; + +5361 +IO_WORD + + m_CP9 + :1; + +5362 +IO_WORD + + m_CP8 + :1; + +5363 +IO_WORD + + m_CP7 + :1; + +5364 +IO_WORD + + m_CP6 + :1; + +5365 +IO_WORD + + m_CP5 + :1; + +5366 +IO_WORD + + m_CP4 + :1; + +5367 +IO_WORD + + m_CP3 + :1; + +5368 +IO_WORD + + m_CP2 + :1; + +5369 +IO_WORD + + m_CP1 + :1; + +5370 +IO_WORD + + m_CP0 + :1; + +5371 } + mb™ +; + +5372 } + tIPCP6STR +; + +5374 +IO_WORD + + mwÜd +; + +5376 +IO_WORD + + m_CP15 + :1; + +5377 +IO_WORD + + m_CP14 + :1; + +5378 +IO_WORD + + m_CP13 + :1; + +5379 +IO_WORD + + m_CP12 + :1; + +5380 +IO_WORD + + m_CP11 + :1; + +5381 +IO_WORD + + m_CP10 + :1; + +5382 +IO_WORD + + m_CP9 + :1; + +5383 +IO_WORD + + m_CP8 + :1; + +5384 +IO_WORD + + m_CP7 + :1; + +5385 +IO_WORD + + m_CP6 + :1; + +5386 +IO_WORD + + m_CP5 + :1; + +5387 +IO_WORD + + m_CP4 + :1; + +5388 +IO_WORD + + m_CP3 + :1; + +5389 +IO_WORD + + m_CP2 + :1; + +5390 +IO_WORD + + m_CP1 + :1; + +5391 +IO_WORD + + m_CP0 + :1; + +5392 } + mb™ +; + +5393 } + tIPCP7STR +; + +5395 +IO_WORD + + mwÜd +; + +5397 + mIO_WORD + :1; + +5398 + mIO_WORD + :1; + +5399 + mIO_WORD + :1; + +5400 +IO_WORD + + m_CMOD + :1; + +5401 + mIO_WORD + :1; + +5402 + mIO_WORD + :1; + +5403 +IO_WORD + + m_OTD5 + :1; + +5404 +IO_WORD + + m_OTD4 + :1; + +5405 +IO_WORD + + m_ICP5 + :1; + +5406 +IO_WORD + + m_ICP4 + :1; + +5407 +IO_WORD + + m_ICE5 + :1; + +5408 +IO_WORD + + m_ICE4 + :1; + +5409 + mIO_WORD + :1; + +5410 + mIO_WORD + :1; + +5411 +IO_WORD + + m_CST5 + :1; + +5412 +IO_WORD + + m_CST4 + :1; + +5413 } + mb™ +; + +5414 } + tOCS45STR +; + +5416 +IO_WORD + + mwÜd +; + +5418 + mIO_WORD + :1; + +5419 + mIO_WORD + :1; + +5420 + mIO_WORD + :1; + +5421 +IO_WORD + + m_CMOD + :1; + +5422 + mIO_WORD + :1; + +5423 + mIO_WORD + :1; + +5424 +IO_WORD + + m_OTD7 + :1; + +5425 +IO_WORD + + m_OTD6 + :1; + +5426 +IO_WORD + + m_ICP7 + :1; + +5427 +IO_WORD + + m_ICP6 + :1; + +5428 +IO_WORD + + m_ICE7 + :1; + +5429 +IO_WORD + + m_ICE6 + :1; + +5430 + mIO_WORD + :1; + +5431 + mIO_WORD + :1; + +5432 +IO_WORD + + m_CST7 + :1; + +5433 +IO_WORD + + m_CST6 + :1; + +5434 } + mb™ +; + +5435 } + tOCS67STR +; + +5437 +IO_WORD + + mwÜd +; + +5439 +IO_WORD + + m_C15 + :1; + +5440 +IO_WORD + + m_C14 + :1; + +5441 +IO_WORD + + m_C13 + :1; + +5442 +IO_WORD + + m_C12 + :1; + +5443 +IO_WORD + + m_C11 + :1; + +5444 +IO_WORD + + m_C10 + :1; + +5445 +IO_WORD + + m_C9 + :1; + +5446 +IO_WORD + + m_C8 + :1; + +5447 +IO_WORD + + m_C7 + :1; + +5448 +IO_WORD + + m_C6 + :1; + +5449 +IO_WORD + + m_C5 + :1; + +5450 +IO_WORD + + m_C4 + :1; + +5451 +IO_WORD + + m_C3 + :1; + +5452 +IO_WORD + + m_C2 + :1; + +5453 +IO_WORD + + m_C1 + :1; + +5454 +IO_WORD + + m_C0 + :1; + +5455 } + mb™ +; + +5456 } + tOCCP4STR +; + +5458 +IO_WORD + + mwÜd +; + +5460 +IO_WORD + + m_C15 + :1; + +5461 +IO_WORD + + m_C14 + :1; + +5462 +IO_WORD + + m_C13 + :1; + +5463 +IO_WORD + + m_C12 + :1; + +5464 +IO_WORD + + m_C11 + :1; + +5465 +IO_WORD + + m_C10 + :1; + +5466 +IO_WORD + + m_C9 + :1; + +5467 +IO_WORD + + m_C8 + :1; + +5468 +IO_WORD + + m_C7 + :1; + +5469 +IO_WORD + + m_C6 + :1; + +5470 +IO_WORD + + m_C5 + :1; + +5471 +IO_WORD + + m_C4 + :1; + +5472 +IO_WORD + + m_C3 + :1; + +5473 +IO_WORD + + m_C2 + :1; + +5474 +IO_WORD + + m_C1 + :1; + +5475 +IO_WORD + + m_C0 + :1; + +5476 } + mb™ +; + +5477 } + tOCCP5STR +; + +5479 +IO_WORD + + mwÜd +; + +5481 +IO_WORD + + m_C15 + :1; + +5482 +IO_WORD + + m_C14 + :1; + +5483 +IO_WORD + + m_C13 + :1; + +5484 +IO_WORD + + m_C12 + :1; + +5485 +IO_WORD + + m_C11 + :1; + +5486 +IO_WORD + + m_C10 + :1; + +5487 +IO_WORD + + m_C9 + :1; + +5488 +IO_WORD + + m_C8 + :1; + +5489 +IO_WORD + + m_C7 + :1; + +5490 +IO_WORD + + m_C6 + :1; + +5491 +IO_WORD + + m_C5 + :1; + +5492 +IO_WORD + + m_C4 + :1; + +5493 +IO_WORD + + m_C3 + :1; + +5494 +IO_WORD + + m_C2 + :1; + +5495 +IO_WORD + + m_C1 + :1; + +5496 +IO_WORD + + m_C0 + :1; + +5497 } + mb™ +; + +5498 } + tOCCP6STR +; + +5500 +IO_WORD + + mwÜd +; + +5502 +IO_WORD + + m_C15 + :1; + +5503 +IO_WORD + + m_C14 + :1; + +5504 +IO_WORD + + m_C13 + :1; + +5505 +IO_WORD + + m_C12 + :1; + +5506 +IO_WORD + + m_C11 + :1; + +5507 +IO_WORD + + m_C10 + :1; + +5508 +IO_WORD + + m_C9 + :1; + +5509 +IO_WORD + + m_C8 + :1; + +5510 +IO_WORD + + m_C7 + :1; + +5511 +IO_WORD + + m_C6 + :1; + +5512 +IO_WORD + + m_C5 + :1; + +5513 +IO_WORD + + m_C4 + :1; + +5514 +IO_WORD + + m_C3 + :1; + +5515 +IO_WORD + + m_C2 + :1; + +5516 +IO_WORD + + m_C1 + :1; + +5517 +IO_WORD + + m_C0 + :1; + +5518 } + mb™ +; + +5519 } + tOCCP7STR +; + +5521 +IO_WORD + + mwÜd +; + +5523 +IO_WORD + + m_T15 + :1; + +5524 +IO_WORD + + m_T14 + :1; + +5525 +IO_WORD + + m_T13 + :1; + +5526 +IO_WORD + + m_T12 + :1; + +5527 +IO_WORD + + m_T11 + :1; + +5528 +IO_WORD + + m_T10 + :1; + +5529 +IO_WORD + + m_T9 + :1; + +5530 +IO_WORD + + m_T8 + :1; + +5531 +IO_WORD + + m_T7 + :1; + +5532 +IO_WORD + + m_T6 + :1; + +5533 +IO_WORD + + m_T5 + :1; + +5534 +IO_WORD + + m_T4 + :1; + +5535 +IO_WORD + + m_T3 + :1; + +5536 +IO_WORD + + m_T2 + :1; + +5537 +IO_WORD + + m_T1 + :1; + +5538 +IO_WORD + + m_T0 + :1; + +5539 } + mb™ +; + +5540 } + tTCDT4STR +; + +5542 +IO_BYTE + + mby‹ +; + +5544 +IO_BYTE + + m_ECLK + :1; + +5545 +IO_BYTE + + m_IVF + :1; + +5546 +IO_BYTE + + m_IVFE + :1; + +5547 +IO_BYTE + + m_STOP + :1; + +5548 +IO_BYTE + + m_MODE + :1; + +5549 +IO_BYTE + + m_CLR + :1; + +5550 +IO_BYTE + + m_CLK1 + :1; + +5551 +IO_BYTE + + m_CLK0 + :1; + +5552 } + mb™ +; + +5554 + mIO_BYTE + :1; + +5555 + mIO_BYTE + :1; + +5556 + mIO_BYTE + :1; + +5557 + mIO_BYTE + :1; + +5558 + mIO_BYTE + :1; + +5559 + mIO_BYTE + :1; + +5560 +IO_BYTE + + m_CLK + :2; + +5561 } + mb™c +; + +5562 } + tTCCS4STR +; + +5564 +IO_WORD + + mwÜd +; + +5566 +IO_WORD + + m_T15 + :1; + +5567 +IO_WORD + + m_T14 + :1; + +5568 +IO_WORD + + m_T13 + :1; + +5569 +IO_WORD + + m_T12 + :1; + +5570 +IO_WORD + + m_T11 + :1; + +5571 +IO_WORD + + m_T10 + :1; + +5572 +IO_WORD + + m_T9 + :1; + +5573 +IO_WORD + + m_T8 + :1; + +5574 +IO_WORD + + m_T7 + :1; + +5575 +IO_WORD + + m_T6 + :1; + +5576 +IO_WORD + + m_T5 + :1; + +5577 +IO_WORD + + m_T4 + :1; + +5578 +IO_WORD + + m_T3 + :1; + +5579 +IO_WORD + + m_T2 + :1; + +5580 +IO_WORD + + m_T1 + :1; + +5581 +IO_WORD + + m_T0 + :1; + +5582 } + mb™ +; + +5583 } + tTCDT5STR +; + +5585 +IO_BYTE + + mby‹ +; + +5587 +IO_BYTE + + m_ECLK + :1; + +5588 +IO_BYTE + + m_IVF + :1; + +5589 +IO_BYTE + + m_IVFE + :1; + +5590 +IO_BYTE + + m_STOP + :1; + +5591 +IO_BYTE + + m_MODE + :1; + +5592 +IO_BYTE + + m_CLR + :1; + +5593 +IO_BYTE + + m_CLK1 + :1; + +5594 +IO_BYTE + + m_CLK0 + :1; + +5595 } + mb™ +; + +5597 + mIO_BYTE + :1; + +5598 + mIO_BYTE + :1; + +5599 + mIO_BYTE + :1; + +5600 + mIO_BYTE + :1; + +5601 + mIO_BYTE + :1; + +5602 + mIO_BYTE + :1; + +5603 +IO_BYTE + + m_CLK + :2; + +5604 } + mb™c +; + +5605 } + tTCCS5STR +; + +5607 +IO_WORD + + mwÜd +; + +5609 +IO_WORD + + m_T15 + :1; + +5610 +IO_WORD + + m_T14 + :1; + +5611 +IO_WORD + + m_T13 + :1; + +5612 +IO_WORD + + m_T12 + :1; + +5613 +IO_WORD + + m_T11 + :1; + +5614 +IO_WORD + + m_T10 + :1; + +5615 +IO_WORD + + m_T9 + :1; + +5616 +IO_WORD + + m_T8 + :1; + +5617 +IO_WORD + + m_T7 + :1; + +5618 +IO_WORD + + m_T6 + :1; + +5619 +IO_WORD + + m_T5 + :1; + +5620 +IO_WORD + + m_T4 + :1; + +5621 +IO_WORD + + m_T3 + :1; + +5622 +IO_WORD + + m_T2 + :1; + +5623 +IO_WORD + + m_T1 + :1; + +5624 +IO_WORD + + m_T0 + :1; + +5625 } + mb™ +; + +5626 } + tTCDT6STR +; + +5628 +IO_BYTE + + mby‹ +; + +5630 +IO_BYTE + + m_ECLK + :1; + +5631 +IO_BYTE + + m_IVF + :1; + +5632 +IO_BYTE + + m_IVFE + :1; + +5633 +IO_BYTE + + m_STOP + :1; + +5634 +IO_BYTE + + m_MODE + :1; + +5635 +IO_BYTE + + m_CLR + :1; + +5636 +IO_BYTE + + m_CLK1 + :1; + +5637 +IO_BYTE + + m_CLK0 + :1; + +5638 } + mb™ +; + +5640 + mIO_BYTE + :1; + +5641 + mIO_BYTE + :1; + +5642 + mIO_BYTE + :1; + +5643 + mIO_BYTE + :1; + +5644 + mIO_BYTE + :1; + +5645 + mIO_BYTE + :1; + +5646 +IO_BYTE + + m_CLK + :2; + +5647 } + mb™c +; + +5648 } + tTCCS6STR +; + +5650 +IO_WORD + + mwÜd +; + +5652 +IO_WORD + + m_T15 + :1; + +5653 +IO_WORD + + m_T14 + :1; + +5654 +IO_WORD + + m_T13 + :1; + +5655 +IO_WORD + + m_T12 + :1; + +5656 +IO_WORD + + m_T11 + :1; + +5657 +IO_WORD + + m_T10 + :1; + +5658 +IO_WORD + + m_T9 + :1; + +5659 +IO_WORD + + m_T8 + :1; + +5660 +IO_WORD + + m_T7 + :1; + +5661 +IO_WORD + + m_T6 + :1; + +5662 +IO_WORD + + m_T5 + :1; + +5663 +IO_WORD + + m_T4 + :1; + +5664 +IO_WORD + + m_T3 + :1; + +5665 +IO_WORD + + m_T2 + :1; + +5666 +IO_WORD + + m_T1 + :1; + +5667 +IO_WORD + + m_T0 + :1; + +5668 } + mb™ +; + +5669 } + tTCDT7STR +; + +5671 +IO_BYTE + + mby‹ +; + +5673 +IO_BYTE + + m_ECLK + :1; + +5674 +IO_BYTE + + m_IVF + :1; + +5675 +IO_BYTE + + m_IVFE + :1; + +5676 +IO_BYTE + + m_STOP + :1; + +5677 +IO_BYTE + + m_MODE + :1; + +5678 +IO_BYTE + + m_CLR + :1; + +5679 +IO_BYTE + + m_CLK1 + :1; + +5680 +IO_BYTE + + m_CLK0 + :1; + +5681 } + mb™ +; + +5683 + mIO_BYTE + :1; + +5684 + mIO_BYTE + :1; + +5685 + mIO_BYTE + :1; + +5686 + mIO_BYTE + :1; + +5687 + mIO_BYTE + :1; + +5688 + mIO_BYTE + :1; + +5689 +IO_BYTE + + m_CLK + :2; + +5690 } + mb™c +; + +5691 } + tTCCS7STR +; + +5693 +IO_WORD + + mwÜd +; + +5695 +IO_WORD + + m_D15 + :1; + +5696 +IO_WORD + + m_D14 + :1; + +5697 +IO_WORD + + m_D13 + :1; + +5698 +IO_WORD + + m_D12 + :1; + +5699 +IO_WORD + + m_D11 + :1; + +5700 +IO_WORD + + m_D10 + :1; + +5701 +IO_WORD + + m_D9 + :1; + +5702 +IO_WORD + + m_D8 + :1; + +5703 +IO_WORD + + m_D7 + :1; + +5704 +IO_WORD + + m_D6 + :1; + +5705 +IO_WORD + + m_D5 + :1; + +5706 +IO_WORD + + m_D4 + :1; + +5707 +IO_WORD + + m_D3 + :1; + +5708 +IO_WORD + + m_D2 + :1; + +5709 +IO_WORD + + m_D1 + :1; + +5710 +IO_WORD + + m_D0 + :1; + +5711 } + mb™ +; + +5712 } + tROMSSTR +; + +5714 +IO_BYTE + + mby‹ +; + +5716 + mIO_BYTE + :1; + +5717 + mIO_BYTE + :1; + +5718 + mIO_BYTE + :1; + +5719 +IO_BYTE + + m_ICR4 + :1; + +5720 +IO_BYTE + + m_ICR3 + :1; + +5721 +IO_BYTE + + m_ICR2 + :1; + +5722 +IO_BYTE + + m_ICR1 + :1; + +5723 +IO_BYTE + + m_ICR0 + :1; + +5724 } + mb™ +; + +5725 } + tICR00STR +; + +5727 +IO_BYTE + + mby‹ +; + +5729 + mIO_BYTE + :1; + +5730 + mIO_BYTE + :1; + +5731 + mIO_BYTE + :1; + +5732 +IO_BYTE + + m_ICR4 + :1; + +5733 +IO_BYTE + + m_ICR3 + :1; + +5734 +IO_BYTE + + m_ICR2 + :1; + +5735 +IO_BYTE + + m_ICR1 + :1; + +5736 +IO_BYTE + + m_ICR0 + :1; + +5737 } + mb™ +; + +5738 } + tICR01STR +; + +5740 +IO_BYTE + + mby‹ +; + +5742 + mIO_BYTE + :1; + +5743 + mIO_BYTE + :1; + +5744 + mIO_BYTE + :1; + +5745 +IO_BYTE + + m_ICR4 + :1; + +5746 +IO_BYTE + + m_ICR3 + :1; + +5747 +IO_BYTE + + m_ICR2 + :1; + +5748 +IO_BYTE + + m_ICR1 + :1; + +5749 +IO_BYTE + + m_ICR0 + :1; + +5750 } + mb™ +; + +5751 } + tICR02STR +; + +5753 +IO_BYTE + + mby‹ +; + +5755 + mIO_BYTE + :1; + +5756 + mIO_BYTE + :1; + +5757 + mIO_BYTE + :1; + +5758 +IO_BYTE + + m_ICR4 + :1; + +5759 +IO_BYTE + + m_ICR3 + :1; + +5760 +IO_BYTE + + m_ICR2 + :1; + +5761 +IO_BYTE + + m_ICR1 + :1; + +5762 +IO_BYTE + + m_ICR0 + :1; + +5763 } + mb™ +; + +5764 } + tICR03STR +; + +5766 +IO_BYTE + + mby‹ +; + +5768 + mIO_BYTE + :1; + +5769 + mIO_BYTE + :1; + +5770 + mIO_BYTE + :1; + +5771 +IO_BYTE + + m_ICR4 + :1; + +5772 +IO_BYTE + + m_ICR3 + :1; + +5773 +IO_BYTE + + m_ICR2 + :1; + +5774 +IO_BYTE + + m_ICR1 + :1; + +5775 +IO_BYTE + + m_ICR0 + :1; + +5776 } + mb™ +; + +5777 } + tICR04STR +; + +5779 +IO_BYTE + + mby‹ +; + +5781 + mIO_BYTE + :1; + +5782 + mIO_BYTE + :1; + +5783 + mIO_BYTE + :1; + +5784 +IO_BYTE + + m_ICR4 + :1; + +5785 +IO_BYTE + + m_ICR3 + :1; + +5786 +IO_BYTE + + m_ICR2 + :1; + +5787 +IO_BYTE + + m_ICR1 + :1; + +5788 +IO_BYTE + + m_ICR0 + :1; + +5789 } + mb™ +; + +5790 } + tICR05STR +; + +5792 +IO_BYTE + + mby‹ +; + +5794 + mIO_BYTE + :1; + +5795 + mIO_BYTE + :1; + +5796 + mIO_BYTE + :1; + +5797 +IO_BYTE + + m_ICR4 + :1; + +5798 +IO_BYTE + + m_ICR3 + :1; + +5799 +IO_BYTE + + m_ICR2 + :1; + +5800 +IO_BYTE + + m_ICR1 + :1; + +5801 +IO_BYTE + + m_ICR0 + :1; + +5802 } + mb™ +; + +5803 } + tICR06STR +; + +5805 +IO_BYTE + + mby‹ +; + +5807 + mIO_BYTE + :1; + +5808 + mIO_BYTE + :1; + +5809 + mIO_BYTE + :1; + +5810 +IO_BYTE + + m_ICR4 + :1; + +5811 +IO_BYTE + + m_ICR3 + :1; + +5812 +IO_BYTE + + m_ICR2 + :1; + +5813 +IO_BYTE + + m_ICR1 + :1; + +5814 +IO_BYTE + + m_ICR0 + :1; + +5815 } + mb™ +; + +5816 } + tICR07STR +; + +5818 +IO_BYTE + + mby‹ +; + +5820 + mIO_BYTE + :1; + +5821 + mIO_BYTE + :1; + +5822 + mIO_BYTE + :1; + +5823 +IO_BYTE + + m_ICR4 + :1; + +5824 +IO_BYTE + + m_ICR3 + :1; + +5825 +IO_BYTE + + m_ICR2 + :1; + +5826 +IO_BYTE + + m_ICR1 + :1; + +5827 +IO_BYTE + + m_ICR0 + :1; + +5828 } + mb™ +; + +5829 } + tICR08STR +; + +5831 +IO_BYTE + + mby‹ +; + +5833 + mIO_BYTE + :1; + +5834 + mIO_BYTE + :1; + +5835 + mIO_BYTE + :1; + +5836 +IO_BYTE + + m_ICR4 + :1; + +5837 +IO_BYTE + + m_ICR3 + :1; + +5838 +IO_BYTE + + m_ICR2 + :1; + +5839 +IO_BYTE + + m_ICR1 + :1; + +5840 +IO_BYTE + + m_ICR0 + :1; + +5841 } + mb™ +; + +5842 } + tICR09STR +; + +5844 +IO_BYTE + + mby‹ +; + +5846 + mIO_BYTE + :1; + +5847 + mIO_BYTE + :1; + +5848 + mIO_BYTE + :1; + +5849 +IO_BYTE + + m_ICR4 + :1; + +5850 +IO_BYTE + + m_ICR3 + :1; + +5851 +IO_BYTE + + m_ICR2 + :1; + +5852 +IO_BYTE + + m_ICR1 + :1; + +5853 +IO_BYTE + + m_ICR0 + :1; + +5854 } + mb™ +; + +5855 } + tICR10STR +; + +5857 +IO_BYTE + + mby‹ +; + +5859 + mIO_BYTE + :1; + +5860 + mIO_BYTE + :1; + +5861 + mIO_BYTE + :1; + +5862 +IO_BYTE + + m_ICR4 + :1; + +5863 +IO_BYTE + + m_ICR3 + :1; + +5864 +IO_BYTE + + m_ICR2 + :1; + +5865 +IO_BYTE + + m_ICR1 + :1; + +5866 +IO_BYTE + + m_ICR0 + :1; + +5867 } + mb™ +; + +5868 } + tICR11STR +; + +5870 +IO_BYTE + + mby‹ +; + +5872 + mIO_BYTE + :1; + +5873 + mIO_BYTE + :1; + +5874 + mIO_BYTE + :1; + +5875 +IO_BYTE + + m_ICR4 + :1; + +5876 +IO_BYTE + + m_ICR3 + :1; + +5877 +IO_BYTE + + m_ICR2 + :1; + +5878 +IO_BYTE + + m_ICR1 + :1; + +5879 +IO_BYTE + + m_ICR0 + :1; + +5880 } + mb™ +; + +5881 } + tICR12STR +; + +5883 +IO_BYTE + + mby‹ +; + +5885 + mIO_BYTE + :1; + +5886 + mIO_BYTE + :1; + +5887 + mIO_BYTE + :1; + +5888 +IO_BYTE + + m_ICR4 + :1; + +5889 +IO_BYTE + + m_ICR3 + :1; + +5890 +IO_BYTE + + m_ICR2 + :1; + +5891 +IO_BYTE + + m_ICR1 + :1; + +5892 +IO_BYTE + + m_ICR0 + :1; + +5893 } + mb™ +; + +5894 } + tICR13STR +; + +5896 +IO_BYTE + + mby‹ +; + +5898 + mIO_BYTE + :1; + +5899 + mIO_BYTE + :1; + +5900 + mIO_BYTE + :1; + +5901 +IO_BYTE + + m_ICR4 + :1; + +5902 +IO_BYTE + + m_ICR3 + :1; + +5903 +IO_BYTE + + m_ICR2 + :1; + +5904 +IO_BYTE + + m_ICR1 + :1; + +5905 +IO_BYTE + + m_ICR0 + :1; + +5906 } + mb™ +; + +5907 } + tICR14STR +; + +5909 +IO_BYTE + + mby‹ +; + +5911 + mIO_BYTE + :1; + +5912 + mIO_BYTE + :1; + +5913 + mIO_BYTE + :1; + +5914 +IO_BYTE + + m_ICR4 + :1; + +5915 +IO_BYTE + + m_ICR3 + :1; + +5916 +IO_BYTE + + m_ICR2 + :1; + +5917 +IO_BYTE + + m_ICR1 + :1; + +5918 +IO_BYTE + + m_ICR0 + :1; + +5919 } + mb™ +; + +5920 } + tICR15STR +; + +5922 +IO_BYTE + + mby‹ +; + +5924 + mIO_BYTE + :1; + +5925 + mIO_BYTE + :1; + +5926 + mIO_BYTE + :1; + +5927 +IO_BYTE + + m_ICR4 + :1; + +5928 +IO_BYTE + + m_ICR3 + :1; + +5929 +IO_BYTE + + m_ICR2 + :1; + +5930 +IO_BYTE + + m_ICR1 + :1; + +5931 +IO_BYTE + + m_ICR0 + :1; + +5932 } + mb™ +; + +5933 } + tICR16STR +; + +5935 +IO_BYTE + + mby‹ +; + +5937 + mIO_BYTE + :1; + +5938 + mIO_BYTE + :1; + +5939 + mIO_BYTE + :1; + +5940 +IO_BYTE + + m_ICR4 + :1; + +5941 +IO_BYTE + + m_ICR3 + :1; + +5942 +IO_BYTE + + m_ICR2 + :1; + +5943 +IO_BYTE + + m_ICR1 + :1; + +5944 +IO_BYTE + + m_ICR0 + :1; + +5945 } + mb™ +; + +5946 } + tICR17STR +; + +5948 +IO_BYTE + + mby‹ +; + +5950 + mIO_BYTE + :1; + +5951 + mIO_BYTE + :1; + +5952 + mIO_BYTE + :1; + +5953 +IO_BYTE + + m_ICR4 + :1; + +5954 +IO_BYTE + + m_ICR3 + :1; + +5955 +IO_BYTE + + m_ICR2 + :1; + +5956 +IO_BYTE + + m_ICR1 + :1; + +5957 +IO_BYTE + + m_ICR0 + :1; + +5958 } + mb™ +; + +5959 } + tICR18STR +; + +5961 +IO_BYTE + + mby‹ +; + +5963 + mIO_BYTE + :1; + +5964 + mIO_BYTE + :1; + +5965 + mIO_BYTE + :1; + +5966 +IO_BYTE + + m_ICR4 + :1; + +5967 +IO_BYTE + + m_ICR3 + :1; + +5968 +IO_BYTE + + m_ICR2 + :1; + +5969 +IO_BYTE + + m_ICR1 + :1; + +5970 +IO_BYTE + + m_ICR0 + :1; + +5971 } + mb™ +; + +5972 } + tICR19STR +; + +5974 +IO_BYTE + + mby‹ +; + +5976 + mIO_BYTE + :1; + +5977 + mIO_BYTE + :1; + +5978 + mIO_BYTE + :1; + +5979 +IO_BYTE + + m_ICR4 + :1; + +5980 +IO_BYTE + + m_ICR3 + :1; + +5981 +IO_BYTE + + m_ICR2 + :1; + +5982 +IO_BYTE + + m_ICR1 + :1; + +5983 +IO_BYTE + + m_ICR0 + :1; + +5984 } + mb™ +; + +5985 } + tICR20STR +; + +5987 +IO_BYTE + + mby‹ +; + +5989 + mIO_BYTE + :1; + +5990 + mIO_BYTE + :1; + +5991 + mIO_BYTE + :1; + +5992 +IO_BYTE + + m_ICR4 + :1; + +5993 +IO_BYTE + + m_ICR3 + :1; + +5994 +IO_BYTE + + m_ICR2 + :1; + +5995 +IO_BYTE + + m_ICR1 + :1; + +5996 +IO_BYTE + + m_ICR0 + :1; + +5997 } + mb™ +; + +5998 } + tICR21STR +; + +6000 +IO_BYTE + + mby‹ +; + +6002 + mIO_BYTE + :1; + +6003 + mIO_BYTE + :1; + +6004 + mIO_BYTE + :1; + +6005 +IO_BYTE + + m_ICR4 + :1; + +6006 +IO_BYTE + + m_ICR3 + :1; + +6007 +IO_BYTE + + m_ICR2 + :1; + +6008 +IO_BYTE + + m_ICR1 + :1; + +6009 +IO_BYTE + + m_ICR0 + :1; + +6010 } + mb™ +; + +6011 } + tICR22STR +; + +6013 +IO_BYTE + + mby‹ +; + +6015 + mIO_BYTE + :1; + +6016 + mIO_BYTE + :1; + +6017 + mIO_BYTE + :1; + +6018 +IO_BYTE + + m_ICR4 + :1; + +6019 +IO_BYTE + + m_ICR3 + :1; + +6020 +IO_BYTE + + m_ICR2 + :1; + +6021 +IO_BYTE + + m_ICR1 + :1; + +6022 +IO_BYTE + + m_ICR0 + :1; + +6023 } + mb™ +; + +6024 } + tICR23STR +; + +6026 +IO_BYTE + + mby‹ +; + +6028 + mIO_BYTE + :1; + +6029 + mIO_BYTE + :1; + +6030 + mIO_BYTE + :1; + +6031 +IO_BYTE + + m_ICR4 + :1; + +6032 +IO_BYTE + + m_ICR3 + :1; + +6033 +IO_BYTE + + m_ICR2 + :1; + +6034 +IO_BYTE + + m_ICR1 + :1; + +6035 +IO_BYTE + + m_ICR0 + :1; + +6036 } + mb™ +; + +6037 } + tICR24STR +; + +6039 +IO_BYTE + + mby‹ +; + +6041 + mIO_BYTE + :1; + +6042 + mIO_BYTE + :1; + +6043 + mIO_BYTE + :1; + +6044 +IO_BYTE + + m_ICR4 + :1; + +6045 +IO_BYTE + + m_ICR3 + :1; + +6046 +IO_BYTE + + m_ICR2 + :1; + +6047 +IO_BYTE + + m_ICR1 + :1; + +6048 +IO_BYTE + + m_ICR0 + :1; + +6049 } + mb™ +; + +6050 } + tICR25STR +; + +6052 +IO_BYTE + + mby‹ +; + +6054 + mIO_BYTE + :1; + +6055 + mIO_BYTE + :1; + +6056 + mIO_BYTE + :1; + +6057 +IO_BYTE + + m_ICR4 + :1; + +6058 +IO_BYTE + + m_ICR3 + :1; + +6059 +IO_BYTE + + m_ICR2 + :1; + +6060 +IO_BYTE + + m_ICR1 + :1; + +6061 +IO_BYTE + + m_ICR0 + :1; + +6062 } + mb™ +; + +6063 } + tICR26STR +; + +6065 +IO_BYTE + + mby‹ +; + +6067 + mIO_BYTE + :1; + +6068 + mIO_BYTE + :1; + +6069 + mIO_BYTE + :1; + +6070 +IO_BYTE + + m_ICR4 + :1; + +6071 +IO_BYTE + + m_ICR3 + :1; + +6072 +IO_BYTE + + m_ICR2 + :1; + +6073 +IO_BYTE + + m_ICR1 + :1; + +6074 +IO_BYTE + + m_ICR0 + :1; + +6075 } + mb™ +; + +6076 } + tICR27STR +; + +6078 +IO_BYTE + + mby‹ +; + +6080 + mIO_BYTE + :1; + +6081 + mIO_BYTE + :1; + +6082 + mIO_BYTE + :1; + +6083 +IO_BYTE + + m_ICR4 + :1; + +6084 +IO_BYTE + + m_ICR3 + :1; + +6085 +IO_BYTE + + m_ICR2 + :1; + +6086 +IO_BYTE + + m_ICR1 + :1; + +6087 +IO_BYTE + + m_ICR0 + :1; + +6088 } + mb™ +; + +6089 } + tICR28STR +; + +6091 +IO_BYTE + + mby‹ +; + +6093 + mIO_BYTE + :1; + +6094 + mIO_BYTE + :1; + +6095 + mIO_BYTE + :1; + +6096 +IO_BYTE + + m_ICR4 + :1; + +6097 +IO_BYTE + + m_ICR3 + :1; + +6098 +IO_BYTE + + m_ICR2 + :1; + +6099 +IO_BYTE + + m_ICR1 + :1; + +6100 +IO_BYTE + + m_ICR0 + :1; + +6101 } + mb™ +; + +6102 } + tICR29STR +; + +6104 +IO_BYTE + + mby‹ +; + +6106 + mIO_BYTE + :1; + +6107 + mIO_BYTE + :1; + +6108 + mIO_BYTE + :1; + +6109 +IO_BYTE + + m_ICR4 + :1; + +6110 +IO_BYTE + + m_ICR3 + :1; + +6111 +IO_BYTE + + m_ICR2 + :1; + +6112 +IO_BYTE + + m_ICR1 + :1; + +6113 +IO_BYTE + + m_ICR0 + :1; + +6114 } + mb™ +; + +6115 } + tICR30STR +; + +6117 +IO_BYTE + + mby‹ +; + +6119 + mIO_BYTE + :1; + +6120 + mIO_BYTE + :1; + +6121 + mIO_BYTE + :1; + +6122 +IO_BYTE + + m_ICR4 + :1; + +6123 +IO_BYTE + + m_ICR3 + :1; + +6124 +IO_BYTE + + m_ICR2 + :1; + +6125 +IO_BYTE + + m_ICR1 + :1; + +6126 +IO_BYTE + + m_ICR0 + :1; + +6127 } + mb™ +; + +6128 } + tICR31STR +; + +6130 +IO_BYTE + + mby‹ +; + +6132 + mIO_BYTE + :1; + +6133 + mIO_BYTE + :1; + +6134 + mIO_BYTE + :1; + +6135 +IO_BYTE + + m_ICR4 + :1; + +6136 +IO_BYTE + + m_ICR3 + :1; + +6137 +IO_BYTE + + m_ICR2 + :1; + +6138 +IO_BYTE + + m_ICR1 + :1; + +6139 +IO_BYTE + + m_ICR0 + :1; + +6140 } + mb™ +; + +6141 } + tICR32STR +; + +6143 +IO_BYTE + + mby‹ +; + +6145 + mIO_BYTE + :1; + +6146 + mIO_BYTE + :1; + +6147 + mIO_BYTE + :1; + +6148 +IO_BYTE + + m_ICR4 + :1; + +6149 +IO_BYTE + + m_ICR3 + :1; + +6150 +IO_BYTE + + m_ICR2 + :1; + +6151 +IO_BYTE + + m_ICR1 + :1; + +6152 +IO_BYTE + + m_ICR0 + :1; + +6153 } + mb™ +; + +6154 } + tICR33STR +; + +6156 +IO_BYTE + + mby‹ +; + +6158 + mIO_BYTE + :1; + +6159 + mIO_BYTE + :1; + +6160 + mIO_BYTE + :1; + +6161 +IO_BYTE + + m_ICR4 + :1; + +6162 +IO_BYTE + + m_ICR3 + :1; + +6163 +IO_BYTE + + m_ICR2 + :1; + +6164 +IO_BYTE + + m_ICR1 + :1; + +6165 +IO_BYTE + + m_ICR0 + :1; + +6166 } + mb™ +; + +6167 } + tICR34STR +; + +6169 +IO_BYTE + + mby‹ +; + +6171 + mIO_BYTE + :1; + +6172 + mIO_BYTE + :1; + +6173 + mIO_BYTE + :1; + +6174 +IO_BYTE + + m_ICR4 + :1; + +6175 +IO_BYTE + + m_ICR3 + :1; + +6176 +IO_BYTE + + m_ICR2 + :1; + +6177 +IO_BYTE + + m_ICR1 + :1; + +6178 +IO_BYTE + + m_ICR0 + :1; + +6179 } + mb™ +; + +6180 } + tICR35STR +; + +6182 +IO_BYTE + + mby‹ +; + +6184 + mIO_BYTE + :1; + +6185 + mIO_BYTE + :1; + +6186 + mIO_BYTE + :1; + +6187 +IO_BYTE + + m_ICR4 + :1; + +6188 +IO_BYTE + + m_ICR3 + :1; + +6189 +IO_BYTE + + m_ICR2 + :1; + +6190 +IO_BYTE + + m_ICR1 + :1; + +6191 +IO_BYTE + + m_ICR0 + :1; + +6192 } + mb™ +; + +6193 } + tICR36STR +; + +6195 +IO_BYTE + + mby‹ +; + +6197 + mIO_BYTE + :1; + +6198 + mIO_BYTE + :1; + +6199 + mIO_BYTE + :1; + +6200 +IO_BYTE + + m_ICR4 + :1; + +6201 +IO_BYTE + + m_ICR3 + :1; + +6202 +IO_BYTE + + m_ICR2 + :1; + +6203 +IO_BYTE + + m_ICR1 + :1; + +6204 +IO_BYTE + + m_ICR0 + :1; + +6205 } + mb™ +; + +6206 } + tICR37STR +; + +6208 +IO_BYTE + + mby‹ +; + +6210 + mIO_BYTE + :1; + +6211 + mIO_BYTE + :1; + +6212 + mIO_BYTE + :1; + +6213 +IO_BYTE + + m_ICR4 + :1; + +6214 +IO_BYTE + + m_ICR3 + :1; + +6215 +IO_BYTE + + m_ICR2 + :1; + +6216 +IO_BYTE + + m_ICR1 + :1; + +6217 +IO_BYTE + + m_ICR0 + :1; + +6218 } + mb™ +; + +6219 } + tICR38STR +; + +6221 +IO_BYTE + + mby‹ +; + +6223 + mIO_BYTE + :1; + +6224 + mIO_BYTE + :1; + +6225 + mIO_BYTE + :1; + +6226 +IO_BYTE + + m_ICR4 + :1; + +6227 +IO_BYTE + + m_ICR3 + :1; + +6228 +IO_BYTE + + m_ICR2 + :1; + +6229 +IO_BYTE + + m_ICR1 + :1; + +6230 +IO_BYTE + + m_ICR0 + :1; + +6231 } + mb™ +; + +6232 } + tICR39STR +; + +6234 +IO_BYTE + + mby‹ +; + +6236 + mIO_BYTE + :1; + +6237 + mIO_BYTE + :1; + +6238 + mIO_BYTE + :1; + +6239 +IO_BYTE + + m_ICR4 + :1; + +6240 +IO_BYTE + + m_ICR3 + :1; + +6241 +IO_BYTE + + m_ICR2 + :1; + +6242 +IO_BYTE + + m_ICR1 + :1; + +6243 +IO_BYTE + + m_ICR0 + :1; + +6244 } + mb™ +; + +6245 } + tICR40STR +; + +6247 +IO_BYTE + + mby‹ +; + +6249 + mIO_BYTE + :1; + +6250 + mIO_BYTE + :1; + +6251 + mIO_BYTE + :1; + +6252 +IO_BYTE + + m_ICR4 + :1; + +6253 +IO_BYTE + + m_ICR3 + :1; + +6254 +IO_BYTE + + m_ICR2 + :1; + +6255 +IO_BYTE + + m_ICR1 + :1; + +6256 +IO_BYTE + + m_ICR0 + :1; + +6257 } + mb™ +; + +6258 } + tICR41STR +; + +6260 +IO_BYTE + + mby‹ +; + +6262 + mIO_BYTE + :1; + +6263 + mIO_BYTE + :1; + +6264 + mIO_BYTE + :1; + +6265 +IO_BYTE + + m_ICR4 + :1; + +6266 +IO_BYTE + + m_ICR3 + :1; + +6267 +IO_BYTE + + m_ICR2 + :1; + +6268 +IO_BYTE + + m_ICR1 + :1; + +6269 +IO_BYTE + + m_ICR0 + :1; + +6270 } + mb™ +; + +6271 } + tICR42STR +; + +6273 +IO_BYTE + + mby‹ +; + +6275 + mIO_BYTE + :1; + +6276 + mIO_BYTE + :1; + +6277 + mIO_BYTE + :1; + +6278 +IO_BYTE + + m_ICR4 + :1; + +6279 +IO_BYTE + + m_ICR3 + :1; + +6280 +IO_BYTE + + m_ICR2 + :1; + +6281 +IO_BYTE + + m_ICR1 + :1; + +6282 +IO_BYTE + + m_ICR0 + :1; + +6283 } + mb™ +; + +6284 } + tICR43STR +; + +6286 +IO_BYTE + + mby‹ +; + +6288 + mIO_BYTE + :1; + +6289 + mIO_BYTE + :1; + +6290 + mIO_BYTE + :1; + +6291 +IO_BYTE + + m_ICR4 + :1; + +6292 +IO_BYTE + + m_ICR3 + :1; + +6293 +IO_BYTE + + m_ICR2 + :1; + +6294 +IO_BYTE + + m_ICR1 + :1; + +6295 +IO_BYTE + + m_ICR0 + :1; + +6296 } + mb™ +; + +6297 } + tICR44STR +; + +6299 +IO_BYTE + + mby‹ +; + +6301 + mIO_BYTE + :1; + +6302 + mIO_BYTE + :1; + +6303 + mIO_BYTE + :1; + +6304 +IO_BYTE + + m_ICR4 + :1; + +6305 +IO_BYTE + + m_ICR3 + :1; + +6306 +IO_BYTE + + m_ICR2 + :1; + +6307 +IO_BYTE + + m_ICR1 + :1; + +6308 +IO_BYTE + + m_ICR0 + :1; + +6309 } + mb™ +; + +6310 } + tICR45STR +; + +6312 +IO_BYTE + + mby‹ +; + +6314 + mIO_BYTE + :1; + +6315 + mIO_BYTE + :1; + +6316 + mIO_BYTE + :1; + +6317 +IO_BYTE + + m_ICR4 + :1; + +6318 +IO_BYTE + + m_ICR3 + :1; + +6319 +IO_BYTE + + m_ICR2 + :1; + +6320 +IO_BYTE + + m_ICR1 + :1; + +6321 +IO_BYTE + + m_ICR0 + :1; + +6322 } + mb™ +; + +6323 } + tICR46STR +; + +6325 +IO_BYTE + + mby‹ +; + +6327 + mIO_BYTE + :1; + +6328 + mIO_BYTE + :1; + +6329 + mIO_BYTE + :1; + +6330 +IO_BYTE + + m_ICR4 + :1; + +6331 +IO_BYTE + + m_ICR3 + :1; + +6332 +IO_BYTE + + m_ICR2 + :1; + +6333 +IO_BYTE + + m_ICR1 + :1; + +6334 +IO_BYTE + + m_ICR0 + :1; + +6335 } + mb™ +; + +6336 } + tICR47STR +; + +6338 +IO_BYTE + + mby‹ +; + +6340 + mIO_BYTE + :1; + +6341 + mIO_BYTE + :1; + +6342 + mIO_BYTE + :1; + +6343 +IO_BYTE + + m_ICR4 + :1; + +6344 +IO_BYTE + + m_ICR3 + :1; + +6345 +IO_BYTE + + m_ICR2 + :1; + +6346 +IO_BYTE + + m_ICR1 + :1; + +6347 +IO_BYTE + + m_ICR0 + :1; + +6348 } + mb™ +; + +6349 } + tICR48STR +; + +6351 +IO_BYTE + + mby‹ +; + +6353 + mIO_BYTE + :1; + +6354 + mIO_BYTE + :1; + +6355 + mIO_BYTE + :1; + +6356 +IO_BYTE + + m_ICR4 + :1; + +6357 +IO_BYTE + + m_ICR3 + :1; + +6358 +IO_BYTE + + m_ICR2 + :1; + +6359 +IO_BYTE + + m_ICR1 + :1; + +6360 +IO_BYTE + + m_ICR0 + :1; + +6361 } + mb™ +; + +6362 } + tICR49STR +; + +6364 +IO_BYTE + + mby‹ +; + +6366 + mIO_BYTE + :1; + +6367 + mIO_BYTE + :1; + +6368 + mIO_BYTE + :1; + +6369 +IO_BYTE + + m_ICR4 + :1; + +6370 +IO_BYTE + + m_ICR3 + :1; + +6371 +IO_BYTE + + m_ICR2 + :1; + +6372 +IO_BYTE + + m_ICR1 + :1; + +6373 +IO_BYTE + + m_ICR0 + :1; + +6374 } + mb™ +; + +6375 } + tICR50STR +; + +6377 +IO_BYTE + + mby‹ +; + +6379 + mIO_BYTE + :1; + +6380 + mIO_BYTE + :1; + +6381 + mIO_BYTE + :1; + +6382 +IO_BYTE + + m_ICR4 + :1; + +6383 +IO_BYTE + + m_ICR3 + :1; + +6384 +IO_BYTE + + m_ICR2 + :1; + +6385 +IO_BYTE + + m_ICR1 + :1; + +6386 +IO_BYTE + + m_ICR0 + :1; + +6387 } + mb™ +; + +6388 } + tICR51STR +; + +6390 +IO_BYTE + + mby‹ +; + +6392 + mIO_BYTE + :1; + +6393 + mIO_BYTE + :1; + +6394 + mIO_BYTE + :1; + +6395 +IO_BYTE + + m_ICR4 + :1; + +6396 +IO_BYTE + + m_ICR3 + :1; + +6397 +IO_BYTE + + m_ICR2 + :1; + +6398 +IO_BYTE + + m_ICR1 + :1; + +6399 +IO_BYTE + + m_ICR0 + :1; + +6400 } + mb™ +; + +6401 } + tICR52STR +; + +6403 +IO_BYTE + + mby‹ +; + +6405 + mIO_BYTE + :1; + +6406 + mIO_BYTE + :1; + +6407 + mIO_BYTE + :1; + +6408 +IO_BYTE + + m_ICR4 + :1; + +6409 +IO_BYTE + + m_ICR3 + :1; + +6410 +IO_BYTE + + m_ICR2 + :1; + +6411 +IO_BYTE + + m_ICR1 + :1; + +6412 +IO_BYTE + + m_ICR0 + :1; + +6413 } + mb™ +; + +6414 } + tICR53STR +; + +6416 +IO_BYTE + + mby‹ +; + +6418 + mIO_BYTE + :1; + +6419 + mIO_BYTE + :1; + +6420 + mIO_BYTE + :1; + +6421 +IO_BYTE + + m_ICR4 + :1; + +6422 +IO_BYTE + + m_ICR3 + :1; + +6423 +IO_BYTE + + m_ICR2 + :1; + +6424 +IO_BYTE + + m_ICR1 + :1; + +6425 +IO_BYTE + + m_ICR0 + :1; + +6426 } + mb™ +; + +6427 } + tICR54STR +; + +6429 +IO_BYTE + + mby‹ +; + +6431 + mIO_BYTE + :1; + +6432 + mIO_BYTE + :1; + +6433 + mIO_BYTE + :1; + +6434 +IO_BYTE + + m_ICR4 + :1; + +6435 +IO_BYTE + + m_ICR3 + :1; + +6436 +IO_BYTE + + m_ICR2 + :1; + +6437 +IO_BYTE + + m_ICR1 + :1; + +6438 +IO_BYTE + + m_ICR0 + :1; + +6439 } + mb™ +; + +6440 } + tICR55STR +; + +6442 +IO_BYTE + + mby‹ +; + +6444 + mIO_BYTE + :1; + +6445 + mIO_BYTE + :1; + +6446 + mIO_BYTE + :1; + +6447 +IO_BYTE + + m_ICR4 + :1; + +6448 +IO_BYTE + + m_ICR3 + :1; + +6449 +IO_BYTE + + m_ICR2 + :1; + +6450 +IO_BYTE + + m_ICR1 + :1; + +6451 +IO_BYTE + + m_ICR0 + :1; + +6452 } + mb™ +; + +6453 } + tICR56STR +; + +6455 +IO_BYTE + + mby‹ +; + +6457 + mIO_BYTE + :1; + +6458 + mIO_BYTE + :1; + +6459 + mIO_BYTE + :1; + +6460 +IO_BYTE + + m_ICR4 + :1; + +6461 +IO_BYTE + + m_ICR3 + :1; + +6462 +IO_BYTE + + m_ICR2 + :1; + +6463 +IO_BYTE + + m_ICR1 + :1; + +6464 +IO_BYTE + + m_ICR0 + :1; + +6465 } + mb™ +; + +6466 } + tICR57STR +; + +6468 +IO_BYTE + + mby‹ +; + +6470 + mIO_BYTE + :1; + +6471 + mIO_BYTE + :1; + +6472 + mIO_BYTE + :1; + +6473 +IO_BYTE + + m_ICR4 + :1; + +6474 +IO_BYTE + + m_ICR3 + :1; + +6475 +IO_BYTE + + m_ICR2 + :1; + +6476 +IO_BYTE + + m_ICR1 + :1; + +6477 +IO_BYTE + + m_ICR0 + :1; + +6478 } + mb™ +; + +6479 } + tICR58STR +; + +6481 +IO_BYTE + + mby‹ +; + +6483 + mIO_BYTE + :1; + +6484 + mIO_BYTE + :1; + +6485 + mIO_BYTE + :1; + +6486 +IO_BYTE + + m_ICR4 + :1; + +6487 +IO_BYTE + + m_ICR3 + :1; + +6488 +IO_BYTE + + m_ICR2 + :1; + +6489 +IO_BYTE + + m_ICR1 + :1; + +6490 +IO_BYTE + + m_ICR0 + :1; + +6491 } + mb™ +; + +6492 } + tICR59STR +; + +6494 +IO_BYTE + + mby‹ +; + +6496 + mIO_BYTE + :1; + +6497 + mIO_BYTE + :1; + +6498 + mIO_BYTE + :1; + +6499 +IO_BYTE + + m_ICR4 + :1; + +6500 +IO_BYTE + + m_ICR3 + :1; + +6501 +IO_BYTE + + m_ICR2 + :1; + +6502 +IO_BYTE + + m_ICR1 + :1; + +6503 +IO_BYTE + + m_ICR0 + :1; + +6504 } + mb™ +; + +6505 } + tICR60STR +; + +6507 +IO_BYTE + + mby‹ +; + +6509 + mIO_BYTE + :1; + +6510 + mIO_BYTE + :1; + +6511 + mIO_BYTE + :1; + +6512 +IO_BYTE + + m_ICR4 + :1; + +6513 +IO_BYTE + + m_ICR3 + :1; + +6514 +IO_BYTE + + m_ICR2 + :1; + +6515 +IO_BYTE + + m_ICR1 + :1; + +6516 +IO_BYTE + + m_ICR0 + :1; + +6517 } + mb™ +; + +6518 } + tICR61STR +; + +6520 +IO_BYTE + + mby‹ +; + +6522 + mIO_BYTE + :1; + +6523 + mIO_BYTE + :1; + +6524 + mIO_BYTE + :1; + +6525 +IO_BYTE + + m_ICR4 + :1; + +6526 +IO_BYTE + + m_ICR3 + :1; + +6527 +IO_BYTE + + m_ICR2 + :1; + +6528 +IO_BYTE + + m_ICR1 + :1; + +6529 +IO_BYTE + + m_ICR0 + :1; + +6530 } + mb™ +; + +6531 } + tICR62STR +; + +6533 +IO_BYTE + + mby‹ +; + +6535 + mIO_BYTE + :1; + +6536 + mIO_BYTE + :1; + +6537 + mIO_BYTE + :1; + +6538 +IO_BYTE + + m_ICR4 + :1; + +6539 +IO_BYTE + + m_ICR3 + :1; + +6540 +IO_BYTE + + m_ICR2 + :1; + +6541 +IO_BYTE + + m_ICR1 + :1; + +6542 +IO_BYTE + + m_ICR0 + :1; + +6543 } + mb™ +; + +6544 } + tICR63STR +; + +6546 +IO_BYTE + + mby‹ +; + +6548 +IO_BYTE + + m_INIT + :1; + +6549 +IO_BYTE + + m_HSTB + :1; + +6550 +IO_BYTE + + m_WDOG + :1; + +6551 +IO_BYTE + + m_ERST + :1; + +6552 +IO_BYTE + + m_SRST + :1; + +6553 +IO_BYTE + + m_LINIT + :1; + +6554 +IO_BYTE + + m_WT1 + :1; + +6555 +IO_BYTE + + m_WT0 + :1; + +6556 } + mb™ +; + +6558 + mIO_BYTE + :1; + +6559 + mIO_BYTE + :1; + +6560 + mIO_BYTE + :1; + +6561 + mIO_BYTE + :1; + +6562 + mIO_BYTE + :1; + +6563 + mIO_BYTE + :1; + +6564 +IO_BYTE + + m_WT + :2; + +6565 } + mb™c +; + +6566 } + tRSRRSTR +; + +6568 +IO_BYTE + + mby‹ +; + +6570 +IO_BYTE + + m_STOP + :1; + +6571 +IO_BYTE + + m_SLEEP + :1; + +6572 +IO_BYTE + + m_HIZ + :1; + +6573 +IO_BYTE + + m_SRST + :1; + +6574 +IO_BYTE + + m_OS1 + :1; + +6575 +IO_BYTE + + m_OS0 + :1; + +6576 +IO_BYTE + + m_OSCD2 + :1; + +6577 +IO_BYTE + + m_OSCD1 + :1; + +6578 } + mb™ +; + +6580 + mIO_BYTE + :1; + +6581 + mIO_BYTE + :1; + +6582 + mIO_BYTE + :1; + +6583 + mIO_BYTE + :1; + +6584 +IO_BYTE + + m_OS + :2; + +6585 +IO_BYTE + + m_OSCD + :2; + +6586 } + mb™c +; + +6587 } + tSTCRSTR +; + +6589 +IO_BYTE + + mby‹ +; + +6591 +IO_BYTE + + m_TBIF + :1; + +6592 +IO_BYTE + + m_TBIE + :1; + +6593 +IO_BYTE + + m_TBC2 + :1; + +6594 +IO_BYTE + + m_TBC1 + :1; + +6595 +IO_BYTE + + m_TBC0 + :1; + +6596 + mIO_BYTE + :1; + +6597 +IO_BYTE + + m_SYNCR + :1; + +6598 +IO_BYTE + + m_SYNCS + :1; + +6599 } + mb™ +; + +6601 + mIO_BYTE + :1; + +6602 + mIO_BYTE + :1; + +6603 +IO_BYTE + + m_TBC + :3; + +6604 } + mb™c +; + +6605 } + tTBCRSTR +; + +6607 +IO_BYTE + + mby‹ +; + +6609 +IO_BYTE + + m_D7 + :1; + +6610 +IO_BYTE + + m_D6 + :1; + +6611 +IO_BYTE + + m_D5 + :1; + +6612 +IO_BYTE + + m_D4 + :1; + +6613 +IO_BYTE + + m_D3 + :1; + +6614 +IO_BYTE + + m_D2 + :1; + +6615 +IO_BYTE + + m_D1 + :1; + +6616 +IO_BYTE + + m_D0 + :1; + +6617 } + mb™ +; + +6618 } + tCTBRSTR +; + +6620 +IO_BYTE + + mby‹ +; + +6622 + mIO_BYTE + :1; + +6623 + mIO_BYTE + :1; + +6624 + mIO_BYTE + :1; + +6625 + mIO_BYTE + :1; + +6626 +IO_BYTE + + m_SCKEN + :1; + +6627 +IO_BYTE + + m_PLL1EN + :1; + +6628 +IO_BYTE + + m_CLKS1 + :1; + +6629 +IO_BYTE + + m_CLKS0 + :1; + +6630 } + mb™ +; + +6632 + mIO_BYTE + :1; + +6633 + mIO_BYTE + :1; + +6634 + mIO_BYTE + :1; + +6635 + mIO_BYTE + :1; + +6636 + mIO_BYTE + :1; + +6637 + mIO_BYTE + :1; + +6638 +IO_BYTE + + m_CLKS + :2; + +6639 } + mb™c +; + +6640 } + tCLKRSTR +; + +6642 +IO_BYTE + + mby‹ +; + +6644 +IO_BYTE + + m_D7 + :1; + +6645 +IO_BYTE + + m_D6 + :1; + +6646 +IO_BYTE + + m_D5 + :1; + +6647 +IO_BYTE + + m_D4 + :1; + +6648 +IO_BYTE + + m_D3 + :1; + +6649 +IO_BYTE + + m_D2 + :1; + +6650 +IO_BYTE + + m_D1 + :1; + +6651 +IO_BYTE + + m_D0 + :1; + +6652 } + mb™ +; + +6653 } + tWPRSTR +; + +6655 +IO_BYTE + + mby‹ +; + +6657 +IO_BYTE + + m_B3 + :1; + +6658 +IO_BYTE + + m_B2 + :1; + +6659 +IO_BYTE + + m_B1 + :1; + +6660 +IO_BYTE + + m_B0 + :1; + +6661 +IO_BYTE + + m_P3 + :1; + +6662 +IO_BYTE + + m_P2 + :1; + +6663 +IO_BYTE + + m_P1 + :1; + +6664 +IO_BYTE + + m_P0 + :1; + +6665 } + mb™ +; + +6667 +IO_BYTE + + m_B + :4; + +6668 +IO_BYTE + + m_P + :4; + +6669 } + mb™c +; + +6670 } + tDIVR0STR +; + +6672 +IO_BYTE + + mby‹ +; + +6674 +IO_BYTE + + m_T3 + :1; + +6675 +IO_BYTE + + m_T2 + :1; + +6676 +IO_BYTE + + m_T1 + :1; + +6677 +IO_BYTE + + m_T0 + :1; + +6678 + mIO_BYTE + :1; + +6679 + mIO_BYTE + :1; + +6680 + mIO_BYTE + :1; + +6681 + mIO_BYTE + :1; + +6682 } + mb™ +; + +6684 +IO_BYTE + + m_T + :4; + +6685 } + mb™c +; + +6686 } + tDIVR1STR +; + +6688 +IO_BYTE + + mby‹ +; + +6690 + mIO_BYTE + :1; + +6691 + mIO_BYTE + :1; + +6692 + mIO_BYTE + :1; + +6693 + mIO_BYTE + :1; + +6694 +IO_BYTE + + m_DVM3 + :1; + +6695 +IO_BYTE + + m_DVM2 + :1; + +6696 +IO_BYTE + + m_DVM1 + :1; + +6697 +IO_BYTE + + m_DVM0 + :1; + +6698 } + mb™ +; + +6700 + mIO_BYTE + :1; + +6701 + mIO_BYTE + :1; + +6702 + mIO_BYTE + :1; + +6703 + mIO_BYTE + :1; + +6704 +IO_BYTE + + m_DVM + :4; + +6705 } + mb™c +; + +6706 } + tPLLDIVMSTR +; + +6708 +IO_BYTE + + mby‹ +; + +6710 + mIO_BYTE + :1; + +6711 + mIO_BYTE + :1; + +6712 +IO_BYTE + + m_DVN5 + :1; + +6713 +IO_BYTE + + m_DVN4 + :1; + +6714 +IO_BYTE + + m_DVN3 + :1; + +6715 +IO_BYTE + + m_DVN2 + :1; + +6716 +IO_BYTE + + m_DVN1 + :1; + +6717 +IO_BYTE + + m_DVN0 + :1; + +6718 } + mb™ +; + +6720 + mIO_BYTE + :1; + +6721 + mIO_BYTE + :1; + +6722 +IO_BYTE + + m_DVN + :6; + +6723 } + mb™c +; + +6724 } + tPLLDIVNSTR +; + +6726 +IO_BYTE + + mby‹ +; + +6728 + mIO_BYTE + :1; + +6729 + mIO_BYTE + :1; + +6730 + mIO_BYTE + :1; + +6731 + mIO_BYTE + :1; + +6732 +IO_BYTE + + m_DVG3 + :1; + +6733 +IO_BYTE + + m_DVG2 + :1; + +6734 +IO_BYTE + + m_DVG1 + :1; + +6735 +IO_BYTE + + m_DVG0 + :1; + +6736 } + mb™ +; + +6738 + mIO_BYTE + :1; + +6739 + mIO_BYTE + :1; + +6740 + mIO_BYTE + :1; + +6741 + mIO_BYTE + :1; + +6742 +IO_BYTE + + m_DVG + :4; + +6743 } + mb™c +; + +6744 } + tPLLDIVGSTR +; + +6746 +IO_BYTE + + mby‹ +; + +6748 +IO_BYTE + + m_MLG7 + :1; + +6749 +IO_BYTE + + m_MLG6 + :1; + +6750 +IO_BYTE + + m_MLG5 + :1; + +6751 +IO_BYTE + + m_MLG4 + :1; + +6752 +IO_BYTE + + m_MLG3 + :1; + +6753 +IO_BYTE + + m_MLG2 + :1; + +6754 +IO_BYTE + + m_MLG1 + :1; + +6755 +IO_BYTE + + m_MLG0 + :1; + +6756 } + mb™ +; + +6758 +IO_BYTE + + m_MLG + :8; + +6759 } + mb™c +; + +6760 } + tPLLMULGSTR +; + +6762 +IO_BYTE + + mby‹ +; + +6764 + mIO_BYTE + :1; + +6765 + mIO_BYTE + :1; + +6766 + mIO_BYTE + :1; + +6767 + mIO_BYTE + :1; + +6768 +IO_BYTE + + m_IEDN + :1; + +6769 +IO_BYTE + + m_GRDN + :1; + +6770 +IO_BYTE + + m_IEUP + :1; + +6771 +IO_BYTE + + m_GRUP + :1; + +6772 } + mb™ +; + +6773 } + tPLLCTRLSTR +; + +6775 +IO_BYTE + + mby‹ +; + +6777 + mIO_BYTE + :1; + +6778 + mIO_BYTE + :1; + +6779 + mIO_BYTE + :1; + +6780 + mIO_BYTE + :1; + +6781 + mIO_BYTE + :1; + +6782 +IO_BYTE + + m_FCI + :1; + +6783 +IO_BYTE + + m_RFBEN + :1; + +6784 +IO_BYTE + + m_OSCR + :1; + +6785 } + mb™ +; + +6786 } + tOSCC1STR +; + +6788 +IO_BYTE + + mby‹ +; + +6790 +IO_BYTE + + m_OSCS7 + :1; + +6791 +IO_BYTE + + m_OSCS6 + :1; + +6792 +IO_BYTE + + m_OSCS5 + :1; + +6793 +IO_BYTE + + m_OSCS4 + :1; + +6794 +IO_BYTE + + m_OSCS3 + :1; + +6795 +IO_BYTE + + m_OSCS2 + :1; + +6796 +IO_BYTE + + m_OSCS1 + :1; + +6797 +IO_BYTE + + m_OSCS0 + :1; + +6798 } + mb™ +; + +6799 } + tOSCS1STR +; + +6801 +IO_BYTE + + mby‹ +; + +6803 + mIO_BYTE + :1; + +6804 + mIO_BYTE + :1; + +6805 + mIO_BYTE + :1; + +6806 + mIO_BYTE + :1; + +6807 + mIO_BYTE + :1; + +6808 +IO_BYTE + + m_FCI + :1; + +6809 +IO_BYTE + + m_RFBEN + :1; + +6810 +IO_BYTE + + m_OSCR + :1; + +6811 } + mb™ +; + +6812 } + tOSCC2STR +; + +6814 +IO_BYTE + + mby‹ +; + +6816 +IO_BYTE + + m_OSCS7 + :1; + +6817 +IO_BYTE + + m_OSCS6 + :1; + +6818 +IO_BYTE + + m_OSCS5 + :1; + +6819 +IO_BYTE + + m_OSCS4 + :1; + +6820 +IO_BYTE + + m_OSCS3 + :1; + +6821 +IO_BYTE + + m_OSCS2 + :1; + +6822 +IO_BYTE + + m_OSCS1 + :1; + +6823 +IO_BYTE + + m_OSCS0 + :1; + +6824 } + mb™ +; + +6825 } + tOSCS2STR +; + +6827 +IO_BYTE + + mby‹ +; + +6829 + mIO_BYTE + :1; + +6830 + mIO_BYTE + :1; + +6831 + mIO_BYTE + :1; + +6832 + mIO_BYTE + :1; + +6833 + mIO_BYTE + :1; + +6834 + mIO_BYTE + :1; + +6835 +IO_BYTE + + m_CPORTEN + :1; + +6836 +IO_BYTE + + m_GPORTEN + :1; + +6837 } + mb™ +; + +6838 } + tPORTENSTR +; + +6840 +IO_BYTE + + mby‹ +; + +6842 + mIO_BYTE + :1; + +6843 + mIO_BYTE + :1; + +6844 + mIO_BYTE + :1; + +6845 + mIO_BYTE + :1; + +6846 + mIO_BYTE + :1; + +6847 + mIO_BYTE + :1; + +6848 +IO_BYTE + + m_INTE4 + :1; + +6849 +IO_BYTE + + m_INT4 + :1; + +6850 } + mb™ +; + +6851 } + tWTCERSTR +; + +6853 +IO_WORD + + mwÜd +; + +6855 +IO_WORD + + m_INTE3 + :1; + +6856 +IO_WORD + + m_INT3 + :1; + +6857 +IO_WORD + + m_INTE2 + :1; + +6858 +IO_WORD + + m_INT2 + :1; + +6859 +IO_WORD + + m_INTE1 + :1; + +6860 +IO_WORD + + m_INT1 + :1; + +6861 +IO_WORD + + m_INTE0 + :1; + +6862 +IO_WORD + + m_INT0 + :1; + +6863 + mIO_WORD + :1; + +6864 + mIO_WORD + :1; + +6865 + mIO_WORD + :1; + +6866 + mIO_WORD + :1; + +6867 +IO_WORD + + m_RUN + :1; + +6868 +IO_WORD + + m_UPDT + :1; + +6869 + mIO_WORD + :1; + +6870 +IO_WORD + + m_ST + :1; + +6871 } + mb™ +; + +6872 } + tWTCRSTR +; + +6874 +IO_LWORD + + mlwÜd +; + +6876 + mIO_LWORD + :1; + +6877 + mIO_LWORD + :1; + +6878 + mIO_LWORD + :1; + +6879 + mIO_LWORD + :1; + +6880 + mIO_LWORD + :1; + +6881 + mIO_LWORD + :1; + +6882 + mIO_LWORD + :1; + +6883 + mIO_LWORD + :1; + +6884 + mIO_LWORD + :1; + +6885 + mIO_LWORD + :1; + +6886 + mIO_LWORD + :1; + +6887 +IO_LWORD + + m_D20 + :1; + +6888 +IO_LWORD + + m_D19 + :1; + +6889 +IO_LWORD + + m_D18 + :1; + +6890 +IO_LWORD + + m_D17 + :1; + +6891 +IO_LWORD + + m_D16 + :1; + +6892 +IO_LWORD + + m_D15 + :1; + +6893 +IO_LWORD + + m_D14 + :1; + +6894 +IO_LWORD + + m_D13 + :1; + +6895 +IO_LWORD + + m_D12 + :1; + +6896 +IO_LWORD + + m_D11 + :1; + +6897 +IO_LWORD + + m_D10 + :1; + +6898 +IO_LWORD + + m_D9 + :1; + +6899 +IO_LWORD + + m_D8 + :1; + +6900 +IO_LWORD + + m_D7 + :1; + +6901 +IO_LWORD + + m_D6 + :1; + +6902 +IO_LWORD + + m_D5 + :1; + +6903 +IO_LWORD + + m_D4 + :1; + +6904 +IO_LWORD + + m_D3 + :1; + +6905 +IO_LWORD + + m_D2 + :1; + +6906 +IO_LWORD + + m_D1 + :1; + +6907 +IO_LWORD + + m_D0 + :1; + +6908 } + mb™ +; + +6909 } + tWTBRSTR +; + +6911 +IO_BYTE + + mby‹ +; + +6913 + mIO_BYTE + :1; + +6914 + mIO_BYTE + :1; + +6915 + mIO_BYTE + :1; + +6916 +IO_BYTE + + m_H4 + :1; + +6917 +IO_BYTE + + m_H3 + :1; + +6918 +IO_BYTE + + m_H2 + :1; + +6919 +IO_BYTE + + m_H1 + :1; + +6920 +IO_BYTE + + m_H0 + :1; + +6921 } + mb™ +; + +6922 } + tWTHRSTR +; + +6924 +IO_BYTE + + mby‹ +; + +6926 + mIO_BYTE + :1; + +6927 + mIO_BYTE + :1; + +6928 +IO_BYTE + + m_M5 + :1; + +6929 +IO_BYTE + + m_M4 + :1; + +6930 +IO_BYTE + + m_M3 + :1; + +6931 +IO_BYTE + + m_M2 + :1; + +6932 +IO_BYTE + + m_M1 + :1; + +6933 +IO_BYTE + + m_M0 + :1; + +6934 } + mb™ +; + +6935 } + tWTMRSTR +; + +6937 +IO_BYTE + + mby‹ +; + +6939 + mIO_BYTE + :1; + +6940 + mIO_BYTE + :1; + +6941 +IO_BYTE + + m_S5 + :1; + +6942 +IO_BYTE + + m_S4 + :1; + +6943 +IO_BYTE + + m_S3 + :1; + +6944 +IO_BYTE + + m_S2 + :1; + +6945 +IO_BYTE + + m_S1 + :1; + +6946 +IO_BYTE + + m_S0 + :1; + +6947 } + mb™ +; + +6948 } + tWTSRSTR +; + +6950 +IO_BYTE + + mby‹ +; + +6952 +IO_BYTE + + m_SCKS + :1; + +6953 +IO_BYTE + + m_MM + :1; + +6954 +IO_BYTE + + m_SM + :1; + +6955 +IO_BYTE + + m_RCE + :1; + +6956 +IO_BYTE + + m_MSVE + :1; + +6957 +IO_BYTE + + m_SSVE + :1; + +6958 +IO_BYTE + + m_SRST + :1; + +6959 +IO_BYTE + + m_OUTE + :1; + +6960 } + mb™ +; + +6961 } + tCSVCRSTR +; + +6963 +IO_BYTE + + mby‹ +; + +6965 +IO_BYTE + + m_EDSUEN + :1; + +6966 +IO_BYTE + + m_PLLLOCK + :1; + +6967 +IO_BYTE + + m_RCSEL + :1; + +6968 +IO_BYTE + + m_MONCKI + :1; + +6969 +IO_BYTE + + m_CSC3 + :1; + +6970 +IO_BYTE + + m_CSC2 + :1; + +6971 +IO_BYTE + + m_CSC1 + :1; + +6972 +IO_BYTE + + m_CSC0 + :1; + +6973 } + mb™ +; + +6975 + mIO_BYTE + :4; + +6976 +IO_BYTE + + m_CSC + :4; + +6977 } + mb™c +; + +6978 } + tCSCFGSTR +; + +6980 +IO_BYTE + + mby‹ +; + +6982 +IO_BYTE + + m_CMPRE3 + :1; + +6983 +IO_BYTE + + m_CMPRE2 + :1; + +6984 +IO_BYTE + + m_CMPRE1 + :1; + +6985 +IO_BYTE + + m_CMPRE0 + :1; + +6986 +IO_BYTE + + m_CMSEL3 + :1; + +6987 +IO_BYTE + + m_CMSEL2 + :1; + +6988 +IO_BYTE + + m_CMSEL1 + :1; + +6989 +IO_BYTE + + m_CMSEL0 + :1; + +6990 } + mb™ +; + +6992 +IO_BYTE + + m_CMPRE + :4; + +6993 +IO_BYTE + + m_CMSEL + :4; + +6994 } + mb™c +; + +6995 } + tCMCFGSTR +; + +6997 +IO_WORD + + mwÜd +; + +6999 + mIO_WORD + :1; + +7000 + mIO_WORD + :1; + +7001 + mIO_WORD + :1; + +7002 + mIO_WORD + :1; + +7003 + mIO_WORD + :1; + +7004 + mIO_WORD + :1; + +7005 + mIO_WORD + :1; + +7006 + mIO_WORD + :1; + +7007 + mIO_WORD + :1; + +7008 + mIO_WORD + :1; + +7009 + mIO_WORD + :1; + +7010 +IO_WORD + + m_STRT + :1; + +7011 + mIO_WORD + :1; + +7012 + mIO_WORD + :1; + +7013 +IO_WORD + + m_INT + :1; + +7014 +IO_WORD + + m_INTEN + :1; + +7015 } + mb™ +; + +7016 } + tCUCRSTR +; + +7018 +IO_WORD + + mwÜd +; + +7020 +IO_WORD + + m_TDD15 + :1; + +7021 +IO_WORD + + m_TDD14 + :1; + +7022 +IO_WORD + + m_TDD13 + :1; + +7023 +IO_WORD + + m_TDD12 + :1; + +7024 +IO_WORD + + m_TDD11 + :1; + +7025 +IO_WORD + + m_TDD10 + :1; + +7026 +IO_WORD + + m_TDD9 + :1; + +7027 +IO_WORD + + m_TDD8 + :1; + +7028 +IO_WORD + + m_TDD7 + :1; + +7029 +IO_WORD + + m_TDD6 + :1; + +7030 +IO_WORD + + m_TDD5 + :1; + +7031 +IO_WORD + + m_TDD4 + :1; + +7032 +IO_WORD + + m_TDD3 + :1; + +7033 +IO_WORD + + m_TDD2 + :1; + +7034 +IO_WORD + + m_TDD1 + :1; + +7035 +IO_WORD + + m_TDD0 + :1; + +7036 } + mb™ +; + +7037 } + tCUTDSTR +; + +7039 +IO_WORD + + mwÜd +; + +7041 + mIO_WORD + :1; + +7042 + mIO_WORD + :1; + +7043 + mIO_WORD + :1; + +7044 + mIO_WORD + :1; + +7045 + mIO_WORD + :1; + +7046 + mIO_WORD + :1; + +7047 + mIO_WORD + :1; + +7048 + mIO_WORD + :1; + +7049 +IO_WORD + + m_TDR23 + :1; + +7050 +IO_WORD + + m_TDR22 + :1; + +7051 +IO_WORD + + m_TDR21 + :1; + +7052 +IO_WORD + + m_TDR20 + :1; + +7053 +IO_WORD + + m_TDR19 + :1; + +7054 +IO_WORD + + m_TDR18 + :1; + +7055 +IO_WORD + + m_TDR17 + :1; + +7056 +IO_WORD + + m_TDR16 + :1; + +7057 } + mb™ +; + +7058 } + tCUTR1STR +; + +7060 +IO_WORD + + mwÜd +; + +7062 +IO_WORD + + m_TDR15 + :1; + +7063 +IO_WORD + + m_TDR14 + :1; + +7064 +IO_WORD + + m_TDR13 + :1; + +7065 +IO_WORD + + m_TDR12 + :1; + +7066 +IO_WORD + + m_TDR11 + :1; + +7067 +IO_WORD + + m_TDR10 + :1; + +7068 +IO_WORD + + m_TDR9 + :1; + +7069 +IO_WORD + + m_TDR8 + :1; + +7070 +IO_WORD + + m_TDR7 + :1; + +7071 +IO_WORD + + m_TDR6 + :1; + +7072 +IO_WORD + + m_TDR5 + :1; + +7073 +IO_WORD + + m_TDR4 + :1; + +7074 +IO_WORD + + m_TDR3 + :1; + +7075 +IO_WORD + + m_TDR2 + :1; + +7076 +IO_WORD + + m_TDR1 + :1; + +7077 +IO_WORD + + m_TDR0 + :1; + +7078 } + mb™ +; + +7079 } + tCUTR2STR +; + +7081 +IO_WORD + + mwÜd +; + +7083 + mIO_WORD + :1; + +7084 + mIO_WORD + :1; + +7085 +IO_WORD + + m_MP13 + :1; + +7086 +IO_WORD + + m_MP12 + :1; + +7087 +IO_WORD + + m_MP11 + :1; + +7088 +IO_WORD + + m_MP10 + :1; + +7089 +IO_WORD + + m_MP9 + :1; + +7090 +IO_WORD + + m_MP8 + :1; + +7091 +IO_WORD + + m_MP7 + :1; + +7092 +IO_WORD + + m_MP6 + :1; + +7093 +IO_WORD + + m_MP5 + :1; + +7094 +IO_WORD + + m_MP4 + :1; + +7095 +IO_WORD + + m_MP3 + :1; + +7096 +IO_WORD + + m_MP2 + :1; + +7097 +IO_WORD + + m_MP1 + :1; + +7098 +IO_WORD + + m_MP0 + :1; + +7099 } + mb™ +; + +7100 } + tCMPRSTR +; + +7102 +IO_BYTE + + mby‹ +; + +7104 + mIO_BYTE + :1; + +7105 + mIO_BYTE + :1; + +7106 + mIO_BYTE + :1; + +7107 + mIO_BYTE + :1; + +7108 +IO_BYTE + + m_FMODRUN + :1; + +7109 + mIO_BYTE + :1; + +7110 +IO_BYTE + + m_FMOD + :1; + +7111 +IO_BYTE + + m_PDX + :1; + +7112 } + mb™ +; + +7113 } + tCMCRSTR +; + +7115 +IO_BYTE + + mby‹ +; + +7117 + mIO_BYTE + :1; + +7118 + mIO_BYTE + :1; + +7119 +IO_BYTE + + m_CPCKS1 + :1; + +7120 +IO_BYTE + + m_CPCKS0 + :1; + +7121 +IO_BYTE + + m_DVC3 + :1; + +7122 +IO_BYTE + + m_DVC2 + :1; + +7123 +IO_BYTE + + m_DVC1 + :1; + +7124 +IO_BYTE + + m_DVC0 + :1; + +7125 } + mb™ +; + +7127 + mIO_BYTE + :2; + +7128 +IO_BYTE + + m_CPCKS + :2; + +7129 +IO_BYTE + + m_DVC + :4; + +7130 } + mb™c +; + +7131 } + tCANPRESTR +; + +7133 +IO_BYTE + + mby‹ +; + +7135 + mIO_BYTE + :1; + +7136 + mIO_BYTE + :1; + +7137 +IO_BYTE + + m_CANCKD5 + :1; + +7138 +IO_BYTE + + m_CANCKD4 + :1; + +7139 +IO_BYTE + + m_CANCKD3 + :1; + +7140 +IO_BYTE + + m_CANCKD2 + :1; + +7141 +IO_BYTE + + m_CANCKD1 + :1; + +7142 +IO_BYTE + + m_CANCKD0 + :1; + +7143 } + mb™ +; + +7144 } + tCANCKDSTR +; + +7146 +IO_BYTE + + mby‹ +; + +7148 +IO_BYTE + + m_LVESEL3 + :1; + +7149 +IO_BYTE + + m_LVESEL2 + :1; + +7150 +IO_BYTE + + m_LVESEL1 + :1; + +7151 +IO_BYTE + + m_LVESEL0 + :1; + +7152 +IO_BYTE + + m_LVISEL3 + :1; + +7153 +IO_BYTE + + m_LVISEL2 + :1; + +7154 +IO_BYTE + + m_LVISEL1 + :1; + +7155 +IO_BYTE + + m_LVISEL0 + :1; + +7156 } + mb™ +; + +7158 +IO_BYTE + + m_LVESEL + :4; + +7159 +IO_BYTE + + m_LVISEL + :4; + +7160 } + mb™c +; + +7161 } + tLVSELSTR +; + +7163 +IO_BYTE + + mby‹ +; + +7165 + mIO_BYTE + :1; + +7166 +IO_BYTE + + m_LVSEL + :1; + +7167 +IO_BYTE + + m_LVEPD + :1; + +7168 +IO_BYTE + + m_LVIPD + :1; + +7169 +IO_BYTE + + m_LVREN + :1; + +7170 + mIO_BYTE + :1; + +7171 +IO_BYTE + + m_LVIEN + :1; + +7172 +IO_BYTE + + m_LVIRQ + :1; + +7173 } + mb™ +; + +7174 } + tLVDETSTR +; + +7176 +IO_BYTE + + mby‹ +; + +7178 + mIO_BYTE + :1; + +7179 + mIO_BYTE + :1; + +7180 + mIO_BYTE + :1; + +7181 + mIO_BYTE + :1; + +7182 + mIO_BYTE + :1; + +7183 + mIO_BYTE + :1; + +7184 +IO_BYTE + + m_ED1 + :1; + +7185 +IO_BYTE + + m_ED0 + :1; + +7186 } + mb™ +; + +7188 + mIO_BYTE + :1; + +7189 + mIO_BYTE + :1; + +7190 + mIO_BYTE + :1; + +7191 + mIO_BYTE + :1; + +7192 + mIO_BYTE + :1; + +7193 + mIO_BYTE + :1; + +7194 +IO_BYTE + + m_ED + :2; + +7195 } + mb™c +; + +7196 } + tHWWDESTR +; + +7198 +IO_BYTE + + mby‹ +; + +7200 + mIO_BYTE + :1; + +7201 + mIO_BYTE + :1; + +7202 + mIO_BYTE + :1; + +7203 + mIO_BYTE + :1; + +7204 +IO_BYTE + + m_CL + :1; + +7205 + mIO_BYTE + :1; + +7206 + mIO_BYTE + :1; + +7207 +IO_BYTE + + m_CPUF + :1; + +7208 } + mb™ +; + +7209 } + tHWWDSTR +; + +7211 +IO_BYTE + + mby‹ +; + +7213 +IO_BYTE + + m_WIF + :1; + +7214 +IO_BYTE + + m_WIE + :1; + +7215 +IO_BYTE + + m_WEN + :1; + +7216 + mIO_BYTE + :1; + +7217 + mIO_BYTE + :1; + +7218 +IO_BYTE + + m_WS1 + :1; + +7219 +IO_BYTE + + m_WS0 + :1; + +7220 +IO_BYTE + + m_WCL + :1; + +7221 } + mb™ +; + +7223 + mIO_BYTE + :1; + +7224 + mIO_BYTE + :1; + +7225 + mIO_BYTE + :1; + +7226 + mIO_BYTE + :1; + +7227 + mIO_BYTE + :1; + +7228 +IO_BYTE + + m_WS + :2; + +7229 } + mb™c +; + +7230 } + tOSCRHSTR +; + +7232 +IO_BYTE + + mby‹ +; + +7234 +IO_BYTE + + m_WIF + :1; + +7235 +IO_BYTE + + m_WIE + :1; + +7236 +IO_BYTE + + m_WEN + :1; + +7237 + mIO_BYTE + :1; + +7238 + mIO_BYTE + :1; + +7239 +IO_BYTE + + m_WS1 + :1; + +7240 +IO_BYTE + + m_WS0 + :1; + +7241 +IO_BYTE + + m_WCL + :1; + +7242 } + mb™ +; + +7244 + mIO_BYTE + :1; + +7245 + mIO_BYTE + :1; + +7246 + mIO_BYTE + :1; + +7247 + mIO_BYTE + :1; + +7248 + mIO_BYTE + :1; + +7249 +IO_BYTE + + m_WS + :2; + +7250 } + mb™c +; + +7251 } + tWPCRHSTR +; + +7253 +IO_BYTE + + mby‹ +; + +7255 + mIO_BYTE + :1; + +7256 + mIO_BYTE + :1; + +7257 + mIO_BYTE + :1; + +7258 + mIO_BYTE + :1; + +7259 + mIO_BYTE + :1; + +7260 + mIO_BYTE + :1; + +7261 + mIO_BYTE + :1; + +7262 +IO_BYTE + + m_OSCDS1 + :1; + +7263 } + mb™ +; + +7264 } + tOSCCRSTR +; + +7266 +IO_BYTE + + mby‹ +; + +7268 + mIO_BYTE + :1; + +7269 + mIO_BYTE + :1; + +7270 +IO_BYTE + + m_FLASHSEL + :1; + +7271 +IO_BYTE + + m_MAINSEL + :1; + +7272 +IO_BYTE + + m_SUBSEL3 + :1; + +7273 +IO_BYTE + + m_SUBSEL2 + :1; + +7274 +IO_BYTE + + m_SUBSEL1 + :1; + +7275 +IO_BYTE + + m_SUBSEL0 + :1; + +7276 } + mb™ +; + +7278 + mIO_BYTE + :4; + +7279 +IO_BYTE + + m_SUBSEL + :4; + +7280 } + mb™c +; + +7281 } + tREGSELSTR +; + +7283 +IO_BYTE + + mby‹ +; + +7285 + mIO_BYTE + :1; + +7286 + mIO_BYTE + :1; + +7287 + mIO_BYTE + :1; + +7288 +IO_BYTE + + m_MSTBO + :1; + +7289 + mIO_BYTE + :1; + +7290 + mIO_BYTE + :1; + +7291 +IO_BYTE + + m_MAINKPEN + :1; + +7292 +IO_BYTE + + m_MAINDSBL + :1; + +7293 } + mb™ +; + +7294 } + tREGCTRSTR +; + +7296 +IO_BYTE + + mby‹ +; + +7298 + mIO_BYTE + :1; + +7299 + mIO_BYTE + :1; + +7300 + mIO_BYTE + :1; + +7301 + mIO_BYTE + :1; + +7302 + mIO_BYTE + :1; + +7303 +IO_BYTE + + m_ROMA + :1; + +7304 +IO_BYTE + + m_WTH1 + :1; + +7305 +IO_BYTE + + m_WTH0 + :1; + +7306 } + mb™ +; + +7308 + mIO_BYTE + :1; + +7309 + mIO_BYTE + :1; + +7310 + mIO_BYTE + :1; + +7311 + mIO_BYTE + :1; + +7312 + mIO_BYTE + :1; + +7313 + mIO_BYTE + :1; + +7314 +IO_BYTE + + m_WTH + :2; + +7315 } + mb™c +; + +7316 } + tMODRSTR +; + +7318 +IO_BYTE + + mby‹ +; + +7320 +IO_BYTE + + m_D7 + :1; + +7321 +IO_BYTE + + m_D6 + :1; + +7322 +IO_BYTE + + m_D5 + :1; + +7323 +IO_BYTE + + m_D4 + :1; + +7324 +IO_BYTE + + m_D3 + :1; + +7325 +IO_BYTE + + m_D2 + :1; + +7326 +IO_BYTE + + m_D1 + :1; + +7327 +IO_BYTE + + m_D0 + :1; + +7328 } + mb™ +; + +7329 } + tPDRD14STR +; + +7331 +IO_BYTE + + mby‹ +; + +7333 +IO_BYTE + + m_D7 + :1; + +7334 +IO_BYTE + + m_D6 + :1; + +7335 +IO_BYTE + + m_D5 + :1; + +7336 +IO_BYTE + + m_D4 + :1; + +7337 +IO_BYTE + + m_D3 + :1; + +7338 +IO_BYTE + + m_D2 + :1; + +7339 +IO_BYTE + + m_D1 + :1; + +7340 +IO_BYTE + + m_D0 + :1; + +7341 } + mb™ +; + +7342 } + tPDRD15STR +; + +7344 +IO_BYTE + + mby‹ +; + +7346 +IO_BYTE + + m_D7 + :1; + +7347 +IO_BYTE + + m_D6 + :1; + +7348 +IO_BYTE + + m_D5 + :1; + +7349 +IO_BYTE + + m_D4 + :1; + +7350 +IO_BYTE + + m_D3 + :1; + +7351 +IO_BYTE + + m_D2 + :1; + +7352 +IO_BYTE + + m_D1 + :1; + +7353 +IO_BYTE + + m_D0 + :1; + +7354 } + mb™ +; + +7355 } + tPDRD16STR +; + +7357 +IO_BYTE + + mby‹ +; + +7359 +IO_BYTE + + m_D7 + :1; + +7360 +IO_BYTE + + m_D6 + :1; + +7361 +IO_BYTE + + m_D5 + :1; + +7362 +IO_BYTE + + m_D4 + :1; + +7363 +IO_BYTE + + m_D3 + :1; + +7364 +IO_BYTE + + m_D2 + :1; + +7365 +IO_BYTE + + m_D1 + :1; + +7366 +IO_BYTE + + m_D0 + :1; + +7367 } + mb™ +; + +7368 } + tPDRD17STR +; + +7370 +IO_BYTE + + mby‹ +; + +7372 + mIO_BYTE + :1; + +7373 +IO_BYTE + + m_D6 + :1; + +7374 + mIO_BYTE + :1; + +7375 + mIO_BYTE + :1; + +7376 + mIO_BYTE + :1; + +7377 +IO_BYTE + + m_D2 + :1; + +7378 + mIO_BYTE + :1; + +7379 + mIO_BYTE + :1; + +7380 } + mb™ +; + +7381 } + tPDRD18STR +; + +7383 +IO_BYTE + + mby‹ +; + +7385 + mIO_BYTE + :1; + +7386 +IO_BYTE + + m_D6 + :1; + +7387 + mIO_BYTE + :1; + +7388 + mIO_BYTE + :1; + +7389 + mIO_BYTE + :1; + +7390 +IO_BYTE + + m_D2 + :1; + +7391 +IO_BYTE + + m_D1 + :1; + +7392 +IO_BYTE + + m_D0 + :1; + +7393 } + mb™ +; + +7394 } + tPDRD19STR +; + +7396 +IO_BYTE + + mby‹ +; + +7398 +IO_BYTE + + m_D7 + :1; + +7399 +IO_BYTE + + m_D6 + :1; + +7400 +IO_BYTE + + m_D5 + :1; + +7401 +IO_BYTE + + m_D4 + :1; + +7402 +IO_BYTE + + m_D3 + :1; + +7403 +IO_BYTE + + m_D2 + :1; + +7404 +IO_BYTE + + m_D1 + :1; + +7405 +IO_BYTE + + m_D0 + :1; + +7406 } + mb™ +; + +7407 } + tPDRD20STR +; + +7409 +IO_BYTE + + mby‹ +; + +7411 +IO_BYTE + + m_D7 + :1; + +7412 +IO_BYTE + + m_D6 + :1; + +7413 +IO_BYTE + + m_D5 + :1; + +7414 +IO_BYTE + + m_D4 + :1; + +7415 +IO_BYTE + + m_D3 + :1; + +7416 +IO_BYTE + + m_D2 + :1; + +7417 +IO_BYTE + + m_D1 + :1; + +7418 +IO_BYTE + + m_D0 + :1; + +7419 } + mb™ +; + +7420 } + tPDRD21STR +; + +7422 +IO_BYTE + + mby‹ +; + +7424 + mIO_BYTE + :1; + +7425 + mIO_BYTE + :1; + +7426 +IO_BYTE + + m_D5 + :1; + +7427 +IO_BYTE + + m_D4 + :1; + +7428 + mIO_BYTE + :1; + +7429 + mIO_BYTE + :1; + +7430 +IO_BYTE + + m_D1 + :1; + +7431 +IO_BYTE + + m_D0 + :1; + +7432 } + mb™ +; + +7433 } + tPDRD22STR +; + +7435 +IO_BYTE + + mby‹ +; + +7437 +IO_BYTE + + m_D7 + :1; + +7438 +IO_BYTE + + m_D6 + :1; + +7439 +IO_BYTE + + m_D5 + :1; + +7440 +IO_BYTE + + m_D4 + :1; + +7441 +IO_BYTE + + m_D3 + :1; + +7442 +IO_BYTE + + m_D2 + :1; + +7443 +IO_BYTE + + m_D1 + :1; + +7444 +IO_BYTE + + m_D0 + :1; + +7445 } + mb™ +; + +7446 } + tPDRD24STR +; + +7448 +IO_BYTE + + mby‹ +; + +7450 + mIO_BYTE + :1; + +7451 + mIO_BYTE + :1; + +7452 + mIO_BYTE + :1; + +7453 + mIO_BYTE + :1; + +7454 + mIO_BYTE + :1; + +7455 + mIO_BYTE + :1; + +7456 +IO_BYTE + + m_D1 + :1; + +7457 +IO_BYTE + + m_D0 + :1; + +7458 } + mb™ +; + +7459 } + tPDRD26STR +; + +7461 +IO_BYTE + + mby‹ +; + +7463 +IO_BYTE + + m_D7 + :1; + +7464 +IO_BYTE + + m_D6 + :1; + +7465 +IO_BYTE + + m_D5 + :1; + +7466 +IO_BYTE + + m_D4 + :1; + +7467 +IO_BYTE + + m_D3 + :1; + +7468 +IO_BYTE + + m_D2 + :1; + +7469 +IO_BYTE + + m_D1 + :1; + +7470 +IO_BYTE + + m_D0 + :1; + +7471 } + mb™ +; + +7472 } + tPDRD27STR +; + +7474 +IO_BYTE + + mby‹ +; + +7476 +IO_BYTE + + m_D7 + :1; + +7477 +IO_BYTE + + m_D6 + :1; + +7478 +IO_BYTE + + m_D5 + :1; + +7479 +IO_BYTE + + m_D4 + :1; + +7480 +IO_BYTE + + m_D3 + :1; + +7481 +IO_BYTE + + m_D2 + :1; + +7482 +IO_BYTE + + m_D1 + :1; + +7483 +IO_BYTE + + m_D0 + :1; + +7484 } + mb™ +; + +7485 } + tPDRD28STR +; + +7487 +IO_BYTE + + mby‹ +; + +7489 +IO_BYTE + + m_D7 + :1; + +7490 +IO_BYTE + + m_D6 + :1; + +7491 +IO_BYTE + + m_D5 + :1; + +7492 +IO_BYTE + + m_D4 + :1; + +7493 +IO_BYTE + + m_D3 + :1; + +7494 +IO_BYTE + + m_D2 + :1; + +7495 +IO_BYTE + + m_D1 + :1; + +7496 +IO_BYTE + + m_D0 + :1; + +7497 } + mb™ +; + +7498 } + tPDRD29STR +; + +7500 +IO_BYTE + + mby‹ +; + +7502 +IO_BYTE + + m_D7 + :1; + +7503 +IO_BYTE + + m_D6 + :1; + +7504 +IO_BYTE + + m_D5 + :1; + +7505 +IO_BYTE + + m_D4 + :1; + +7506 +IO_BYTE + + m_D3 + :1; + +7507 +IO_BYTE + + m_D2 + :1; + +7508 +IO_BYTE + + m_D1 + :1; + +7509 +IO_BYTE + + m_D0 + :1; + +7510 } + mb™ +; + +7511 } + tDDR14STR +; + +7513 +IO_BYTE + + mby‹ +; + +7515 +IO_BYTE + + m_D7 + :1; + +7516 +IO_BYTE + + m_D6 + :1; + +7517 +IO_BYTE + + m_D5 + :1; + +7518 +IO_BYTE + + m_D4 + :1; + +7519 +IO_BYTE + + m_D3 + :1; + +7520 +IO_BYTE + + m_D2 + :1; + +7521 +IO_BYTE + + m_D1 + :1; + +7522 +IO_BYTE + + m_D0 + :1; + +7523 } + mb™ +; + +7524 } + tDDR15STR +; + +7526 +IO_BYTE + + mby‹ +; + +7528 +IO_BYTE + + m_D7 + :1; + +7529 +IO_BYTE + + m_D6 + :1; + +7530 +IO_BYTE + + m_D5 + :1; + +7531 +IO_BYTE + + m_D4 + :1; + +7532 +IO_BYTE + + m_D3 + :1; + +7533 +IO_BYTE + + m_D2 + :1; + +7534 +IO_BYTE + + m_D1 + :1; + +7535 +IO_BYTE + + m_D0 + :1; + +7536 } + mb™ +; + +7537 } + tDDR16STR +; + +7539 +IO_BYTE + + mby‹ +; + +7541 +IO_BYTE + + m_D7 + :1; + +7542 +IO_BYTE + + m_D6 + :1; + +7543 +IO_BYTE + + m_D5 + :1; + +7544 +IO_BYTE + + m_D4 + :1; + +7545 +IO_BYTE + + m_D3 + :1; + +7546 +IO_BYTE + + m_D2 + :1; + +7547 +IO_BYTE + + m_D1 + :1; + +7548 +IO_BYTE + + m_D0 + :1; + +7549 } + mb™ +; + +7550 } + tDDR17STR +; + +7552 +IO_BYTE + + mby‹ +; + +7554 + mIO_BYTE + :1; + +7555 +IO_BYTE + + m_D6 + :1; + +7556 + mIO_BYTE + :1; + +7557 + mIO_BYTE + :1; + +7558 + mIO_BYTE + :1; + +7559 +IO_BYTE + + m_D2 + :1; + +7560 + mIO_BYTE + :1; + +7561 + mIO_BYTE + :1; + +7562 } + mb™ +; + +7563 } + tDDR18STR +; + +7565 +IO_BYTE + + mby‹ +; + +7567 + mIO_BYTE + :1; + +7568 +IO_BYTE + + m_D6 + :1; + +7569 + mIO_BYTE + :1; + +7570 + mIO_BYTE + :1; + +7571 + mIO_BYTE + :1; + +7572 +IO_BYTE + + m_D2 + :1; + +7573 +IO_BYTE + + m_D1 + :1; + +7574 +IO_BYTE + + m_D0 + :1; + +7575 } + mb™ +; + +7576 } + tDDR19STR +; + +7578 +IO_BYTE + + mby‹ +; + +7580 +IO_BYTE + + m_D7 + :1; + +7581 +IO_BYTE + + m_D6 + :1; + +7582 +IO_BYTE + + m_D5 + :1; + +7583 +IO_BYTE + + m_D4 + :1; + +7584 +IO_BYTE + + m_D3 + :1; + +7585 +IO_BYTE + + m_D2 + :1; + +7586 +IO_BYTE + + m_D1 + :1; + +7587 +IO_BYTE + + m_D0 + :1; + +7588 } + mb™ +; + +7589 } + tDDR20STR +; + +7591 +IO_BYTE + + mby‹ +; + +7593 +IO_BYTE + + m_D7 + :1; + +7594 +IO_BYTE + + m_D6 + :1; + +7595 +IO_BYTE + + m_D5 + :1; + +7596 +IO_BYTE + + m_D4 + :1; + +7597 +IO_BYTE + + m_D3 + :1; + +7598 +IO_BYTE + + m_D2 + :1; + +7599 +IO_BYTE + + m_D1 + :1; + +7600 +IO_BYTE + + m_D0 + :1; + +7601 } + mb™ +; + +7602 } + tDDR21STR +; + +7604 +IO_BYTE + + mby‹ +; + +7606 + mIO_BYTE + :1; + +7607 + mIO_BYTE + :1; + +7608 +IO_BYTE + + m_D5 + :1; + +7609 +IO_BYTE + + m_D4 + :1; + +7610 + mIO_BYTE + :1; + +7611 + mIO_BYTE + :1; + +7612 +IO_BYTE + + m_D1 + :1; + +7613 +IO_BYTE + + m_D0 + :1; + +7614 } + mb™ +; + +7615 } + tDDR22STR +; + +7617 +IO_BYTE + + mby‹ +; + +7619 +IO_BYTE + + m_D7 + :1; + +7620 +IO_BYTE + + m_D6 + :1; + +7621 +IO_BYTE + + m_D5 + :1; + +7622 +IO_BYTE + + m_D4 + :1; + +7623 +IO_BYTE + + m_D3 + :1; + +7624 +IO_BYTE + + m_D2 + :1; + +7625 +IO_BYTE + + m_D1 + :1; + +7626 +IO_BYTE + + m_D0 + :1; + +7627 } + mb™ +; + +7628 } + tDDR24STR +; + +7630 +IO_BYTE + + mby‹ +; + +7632 + mIO_BYTE + :1; + +7633 + mIO_BYTE + :1; + +7634 + mIO_BYTE + :1; + +7635 + mIO_BYTE + :1; + +7636 + mIO_BYTE + :1; + +7637 + mIO_BYTE + :1; + +7638 +IO_BYTE + + m_D1 + :1; + +7639 +IO_BYTE + + m_D0 + :1; + +7640 } + mb™ +; + +7641 } + tDDR26STR +; + +7643 +IO_BYTE + + mby‹ +; + +7645 +IO_BYTE + + m_D7 + :1; + +7646 +IO_BYTE + + m_D6 + :1; + +7647 +IO_BYTE + + m_D5 + :1; + +7648 +IO_BYTE + + m_D4 + :1; + +7649 +IO_BYTE + + m_D3 + :1; + +7650 +IO_BYTE + + m_D2 + :1; + +7651 +IO_BYTE + + m_D1 + :1; + +7652 +IO_BYTE + + m_D0 + :1; + +7653 } + mb™ +; + +7654 } + tDDR27STR +; + +7656 +IO_BYTE + + mby‹ +; + +7658 +IO_BYTE + + m_D7 + :1; + +7659 +IO_BYTE + + m_D6 + :1; + +7660 +IO_BYTE + + m_D5 + :1; + +7661 +IO_BYTE + + m_D4 + :1; + +7662 +IO_BYTE + + m_D3 + :1; + +7663 +IO_BYTE + + m_D2 + :1; + +7664 +IO_BYTE + + m_D1 + :1; + +7665 +IO_BYTE + + m_D0 + :1; + +7666 } + mb™ +; + +7667 } + tDDR28STR +; + +7669 +IO_BYTE + + mby‹ +; + +7671 +IO_BYTE + + m_D7 + :1; + +7672 +IO_BYTE + + m_D6 + :1; + +7673 +IO_BYTE + + m_D5 + :1; + +7674 +IO_BYTE + + m_D4 + :1; + +7675 +IO_BYTE + + m_D3 + :1; + +7676 +IO_BYTE + + m_D2 + :1; + +7677 +IO_BYTE + + m_D1 + :1; + +7678 +IO_BYTE + + m_D0 + :1; + +7679 } + mb™ +; + +7680 } + tDDR29STR +; + +7682 +IO_BYTE + + mby‹ +; + +7684 +IO_BYTE + + m_D7 + :1; + +7685 +IO_BYTE + + m_D6 + :1; + +7686 +IO_BYTE + + m_D5 + :1; + +7687 +IO_BYTE + + m_D4 + :1; + +7688 +IO_BYTE + + m_D3 + :1; + +7689 +IO_BYTE + + m_D2 + :1; + +7690 +IO_BYTE + + m_D1 + :1; + +7691 +IO_BYTE + + m_D0 + :1; + +7692 } + mb™ +; + +7693 } + tPFR14STR +; + +7695 +IO_BYTE + + mby‹ +; + +7697 +IO_BYTE + + m_D7 + :1; + +7698 +IO_BYTE + + m_D6 + :1; + +7699 +IO_BYTE + + m_D5 + :1; + +7700 +IO_BYTE + + m_D4 + :1; + +7701 +IO_BYTE + + m_D3 + :1; + +7702 +IO_BYTE + + m_D2 + :1; + +7703 +IO_BYTE + + m_D1 + :1; + +7704 +IO_BYTE + + m_D0 + :1; + +7705 } + mb™ +; + +7706 } + tPFR15STR +; + +7708 +IO_BYTE + + mby‹ +; + +7710 +IO_BYTE + + m_D7 + :1; + +7711 +IO_BYTE + + m_D6 + :1; + +7712 +IO_BYTE + + m_D5 + :1; + +7713 +IO_BYTE + + m_D4 + :1; + +7714 +IO_BYTE + + m_D3 + :1; + +7715 +IO_BYTE + + m_D2 + :1; + +7716 +IO_BYTE + + m_D1 + :1; + +7717 +IO_BYTE + + m_D0 + :1; + +7718 } + mb™ +; + +7719 } + tPFR16STR +; + +7721 +IO_BYTE + + mby‹ +; + +7723 +IO_BYTE + + m_D7 + :1; + +7724 +IO_BYTE + + m_D6 + :1; + +7725 +IO_BYTE + + m_D5 + :1; + +7726 +IO_BYTE + + m_D4 + :1; + +7727 +IO_BYTE + + m_D3 + :1; + +7728 +IO_BYTE + + m_D2 + :1; + +7729 +IO_BYTE + + m_D1 + :1; + +7730 +IO_BYTE + + m_D0 + :1; + +7731 } + mb™ +; + +7732 } + tPFR17STR +; + +7734 +IO_BYTE + + mby‹ +; + +7736 + mIO_BYTE + :1; + +7737 +IO_BYTE + + m_D6 + :1; + +7738 + mIO_BYTE + :1; + +7739 + mIO_BYTE + :1; + +7740 + mIO_BYTE + :1; + +7741 +IO_BYTE + + m_D2 + :1; + +7742 + mIO_BYTE + :1; + +7743 + mIO_BYTE + :1; + +7744 } + mb™ +; + +7745 } + tPFR18STR +; + +7747 +IO_BYTE + + mby‹ +; + +7749 + mIO_BYTE + :1; + +7750 +IO_BYTE + + m_D6 + :1; + +7751 + mIO_BYTE + :1; + +7752 + mIO_BYTE + :1; + +7753 + mIO_BYTE + :1; + +7754 +IO_BYTE + + m_D2 + :1; + +7755 +IO_BYTE + + m_D1 + :1; + +7756 +IO_BYTE + + m_D0 + :1; + +7757 } + mb™ +; + +7758 } + tPFR19STR +; + +7760 +IO_BYTE + + mby‹ +; + +7762 +IO_BYTE + + m_D7 + :1; + +7763 +IO_BYTE + + m_D6 + :1; + +7764 +IO_BYTE + + m_D5 + :1; + +7765 +IO_BYTE + + m_D4 + :1; + +7766 +IO_BYTE + + m_D3 + :1; + +7767 +IO_BYTE + + m_D2 + :1; + +7768 +IO_BYTE + + m_D1 + :1; + +7769 +IO_BYTE + + m_D0 + :1; + +7770 } + mb™ +; + +7771 } + tPFR20STR +; + +7773 +IO_BYTE + + mby‹ +; + +7775 +IO_BYTE + + m_D7 + :1; + +7776 +IO_BYTE + + m_D6 + :1; + +7777 +IO_BYTE + + m_D5 + :1; + +7778 +IO_BYTE + + m_D4 + :1; + +7779 +IO_BYTE + + m_D3 + :1; + +7780 +IO_BYTE + + m_D2 + :1; + +7781 +IO_BYTE + + m_D1 + :1; + +7782 +IO_BYTE + + m_D0 + :1; + +7783 } + mb™ +; + +7784 } + tPFR21STR +; + +7786 +IO_BYTE + + mby‹ +; + +7788 + mIO_BYTE + :1; + +7789 + mIO_BYTE + :1; + +7790 +IO_BYTE + + m_D5 + :1; + +7791 +IO_BYTE + + m_D4 + :1; + +7792 + mIO_BYTE + :1; + +7793 + mIO_BYTE + :1; + +7794 +IO_BYTE + + m_D1 + :1; + +7795 +IO_BYTE + + m_D0 + :1; + +7796 } + mb™ +; + +7797 } + tPFR22STR +; + +7799 +IO_BYTE + + mby‹ +; + +7801 +IO_BYTE + + m_D7 + :1; + +7802 +IO_BYTE + + m_D6 + :1; + +7803 +IO_BYTE + + m_D5 + :1; + +7804 +IO_BYTE + + m_D4 + :1; + +7805 +IO_BYTE + + m_D3 + :1; + +7806 +IO_BYTE + + m_D2 + :1; + +7807 +IO_BYTE + + m_D1 + :1; + +7808 +IO_BYTE + + m_D0 + :1; + +7809 } + mb™ +; + +7810 } + tPFR24STR +; + +7812 +IO_BYTE + + mby‹ +; + +7814 + mIO_BYTE + :1; + +7815 + mIO_BYTE + :1; + +7816 + mIO_BYTE + :1; + +7817 + mIO_BYTE + :1; + +7818 + mIO_BYTE + :1; + +7819 + mIO_BYTE + :1; + +7820 +IO_BYTE + + m_D1 + :1; + +7821 +IO_BYTE + + m_D0 + :1; + +7822 } + mb™ +; + +7823 } + tPFR26STR +; + +7825 +IO_BYTE + + mby‹ +; + +7827 +IO_BYTE + + m_D7 + :1; + +7828 +IO_BYTE + + m_D6 + :1; + +7829 +IO_BYTE + + m_D5 + :1; + +7830 +IO_BYTE + + m_D4 + :1; + +7831 +IO_BYTE + + m_D3 + :1; + +7832 +IO_BYTE + + m_D2 + :1; + +7833 +IO_BYTE + + m_D1 + :1; + +7834 +IO_BYTE + + m_D0 + :1; + +7835 } + mb™ +; + +7836 } + tPFR27STR +; + +7838 +IO_BYTE + + mby‹ +; + +7840 +IO_BYTE + + m_D7 + :1; + +7841 +IO_BYTE + + m_D6 + :1; + +7842 +IO_BYTE + + m_D5 + :1; + +7843 +IO_BYTE + + m_D4 + :1; + +7844 +IO_BYTE + + m_D3 + :1; + +7845 +IO_BYTE + + m_D2 + :1; + +7846 +IO_BYTE + + m_D1 + :1; + +7847 +IO_BYTE + + m_D0 + :1; + +7848 } + mb™ +; + +7849 } + tPFR28STR +; + +7851 +IO_BYTE + + mby‹ +; + +7853 +IO_BYTE + + m_D7 + :1; + +7854 +IO_BYTE + + m_D6 + :1; + +7855 +IO_BYTE + + m_D5 + :1; + +7856 +IO_BYTE + + m_D4 + :1; + +7857 +IO_BYTE + + m_D3 + :1; + +7858 +IO_BYTE + + m_D2 + :1; + +7859 +IO_BYTE + + m_D1 + :1; + +7860 +IO_BYTE + + m_D0 + :1; + +7861 } + mb™ +; + +7862 } + tPFR29STR +; + +7864 +IO_BYTE + + mby‹ +; + +7866 +IO_BYTE + + m_D7 + :1; + +7867 +IO_BYTE + + m_D6 + :1; + +7868 +IO_BYTE + + m_D5 + :1; + +7869 +IO_BYTE + + m_D4 + :1; + +7870 +IO_BYTE + + m_D3 + :1; + +7871 +IO_BYTE + + m_D2 + :1; + +7872 +IO_BYTE + + m_D1 + :1; + +7873 +IO_BYTE + + m_D0 + :1; + +7874 } + mb™ +; + +7875 } + tEPFR14STR +; + +7877 +IO_BYTE + + mby‹ +; + +7879 +IO_BYTE + + m_D7 + :1; + +7880 +IO_BYTE + + m_D6 + :1; + +7881 +IO_BYTE + + m_D5 + :1; + +7882 +IO_BYTE + + m_D4 + :1; + +7883 +IO_BYTE + + m_D3 + :1; + +7884 +IO_BYTE + + m_D2 + :1; + +7885 +IO_BYTE + + m_D1 + :1; + +7886 +IO_BYTE + + m_D0 + :1; + +7887 } + mb™ +; + +7888 } + tEPFR15STR +; + +7890 +IO_BYTE + + mby‹ +; + +7892 +IO_BYTE + + m_D7 + :1; + +7893 + mIO_BYTE + :1; + +7894 + mIO_BYTE + :1; + +7895 + mIO_BYTE + :1; + +7896 + mIO_BYTE + :1; + +7897 + mIO_BYTE + :1; + +7898 + mIO_BYTE + :1; + +7899 + mIO_BYTE + :1; + +7900 } + mb™ +; + +7901 } + tEPFR16STR +; + +7903 +IO_BYTE + + mby‹ +; + +7905 + mIO_BYTE + :1; + +7906 +IO_BYTE + + m_D6 + :1; + +7907 + mIO_BYTE + :1; + +7908 + mIO_BYTE + :1; + +7909 + mIO_BYTE + :1; + +7910 +IO_BYTE + + m_D2 + :1; + +7911 + mIO_BYTE + :1; + +7912 + mIO_BYTE + :1; + +7913 } + mb™ +; + +7914 } + tEPFR18STR +; + +7916 +IO_BYTE + + mby‹ +; + +7918 + mIO_BYTE + :1; + +7919 +IO_BYTE + + m_D6 + :1; + +7920 + mIO_BYTE + :1; + +7921 + mIO_BYTE + :1; + +7922 + mIO_BYTE + :1; + +7923 +IO_BYTE + + m_D2 + :1; + +7924 + mIO_BYTE + :1; + +7925 + mIO_BYTE + :1; + +7926 } + mb™ +; + +7927 } + tEPFR19STR +; + +7929 +IO_BYTE + + mby‹ +; + +7931 + mIO_BYTE + :1; + +7932 +IO_BYTE + + m_D6 + :1; + +7933 + mIO_BYTE + :1; + +7934 + mIO_BYTE + :1; + +7935 + mIO_BYTE + :1; + +7936 +IO_BYTE + + m_D2 + :1; + +7937 + mIO_BYTE + :1; + +7938 + mIO_BYTE + :1; + +7939 } + mb™ +; + +7940 } + tEPFR20STR +; + +7942 +IO_BYTE + + mby‹ +; + +7944 + mIO_BYTE + :1; + +7945 +IO_BYTE + + m_D6 + :1; + +7946 + mIO_BYTE + :1; + +7947 + mIO_BYTE + :1; + +7948 + mIO_BYTE + :1; + +7949 +IO_BYTE + + m_D2 + :1; + +7950 + mIO_BYTE + :1; + +7951 + mIO_BYTE + :1; + +7952 } + mb™ +; + +7953 } + tEPFR21STR +; + +7955 +IO_BYTE + + mby‹ +; + +7957 + mIO_BYTE + :1; + +7958 + mIO_BYTE + :1; + +7959 + mIO_BYTE + :1; + +7960 + mIO_BYTE + :1; + +7961 + mIO_BYTE + :1; + +7962 + mIO_BYTE + :1; + +7963 +IO_BYTE + + m_D1 + :1; + +7964 +IO_BYTE + + m_D0 + :1; + +7965 } + mb™ +; + +7966 } + tEPFR26STR +; + +7968 +IO_BYTE + + mby‹ +; + +7970 +IO_BYTE + + m_D7 + :1; + +7971 +IO_BYTE + + m_D6 + :1; + +7972 +IO_BYTE + + m_D5 + :1; + +7973 +IO_BYTE + + m_D4 + :1; + +7974 +IO_BYTE + + m_D3 + :1; + +7975 +IO_BYTE + + m_D2 + :1; + +7976 +IO_BYTE + + m_D1 + :1; + +7977 +IO_BYTE + + m_D0 + :1; + +7978 } + mb™ +; + +7979 } + tEPFR27STR +; + +7981 +IO_BYTE + + mby‹ +; + +7983 +IO_BYTE + + m_D7 + :1; + +7984 +IO_BYTE + + m_D6 + :1; + +7985 +IO_BYTE + + m_D5 + :1; + +7986 +IO_BYTE + + m_D4 + :1; + +7987 +IO_BYTE + + m_D3 + :1; + +7988 +IO_BYTE + + m_D2 + :1; + +7989 +IO_BYTE + + m_D1 + :1; + +7990 +IO_BYTE + + m_D0 + :1; + +7991 } + mb™ +; + +7992 } + tPODR14STR +; + +7994 +IO_BYTE + + mby‹ +; + +7996 +IO_BYTE + + m_D7 + :1; + +7997 +IO_BYTE + + m_D6 + :1; + +7998 +IO_BYTE + + m_D5 + :1; + +7999 +IO_BYTE + + m_D4 + :1; + +8000 +IO_BYTE + + m_D3 + :1; + +8001 +IO_BYTE + + m_D2 + :1; + +8002 +IO_BYTE + + m_D1 + :1; + +8003 +IO_BYTE + + m_D0 + :1; + +8004 } + mb™ +; + +8005 } + tPODR15STR +; + +8007 +IO_BYTE + + mby‹ +; + +8009 +IO_BYTE + + m_D7 + :1; + +8010 +IO_BYTE + + m_D6 + :1; + +8011 +IO_BYTE + + m_D5 + :1; + +8012 +IO_BYTE + + m_D4 + :1; + +8013 +IO_BYTE + + m_D3 + :1; + +8014 +IO_BYTE + + m_D2 + :1; + +8015 +IO_BYTE + + m_D1 + :1; + +8016 +IO_BYTE + + m_D0 + :1; + +8017 } + mb™ +; + +8018 } + tPODR16STR +; + +8020 +IO_BYTE + + mby‹ +; + +8022 +IO_BYTE + + m_D7 + :1; + +8023 +IO_BYTE + + m_D6 + :1; + +8024 +IO_BYTE + + m_D5 + :1; + +8025 +IO_BYTE + + m_D4 + :1; + +8026 +IO_BYTE + + m_D3 + :1; + +8027 +IO_BYTE + + m_D2 + :1; + +8028 +IO_BYTE + + m_D1 + :1; + +8029 +IO_BYTE + + m_D0 + :1; + +8030 } + mb™ +; + +8031 } + tPODR17STR +; + +8033 +IO_BYTE + + mby‹ +; + +8035 + mIO_BYTE + :1; + +8036 +IO_BYTE + + m_D6 + :1; + +8037 + mIO_BYTE + :1; + +8038 + mIO_BYTE + :1; + +8039 + mIO_BYTE + :1; + +8040 +IO_BYTE + + m_D2 + :1; + +8041 + mIO_BYTE + :1; + +8042 + mIO_BYTE + :1; + +8043 } + mb™ +; + +8044 } + tPODR18STR +; + +8046 +IO_BYTE + + mby‹ +; + +8048 + mIO_BYTE + :1; + +8049 +IO_BYTE + + m_D6 + :1; + +8050 + mIO_BYTE + :1; + +8051 + mIO_BYTE + :1; + +8052 + mIO_BYTE + :1; + +8053 +IO_BYTE + + m_D2 + :1; + +8054 +IO_BYTE + + m_D1 + :1; + +8055 +IO_BYTE + + m_D0 + :1; + +8056 } + mb™ +; + +8057 } + tPODR19STR +; + +8059 +IO_BYTE + + mby‹ +; + +8061 +IO_BYTE + + m_D7 + :1; + +8062 +IO_BYTE + + m_D6 + :1; + +8063 +IO_BYTE + + m_D5 + :1; + +8064 +IO_BYTE + + m_D4 + :1; + +8065 +IO_BYTE + + m_D3 + :1; + +8066 +IO_BYTE + + m_D2 + :1; + +8067 +IO_BYTE + + m_D1 + :1; + +8068 +IO_BYTE + + m_D0 + :1; + +8069 } + mb™ +; + +8070 } + tPODR20STR +; + +8072 +IO_BYTE + + mby‹ +; + +8074 +IO_BYTE + + m_D7 + :1; + +8075 +IO_BYTE + + m_D6 + :1; + +8076 +IO_BYTE + + m_D5 + :1; + +8077 +IO_BYTE + + m_D4 + :1; + +8078 +IO_BYTE + + m_D3 + :1; + +8079 +IO_BYTE + + m_D2 + :1; + +8080 +IO_BYTE + + m_D1 + :1; + +8081 +IO_BYTE + + m_D0 + :1; + +8082 } + mb™ +; + +8083 } + tPODR21STR +; + +8085 +IO_BYTE + + mby‹ +; + +8087 + mIO_BYTE + :1; + +8088 + mIO_BYTE + :1; + +8089 +IO_BYTE + + m_D5 + :1; + +8090 +IO_BYTE + + m_D4 + :1; + +8091 + mIO_BYTE + :1; + +8092 + mIO_BYTE + :1; + +8093 +IO_BYTE + + m_D1 + :1; + +8094 +IO_BYTE + + m_D0 + :1; + +8095 } + mb™ +; + +8096 } + tPODR22STR +; + +8098 +IO_BYTE + + mby‹ +; + +8100 +IO_BYTE + + m_D7 + :1; + +8101 +IO_BYTE + + m_D6 + :1; + +8102 +IO_BYTE + + m_D5 + :1; + +8103 +IO_BYTE + + m_D4 + :1; + +8104 +IO_BYTE + + m_D3 + :1; + +8105 +IO_BYTE + + m_D2 + :1; + +8106 +IO_BYTE + + m_D1 + :1; + +8107 +IO_BYTE + + m_D0 + :1; + +8108 } + mb™ +; + +8109 } + tPODR24STR +; + +8111 +IO_BYTE + + mby‹ +; + +8113 + mIO_BYTE + :1; + +8114 + mIO_BYTE + :1; + +8115 + mIO_BYTE + :1; + +8116 + mIO_BYTE + :1; + +8117 + mIO_BYTE + :1; + +8118 + mIO_BYTE + :1; + +8119 +IO_BYTE + + m_D1 + :1; + +8120 +IO_BYTE + + m_D0 + :1; + +8121 } + mb™ +; + +8122 } + tPODR26STR +; + +8124 +IO_BYTE + + mby‹ +; + +8126 +IO_BYTE + + m_D7 + :1; + +8127 +IO_BYTE + + m_D6 + :1; + +8128 +IO_BYTE + + m_D5 + :1; + +8129 +IO_BYTE + + m_D4 + :1; + +8130 +IO_BYTE + + m_D3 + :1; + +8131 +IO_BYTE + + m_D2 + :1; + +8132 +IO_BYTE + + m_D1 + :1; + +8133 +IO_BYTE + + m_D0 + :1; + +8134 } + mb™ +; + +8135 } + tPODR27STR +; + +8137 +IO_BYTE + + mby‹ +; + +8139 +IO_BYTE + + m_D7 + :1; + +8140 +IO_BYTE + + m_D6 + :1; + +8141 +IO_BYTE + + m_D5 + :1; + +8142 +IO_BYTE + + m_D4 + :1; + +8143 +IO_BYTE + + m_D3 + :1; + +8144 +IO_BYTE + + m_D2 + :1; + +8145 +IO_BYTE + + m_D1 + :1; + +8146 +IO_BYTE + + m_D0 + :1; + +8147 } + mb™ +; + +8148 } + tPODR28STR +; + +8150 +IO_BYTE + + mby‹ +; + +8152 +IO_BYTE + + m_D7 + :1; + +8153 +IO_BYTE + + m_D6 + :1; + +8154 +IO_BYTE + + m_D5 + :1; + +8155 +IO_BYTE + + m_D4 + :1; + +8156 +IO_BYTE + + m_D3 + :1; + +8157 +IO_BYTE + + m_D2 + :1; + +8158 +IO_BYTE + + m_D1 + :1; + +8159 +IO_BYTE + + m_D0 + :1; + +8160 } + mb™ +; + +8161 } + tPODR29STR +; + +8163 +IO_BYTE + + mby‹ +; + +8165 +IO_BYTE + + m_D7 + :1; + +8166 +IO_BYTE + + m_D6 + :1; + +8167 +IO_BYTE + + m_D5 + :1; + +8168 +IO_BYTE + + m_D4 + :1; + +8169 +IO_BYTE + + m_D3 + :1; + +8170 +IO_BYTE + + m_D2 + :1; + +8171 +IO_BYTE + + m_D1 + :1; + +8172 +IO_BYTE + + m_D0 + :1; + +8173 } + mb™ +; + +8174 } + tPILR14STR +; + +8176 +IO_BYTE + + mby‹ +; + +8178 +IO_BYTE + + m_D7 + :1; + +8179 +IO_BYTE + + m_D6 + :1; + +8180 +IO_BYTE + + m_D5 + :1; + +8181 +IO_BYTE + + m_D4 + :1; + +8182 +IO_BYTE + + m_D3 + :1; + +8183 +IO_BYTE + + m_D2 + :1; + +8184 +IO_BYTE + + m_D1 + :1; + +8185 +IO_BYTE + + m_D0 + :1; + +8186 } + mb™ +; + +8187 } + tPILR15STR +; + +8189 +IO_BYTE + + mby‹ +; + +8191 +IO_BYTE + + m_D7 + :1; + +8192 +IO_BYTE + + m_D6 + :1; + +8193 +IO_BYTE + + m_D5 + :1; + +8194 +IO_BYTE + + m_D4 + :1; + +8195 +IO_BYTE + + m_D3 + :1; + +8196 +IO_BYTE + + m_D2 + :1; + +8197 +IO_BYTE + + m_D1 + :1; + +8198 +IO_BYTE + + m_D0 + :1; + +8199 } + mb™ +; + +8200 } + tPILR16STR +; + +8202 +IO_BYTE + + mby‹ +; + +8204 +IO_BYTE + + m_D7 + :1; + +8205 +IO_BYTE + + m_D6 + :1; + +8206 +IO_BYTE + + m_D5 + :1; + +8207 +IO_BYTE + + m_D4 + :1; + +8208 +IO_BYTE + + m_D3 + :1; + +8209 +IO_BYTE + + m_D2 + :1; + +8210 +IO_BYTE + + m_D1 + :1; + +8211 +IO_BYTE + + m_D0 + :1; + +8212 } + mb™ +; + +8213 } + tPILR17STR +; + +8215 +IO_BYTE + + mby‹ +; + +8217 + mIO_BYTE + :1; + +8218 +IO_BYTE + + m_D6 + :1; + +8219 + mIO_BYTE + :1; + +8220 + mIO_BYTE + :1; + +8221 + mIO_BYTE + :1; + +8222 +IO_BYTE + + m_D2 + :1; + +8223 + mIO_BYTE + :1; + +8224 + mIO_BYTE + :1; + +8225 } + mb™ +; + +8226 } + tPILR18STR +; + +8228 +IO_BYTE + + mby‹ +; + +8230 + mIO_BYTE + :1; + +8231 +IO_BYTE + + m_D6 + :1; + +8232 + mIO_BYTE + :1; + +8233 + mIO_BYTE + :1; + +8234 + mIO_BYTE + :1; + +8235 +IO_BYTE + + m_D2 + :1; + +8236 +IO_BYTE + + m_D1 + :1; + +8237 +IO_BYTE + + m_D0 + :1; + +8238 } + mb™ +; + +8239 } + tPILR19STR +; + +8241 +IO_BYTE + + mby‹ +; + +8243 +IO_BYTE + + m_D7 + :1; + +8244 +IO_BYTE + + m_D6 + :1; + +8245 +IO_BYTE + + m_D5 + :1; + +8246 +IO_BYTE + + m_D4 + :1; + +8247 +IO_BYTE + + m_D3 + :1; + +8248 +IO_BYTE + + m_D2 + :1; + +8249 +IO_BYTE + + m_D1 + :1; + +8250 +IO_BYTE + + m_D0 + :1; + +8251 } + mb™ +; + +8252 } + tPILR20STR +; + +8254 +IO_BYTE + + mby‹ +; + +8256 +IO_BYTE + + m_D7 + :1; + +8257 +IO_BYTE + + m_D6 + :1; + +8258 +IO_BYTE + + m_D5 + :1; + +8259 +IO_BYTE + + m_D4 + :1; + +8260 +IO_BYTE + + m_D3 + :1; + +8261 +IO_BYTE + + m_D2 + :1; + +8262 +IO_BYTE + + m_D1 + :1; + +8263 +IO_BYTE + + m_D0 + :1; + +8264 } + mb™ +; + +8265 } + tPILR21STR +; + +8267 +IO_BYTE + + mby‹ +; + +8269 + mIO_BYTE + :1; + +8270 + mIO_BYTE + :1; + +8271 +IO_BYTE + + m_D5 + :1; + +8272 +IO_BYTE + + m_D4 + :1; + +8273 + mIO_BYTE + :1; + +8274 + mIO_BYTE + :1; + +8275 +IO_BYTE + + m_D1 + :1; + +8276 +IO_BYTE + + m_D0 + :1; + +8277 } + mb™ +; + +8278 } + tPILR22STR +; + +8280 +IO_BYTE + + mby‹ +; + +8282 +IO_BYTE + + m_D7 + :1; + +8283 +IO_BYTE + + m_D6 + :1; + +8284 +IO_BYTE + + m_D5 + :1; + +8285 +IO_BYTE + + m_D4 + :1; + +8286 +IO_BYTE + + m_D3 + :1; + +8287 +IO_BYTE + + m_D2 + :1; + +8288 +IO_BYTE + + m_D1 + :1; + +8289 +IO_BYTE + + m_D0 + :1; + +8290 } + mb™ +; + +8291 } + tPILR24STR +; + +8293 +IO_BYTE + + mby‹ +; + +8295 + mIO_BYTE + :1; + +8296 + mIO_BYTE + :1; + +8297 + mIO_BYTE + :1; + +8298 + mIO_BYTE + :1; + +8299 + mIO_BYTE + :1; + +8300 + mIO_BYTE + :1; + +8301 +IO_BYTE + + m_D1 + :1; + +8302 +IO_BYTE + + m_D0 + :1; + +8303 } + mb™ +; + +8304 } + tPILR26STR +; + +8306 +IO_BYTE + + mby‹ +; + +8308 +IO_BYTE + + m_D7 + :1; + +8309 +IO_BYTE + + m_D6 + :1; + +8310 +IO_BYTE + + m_D5 + :1; + +8311 +IO_BYTE + + m_D4 + :1; + +8312 +IO_BYTE + + m_D3 + :1; + +8313 +IO_BYTE + + m_D2 + :1; + +8314 +IO_BYTE + + m_D1 + :1; + +8315 +IO_BYTE + + m_D0 + :1; + +8316 } + mb™ +; + +8317 } + tPILR27STR +; + +8319 +IO_BYTE + + mby‹ +; + +8321 +IO_BYTE + + m_D7 + :1; + +8322 +IO_BYTE + + m_D6 + :1; + +8323 +IO_BYTE + + m_D5 + :1; + +8324 +IO_BYTE + + m_D4 + :1; + +8325 +IO_BYTE + + m_D3 + :1; + +8326 +IO_BYTE + + m_D2 + :1; + +8327 +IO_BYTE + + m_D1 + :1; + +8328 +IO_BYTE + + m_D0 + :1; + +8329 } + mb™ +; + +8330 } + tPILR28STR +; + +8332 +IO_BYTE + + mby‹ +; + +8334 +IO_BYTE + + m_D7 + :1; + +8335 +IO_BYTE + + m_D6 + :1; + +8336 +IO_BYTE + + m_D5 + :1; + +8337 +IO_BYTE + + m_D4 + :1; + +8338 +IO_BYTE + + m_D3 + :1; + +8339 +IO_BYTE + + m_D2 + :1; + +8340 +IO_BYTE + + m_D1 + :1; + +8341 +IO_BYTE + + m_D0 + :1; + +8342 } + mb™ +; + +8343 } + tPILR29STR +; + +8345 +IO_BYTE + + mby‹ +; + +8347 +IO_BYTE + + m_D7 + :1; + +8348 +IO_BYTE + + m_D6 + :1; + +8349 +IO_BYTE + + m_D5 + :1; + +8350 +IO_BYTE + + m_D4 + :1; + +8351 +IO_BYTE + + m_D3 + :1; + +8352 +IO_BYTE + + m_D2 + :1; + +8353 +IO_BYTE + + m_D1 + :1; + +8354 +IO_BYTE + + m_D0 + :1; + +8355 } + mb™ +; + +8356 } + tEPILR14STR +; + +8358 +IO_BYTE + + mby‹ +; + +8360 +IO_BYTE + + m_D7 + :1; + +8361 +IO_BYTE + + m_D6 + :1; + +8362 +IO_BYTE + + m_D5 + :1; + +8363 +IO_BYTE + + m_D4 + :1; + +8364 +IO_BYTE + + m_D3 + :1; + +8365 +IO_BYTE + + m_D2 + :1; + +8366 +IO_BYTE + + m_D1 + :1; + +8367 +IO_BYTE + + m_D0 + :1; + +8368 } + mb™ +; + +8369 } + tEPILR15STR +; + +8371 +IO_BYTE + + mby‹ +; + +8373 +IO_BYTE + + m_D7 + :1; + +8374 +IO_BYTE + + m_D6 + :1; + +8375 +IO_BYTE + + m_D5 + :1; + +8376 +IO_BYTE + + m_D4 + :1; + +8377 +IO_BYTE + + m_D3 + :1; + +8378 +IO_BYTE + + m_D2 + :1; + +8379 +IO_BYTE + + m_D1 + :1; + +8380 +IO_BYTE + + m_D0 + :1; + +8381 } + mb™ +; + +8382 } + tEPILR16STR +; + +8384 +IO_BYTE + + mby‹ +; + +8386 +IO_BYTE + + m_D7 + :1; + +8387 +IO_BYTE + + m_D6 + :1; + +8388 +IO_BYTE + + m_D5 + :1; + +8389 +IO_BYTE + + m_D4 + :1; + +8390 +IO_BYTE + + m_D3 + :1; + +8391 +IO_BYTE + + m_D2 + :1; + +8392 +IO_BYTE + + m_D1 + :1; + +8393 +IO_BYTE + + m_D0 + :1; + +8394 } + mb™ +; + +8395 } + tEPILR17STR +; + +8397 +IO_BYTE + + mby‹ +; + +8399 + mIO_BYTE + :1; + +8400 +IO_BYTE + + m_D6 + :1; + +8401 + mIO_BYTE + :1; + +8402 + mIO_BYTE + :1; + +8403 + mIO_BYTE + :1; + +8404 +IO_BYTE + + m_D2 + :1; + +8405 + mIO_BYTE + :1; + +8406 + mIO_BYTE + :1; + +8407 } + mb™ +; + +8408 } + tEPILR18STR +; + +8410 +IO_BYTE + + mby‹ +; + +8412 + mIO_BYTE + :1; + +8413 +IO_BYTE + + m_D6 + :1; + +8414 + mIO_BYTE + :1; + +8415 + mIO_BYTE + :1; + +8416 + mIO_BYTE + :1; + +8417 +IO_BYTE + + m_D2 + :1; + +8418 +IO_BYTE + + m_D1 + :1; + +8419 +IO_BYTE + + m_D0 + :1; + +8420 } + mb™ +; + +8421 } + tEPILR19STR +; + +8423 +IO_BYTE + + mby‹ +; + +8425 +IO_BYTE + + m_D7 + :1; + +8426 +IO_BYTE + + m_D6 + :1; + +8427 +IO_BYTE + + m_D5 + :1; + +8428 +IO_BYTE + + m_D4 + :1; + +8429 +IO_BYTE + + m_D3 + :1; + +8430 +IO_BYTE + + m_D2 + :1; + +8431 +IO_BYTE + + m_D1 + :1; + +8432 +IO_BYTE + + m_D0 + :1; + +8433 } + mb™ +; + +8434 } + tEPILR20STR +; + +8436 +IO_BYTE + + mby‹ +; + +8438 +IO_BYTE + + m_D7 + :1; + +8439 +IO_BYTE + + m_D6 + :1; + +8440 +IO_BYTE + + m_D5 + :1; + +8441 +IO_BYTE + + m_D4 + :1; + +8442 +IO_BYTE + + m_D3 + :1; + +8443 +IO_BYTE + + m_D2 + :1; + +8444 +IO_BYTE + + m_D1 + :1; + +8445 +IO_BYTE + + m_D0 + :1; + +8446 } + mb™ +; + +8447 } + tEPILR21STR +; + +8449 +IO_BYTE + + mby‹ +; + +8451 + mIO_BYTE + :1; + +8452 + mIO_BYTE + :1; + +8453 +IO_BYTE + + m_D5 + :1; + +8454 +IO_BYTE + + m_D4 + :1; + +8455 + mIO_BYTE + :1; + +8456 + mIO_BYTE + :1; + +8457 +IO_BYTE + + m_D1 + :1; + +8458 +IO_BYTE + + m_D0 + :1; + +8459 } + mb™ +; + +8460 } + tEPILR22STR +; + +8462 +IO_BYTE + + mby‹ +; + +8464 +IO_BYTE + + m_D7 + :1; + +8465 +IO_BYTE + + m_D6 + :1; + +8466 +IO_BYTE + + m_D5 + :1; + +8467 +IO_BYTE + + m_D4 + :1; + +8468 +IO_BYTE + + m_D3 + :1; + +8469 +IO_BYTE + + m_D2 + :1; + +8470 +IO_BYTE + + m_D1 + :1; + +8471 +IO_BYTE + + m_D0 + :1; + +8472 } + mb™ +; + +8473 } + tEPILR24STR +; + +8475 +IO_BYTE + + mby‹ +; + +8477 + mIO_BYTE + :1; + +8478 + mIO_BYTE + :1; + +8479 + mIO_BYTE + :1; + +8480 + mIO_BYTE + :1; + +8481 + mIO_BYTE + :1; + +8482 + mIO_BYTE + :1; + +8483 +IO_BYTE + + m_D1 + :1; + +8484 +IO_BYTE + + m_D0 + :1; + +8485 } + mb™ +; + +8486 } + tEPILR26STR +; + +8488 +IO_BYTE + + mby‹ +; + +8490 +IO_BYTE + + m_D7 + :1; + +8491 +IO_BYTE + + m_D6 + :1; + +8492 +IO_BYTE + + m_D5 + :1; + +8493 +IO_BYTE + + m_D4 + :1; + +8494 +IO_BYTE + + m_D3 + :1; + +8495 +IO_BYTE + + m_D2 + :1; + +8496 +IO_BYTE + + m_D1 + :1; + +8497 +IO_BYTE + + m_D0 + :1; + +8498 } + mb™ +; + +8499 } + tEPILR27STR +; + +8501 +IO_BYTE + + mby‹ +; + +8503 +IO_BYTE + + m_D7 + :1; + +8504 +IO_BYTE + + m_D6 + :1; + +8505 +IO_BYTE + + m_D5 + :1; + +8506 +IO_BYTE + + m_D4 + :1; + +8507 +IO_BYTE + + m_D3 + :1; + +8508 +IO_BYTE + + m_D2 + :1; + +8509 +IO_BYTE + + m_D1 + :1; + +8510 +IO_BYTE + + m_D0 + :1; + +8511 } + mb™ +; + +8512 } + tEPILR28STR +; + +8514 +IO_BYTE + + mby‹ +; + +8516 +IO_BYTE + + m_D7 + :1; + +8517 +IO_BYTE + + m_D6 + :1; + +8518 +IO_BYTE + + m_D5 + :1; + +8519 +IO_BYTE + + m_D4 + :1; + +8520 +IO_BYTE + + m_D3 + :1; + +8521 +IO_BYTE + + m_D2 + :1; + +8522 +IO_BYTE + + m_D1 + :1; + +8523 +IO_BYTE + + m_D0 + :1; + +8524 } + mb™ +; + +8525 } + tEPILR29STR +; + +8527 +IO_BYTE + + mby‹ +; + +8529 +IO_BYTE + + m_D7 + :1; + +8530 +IO_BYTE + + m_D6 + :1; + +8531 +IO_BYTE + + m_D5 + :1; + +8532 +IO_BYTE + + m_D4 + :1; + +8533 +IO_BYTE + + m_D3 + :1; + +8534 +IO_BYTE + + m_D2 + :1; + +8535 +IO_BYTE + + m_D1 + :1; + +8536 +IO_BYTE + + m_D0 + :1; + +8537 } + mb™ +; + +8538 } + tPPER14STR +; + +8540 +IO_BYTE + + mby‹ +; + +8542 +IO_BYTE + + m_D7 + :1; + +8543 +IO_BYTE + + m_D6 + :1; + +8544 +IO_BYTE + + m_D5 + :1; + +8545 +IO_BYTE + + m_D4 + :1; + +8546 +IO_BYTE + + m_D3 + :1; + +8547 +IO_BYTE + + m_D2 + :1; + +8548 +IO_BYTE + + m_D1 + :1; + +8549 +IO_BYTE + + m_D0 + :1; + +8550 } + mb™ +; + +8551 } + tPPER15STR +; + +8553 +IO_BYTE + + mby‹ +; + +8555 +IO_BYTE + + m_D7 + :1; + +8556 +IO_BYTE + + m_D6 + :1; + +8557 +IO_BYTE + + m_D5 + :1; + +8558 +IO_BYTE + + m_D4 + :1; + +8559 +IO_BYTE + + m_D3 + :1; + +8560 +IO_BYTE + + m_D2 + :1; + +8561 +IO_BYTE + + m_D1 + :1; + +8562 +IO_BYTE + + m_D0 + :1; + +8563 } + mb™ +; + +8564 } + tPPER16STR +; + +8566 +IO_BYTE + + mby‹ +; + +8568 +IO_BYTE + + m_D7 + :1; + +8569 +IO_BYTE + + m_D6 + :1; + +8570 +IO_BYTE + + m_D5 + :1; + +8571 +IO_BYTE + + m_D4 + :1; + +8572 +IO_BYTE + + m_D3 + :1; + +8573 +IO_BYTE + + m_D2 + :1; + +8574 +IO_BYTE + + m_D1 + :1; + +8575 +IO_BYTE + + m_D0 + :1; + +8576 } + mb™ +; + +8577 } + tPPER17STR +; + +8579 +IO_BYTE + + mby‹ +; + +8581 + mIO_BYTE + :1; + +8582 +IO_BYTE + + m_D6 + :1; + +8583 + mIO_BYTE + :1; + +8584 + mIO_BYTE + :1; + +8585 + mIO_BYTE + :1; + +8586 +IO_BYTE + + m_D2 + :1; + +8587 + mIO_BYTE + :1; + +8588 + mIO_BYTE + :1; + +8589 } + mb™ +; + +8590 } + tPPER18STR +; + +8592 +IO_BYTE + + mby‹ +; + +8594 + mIO_BYTE + :1; + +8595 +IO_BYTE + + m_D6 + :1; + +8596 + mIO_BYTE + :1; + +8597 + mIO_BYTE + :1; + +8598 + mIO_BYTE + :1; + +8599 +IO_BYTE + + m_D2 + :1; + +8600 +IO_BYTE + + m_D1 + :1; + +8601 +IO_BYTE + + m_D0 + :1; + +8602 } + mb™ +; + +8603 } + tPPER19STR +; + +8605 +IO_BYTE + + mby‹ +; + +8607 +IO_BYTE + + m_D7 + :1; + +8608 +IO_BYTE + + m_D6 + :1; + +8609 +IO_BYTE + + m_D5 + :1; + +8610 +IO_BYTE + + m_D4 + :1; + +8611 +IO_BYTE + + m_D3 + :1; + +8612 +IO_BYTE + + m_D2 + :1; + +8613 +IO_BYTE + + m_D1 + :1; + +8614 +IO_BYTE + + m_D0 + :1; + +8615 } + mb™ +; + +8616 } + tPPER20STR +; + +8618 +IO_BYTE + + mby‹ +; + +8620 +IO_BYTE + + m_D7 + :1; + +8621 +IO_BYTE + + m_D6 + :1; + +8622 +IO_BYTE + + m_D5 + :1; + +8623 +IO_BYTE + + m_D4 + :1; + +8624 +IO_BYTE + + m_D3 + :1; + +8625 +IO_BYTE + + m_D2 + :1; + +8626 +IO_BYTE + + m_D1 + :1; + +8627 +IO_BYTE + + m_D0 + :1; + +8628 } + mb™ +; + +8629 } + tPPER21STR +; + +8631 +IO_BYTE + + mby‹ +; + +8633 + mIO_BYTE + :1; + +8634 + mIO_BYTE + :1; + +8635 +IO_BYTE + + m_D5 + :1; + +8636 +IO_BYTE + + m_D4 + :1; + +8637 + mIO_BYTE + :1; + +8638 + mIO_BYTE + :1; + +8639 +IO_BYTE + + m_D1 + :1; + +8640 +IO_BYTE + + m_D0 + :1; + +8641 } + mb™ +; + +8642 } + tPPER22STR +; + +8644 +IO_BYTE + + mby‹ +; + +8646 +IO_BYTE + + m_D7 + :1; + +8647 +IO_BYTE + + m_D6 + :1; + +8648 +IO_BYTE + + m_D5 + :1; + +8649 +IO_BYTE + + m_D4 + :1; + +8650 +IO_BYTE + + m_D3 + :1; + +8651 +IO_BYTE + + m_D2 + :1; + +8652 +IO_BYTE + + m_D1 + :1; + +8653 +IO_BYTE + + m_D0 + :1; + +8654 } + mb™ +; + +8655 } + tPPER24STR +; + +8657 +IO_BYTE + + mby‹ +; + +8659 + mIO_BYTE + :1; + +8660 + mIO_BYTE + :1; + +8661 + mIO_BYTE + :1; + +8662 + mIO_BYTE + :1; + +8663 + mIO_BYTE + :1; + +8664 + mIO_BYTE + :1; + +8665 +IO_BYTE + + m_D1 + :1; + +8666 +IO_BYTE + + m_D0 + :1; + +8667 } + mb™ +; + +8668 } + tPPER26STR +; + +8670 +IO_BYTE + + mby‹ +; + +8672 +IO_BYTE + + m_D7 + :1; + +8673 +IO_BYTE + + m_D6 + :1; + +8674 +IO_BYTE + + m_D5 + :1; + +8675 +IO_BYTE + + m_D4 + :1; + +8676 +IO_BYTE + + m_D3 + :1; + +8677 +IO_BYTE + + m_D2 + :1; + +8678 +IO_BYTE + + m_D1 + :1; + +8679 +IO_BYTE + + m_D0 + :1; + +8680 } + mb™ +; + +8681 } + tPPER27STR +; + +8683 +IO_BYTE + + mby‹ +; + +8685 +IO_BYTE + + m_D7 + :1; + +8686 +IO_BYTE + + m_D6 + :1; + +8687 +IO_BYTE + + m_D5 + :1; + +8688 +IO_BYTE + + m_D4 + :1; + +8689 +IO_BYTE + + m_D3 + :1; + +8690 +IO_BYTE + + m_D2 + :1; + +8691 +IO_BYTE + + m_D1 + :1; + +8692 +IO_BYTE + + m_D0 + :1; + +8693 } + mb™ +; + +8694 } + tPPER28STR +; + +8696 +IO_BYTE + + mby‹ +; + +8698 +IO_BYTE + + m_D7 + :1; + +8699 +IO_BYTE + + m_D6 + :1; + +8700 +IO_BYTE + + m_D5 + :1; + +8701 +IO_BYTE + + m_D4 + :1; + +8702 +IO_BYTE + + m_D3 + :1; + +8703 +IO_BYTE + + m_D2 + :1; + +8704 +IO_BYTE + + m_D1 + :1; + +8705 +IO_BYTE + + m_D0 + :1; + +8706 } + mb™ +; + +8707 } + tPPER29STR +; + +8709 +IO_BYTE + + mby‹ +; + +8711 +IO_BYTE + + m_D7 + :1; + +8712 +IO_BYTE + + m_D6 + :1; + +8713 +IO_BYTE + + m_D5 + :1; + +8714 +IO_BYTE + + m_D4 + :1; + +8715 +IO_BYTE + + m_D3 + :1; + +8716 +IO_BYTE + + m_D2 + :1; + +8717 +IO_BYTE + + m_D1 + :1; + +8718 +IO_BYTE + + m_D0 + :1; + +8719 } + mb™ +; + +8720 } + tPPCR14STR +; + +8722 +IO_BYTE + + mby‹ +; + +8724 +IO_BYTE + + m_D7 + :1; + +8725 +IO_BYTE + + m_D6 + :1; + +8726 +IO_BYTE + + m_D5 + :1; + +8727 +IO_BYTE + + m_D4 + :1; + +8728 +IO_BYTE + + m_D3 + :1; + +8729 +IO_BYTE + + m_D2 + :1; + +8730 +IO_BYTE + + m_D1 + :1; + +8731 +IO_BYTE + + m_D0 + :1; + +8732 } + mb™ +; + +8733 } + tPPCR15STR +; + +8735 +IO_BYTE + + mby‹ +; + +8737 +IO_BYTE + + m_D7 + :1; + +8738 +IO_BYTE + + m_D6 + :1; + +8739 +IO_BYTE + + m_D5 + :1; + +8740 +IO_BYTE + + m_D4 + :1; + +8741 +IO_BYTE + + m_D3 + :1; + +8742 +IO_BYTE + + m_D2 + :1; + +8743 +IO_BYTE + + m_D1 + :1; + +8744 +IO_BYTE + + m_D0 + :1; + +8745 } + mb™ +; + +8746 } + tPPCR16STR +; + +8748 +IO_BYTE + + mby‹ +; + +8750 +IO_BYTE + + m_D7 + :1; + +8751 +IO_BYTE + + m_D6 + :1; + +8752 +IO_BYTE + + m_D5 + :1; + +8753 +IO_BYTE + + m_D4 + :1; + +8754 +IO_BYTE + + m_D3 + :1; + +8755 +IO_BYTE + + m_D2 + :1; + +8756 +IO_BYTE + + m_D1 + :1; + +8757 +IO_BYTE + + m_D0 + :1; + +8758 } + mb™ +; + +8759 } + tPPCR17STR +; + +8761 +IO_BYTE + + mby‹ +; + +8763 + mIO_BYTE + :1; + +8764 +IO_BYTE + + m_D6 + :1; + +8765 + mIO_BYTE + :1; + +8766 + mIO_BYTE + :1; + +8767 + mIO_BYTE + :1; + +8768 +IO_BYTE + + m_D2 + :1; + +8769 + mIO_BYTE + :1; + +8770 + mIO_BYTE + :1; + +8771 } + mb™ +; + +8772 } + tPPCR18STR +; + +8774 +IO_BYTE + + mby‹ +; + +8776 + mIO_BYTE + :1; + +8777 +IO_BYTE + + m_D6 + :1; + +8778 + mIO_BYTE + :1; + +8779 +IO_BYTE + + m_D2 + :1; + +8780 +IO_BYTE + + m_D1 + :1; + +8781 +IO_BYTE + + m_D0 + :1; + +8782 + mIO_BYTE + :1; + +8783 + mIO_BYTE + :1; + +8784 } + mb™ +; + +8785 } + tPPCR19STR +; + +8787 +IO_BYTE + + mby‹ +; + +8789 +IO_BYTE + + m_D7 + :1; + +8790 +IO_BYTE + + m_D6 + :1; + +8791 +IO_BYTE + + m_D5 + :1; + +8792 +IO_BYTE + + m_D4 + :1; + +8793 +IO_BYTE + + m_D3 + :1; + +8794 +IO_BYTE + + m_D2 + :1; + +8795 +IO_BYTE + + m_D1 + :1; + +8796 +IO_BYTE + + m_D0 + :1; + +8797 } + mb™ +; + +8798 } + tPPCR20STR +; + +8800 +IO_BYTE + + mby‹ +; + +8802 +IO_BYTE + + m_D7 + :1; + +8803 +IO_BYTE + + m_D6 + :1; + +8804 +IO_BYTE + + m_D5 + :1; + +8805 +IO_BYTE + + m_D4 + :1; + +8806 +IO_BYTE + + m_D3 + :1; + +8807 +IO_BYTE + + m_D2 + :1; + +8808 +IO_BYTE + + m_D1 + :1; + +8809 +IO_BYTE + + m_D0 + :1; + +8810 } + mb™ +; + +8811 } + tPPCR21STR +; + +8813 +IO_BYTE + + mby‹ +; + +8815 + mIO_BYTE + :1; + +8816 + mIO_BYTE + :1; + +8817 +IO_BYTE + + m_D5 + :1; + +8818 +IO_BYTE + + m_D4 + :1; + +8819 + mIO_BYTE + :1; + +8820 + mIO_BYTE + :1; + +8821 +IO_BYTE + + m_D1 + :1; + +8822 +IO_BYTE + + m_D0 + :1; + +8823 } + mb™ +; + +8824 } + tPPCR22STR +; + +8826 +IO_BYTE + + mby‹ +; + +8828 +IO_BYTE + + m_D7 + :1; + +8829 +IO_BYTE + + m_D6 + :1; + +8830 +IO_BYTE + + m_D5 + :1; + +8831 +IO_BYTE + + m_D4 + :1; + +8832 +IO_BYTE + + m_D3 + :1; + +8833 +IO_BYTE + + m_D2 + :1; + +8834 +IO_BYTE + + m_D1 + :1; + +8835 +IO_BYTE + + m_D0 + :1; + +8836 } + mb™ +; + +8837 } + tPPCR24STR +; + +8839 +IO_BYTE + + mby‹ +; + +8841 + mIO_BYTE + :1; + +8842 + mIO_BYTE + :1; + +8843 + mIO_BYTE + :1; + +8844 + mIO_BYTE + :1; + +8845 + mIO_BYTE + :1; + +8846 + mIO_BYTE + :1; + +8847 +IO_BYTE + + m_D1 + :1; + +8848 +IO_BYTE + + m_D0 + :1; + +8849 } + mb™ +; + +8850 } + tPPCR26STR +; + +8852 +IO_BYTE + + mby‹ +; + +8854 +IO_BYTE + + m_D7 + :1; + +8855 +IO_BYTE + + m_D6 + :1; + +8856 +IO_BYTE + + m_D5 + :1; + +8857 +IO_BYTE + + m_D4 + :1; + +8858 +IO_BYTE + + m_D3 + :1; + +8859 +IO_BYTE + + m_D2 + :1; + +8860 +IO_BYTE + + m_D1 + :1; + +8861 +IO_BYTE + + m_D0 + :1; + +8862 } + mb™ +; + +8863 } + tPPCR27STR +; + +8865 +IO_BYTE + + mby‹ +; + +8867 +IO_BYTE + + m_D7 + :1; + +8868 +IO_BYTE + + m_D6 + :1; + +8869 +IO_BYTE + + m_D5 + :1; + +8870 +IO_BYTE + + m_D4 + :1; + +8871 +IO_BYTE + + m_D3 + :1; + +8872 +IO_BYTE + + m_D2 + :1; + +8873 +IO_BYTE + + m_D1 + :1; + +8874 +IO_BYTE + + m_D0 + :1; + +8875 } + mb™ +; + +8876 } + tPPCR28STR +; + +8878 +IO_BYTE + + mby‹ +; + +8880 +IO_BYTE + + m_D7 + :1; + +8881 +IO_BYTE + + m_D6 + :1; + +8882 +IO_BYTE + + m_D5 + :1; + +8883 +IO_BYTE + + m_D4 + :1; + +8884 +IO_BYTE + + m_D3 + :1; + +8885 +IO_BYTE + + m_D2 + :1; + +8886 +IO_BYTE + + m_D1 + :1; + +8887 +IO_BYTE + + m_D0 + :1; + +8888 } + mb™ +; + +8889 } + tPPCR29STR +; + +8891 +IO_BYTE + + mby‹ +; + +8893 +IO_BYTE + + m_ASYNC + :1; + +8894 +IO_BYTE + + m_FIXE + :1; + +8895 +IO_BYTE + + m_BIRE + :1; + +8896 +IO_BYTE + + m_RDYEG + :1; + +8897 +IO_BYTE + + m_RDY + :1; + +8898 +IO_BYTE + + m_RDYI + :1; + +8899 +IO_BYTE + + m_RW16 + :1; + +8900 +IO_BYTE + + m_LPM + :1; + +8901 } + mb™ +; + +8902 } + tFMCSSTR +; + +8904 +IO_BYTE + + mby‹ +; + +8906 + mIO_BYTE + :1; + +8907 + mIO_BYTE + :1; + +8908 + mIO_BYTE + :1; + +8909 + mIO_BYTE + :1; + +8910 +IO_BYTE + + m_LOCK + :1; + +8911 +IO_BYTE + + m_PHASE + :1; + +8912 +IO_BYTE + + m_PF2I + :1; + +8913 +IO_BYTE + + m_RD64 + :1; + +8914 } + mb™ +; + +8915 } + tFMCRSTR +; + +8917 +IO_WORD + + mwÜd +; + +8919 + mIO_WORD + :1; + +8920 + mIO_WORD + :1; + +8921 + mIO_WORD + :1; + +8922 + mIO_WORD + :1; + +8923 + mIO_WORD + :1; + +8924 + mIO_WORD + :1; + +8925 +IO_WORD + + m_REN + :1; + +8926 +IO_WORD + + m_TAGE + :1; + +8927 +IO_WORD + + m_FLUSH + :1; + +8928 +IO_WORD + + m_DBEN + :1; + +8929 +IO_WORD + + m_PFEN + :1; + +8930 +IO_WORD + + m_PFMC + :1; + +8931 +IO_WORD + + m_LOCK + :1; + +8932 +IO_WORD + + m_ENAB + :1; + +8933 +IO_WORD + + m_SIZE1 + :1; + +8934 +IO_WORD + + m_SIZE0 + :1; + +8935 } + mb™ +; + +8937 + mIO_WORD + :1; + +8938 + mIO_WORD + :1; + +8939 + mIO_WORD + :1; + +8940 + mIO_WORD + :1; + +8941 + mIO_WORD + :1; + +8942 + mIO_WORD + :1; + +8943 + mIO_WORD + :1; + +8944 + mIO_WORD + :1; + +8945 + mIO_WORD + :1; + +8946 + mIO_WORD + :1; + +8947 + mIO_WORD + :1; + +8948 + mIO_WORD + :1; + +8949 + mIO_WORD + :1; + +8950 + mIO_WORD + :1; + +8951 +IO_WORD + + m_SIZE + :2; + +8952 } + mb™c +; + +8953 } + tFCHCRSTR +; + +8955 +IO_WORD + + mwÜd +; + +8957 +IO_WORD + + m_WTP1 + :1; + +8958 +IO_WORD + + m_WTP0 + :1; + +8959 +IO_WORD + + m_WEXH1 + :1; + +8960 +IO_WORD + + m_WEXH0 + :1; + +8961 +IO_WORD + + m_WTC3 + :1; + +8962 +IO_WORD + + m_WTC2 + :1; + +8963 +IO_WORD + + m_WTC1 + :1; + +8964 +IO_WORD + + m_WTC0 + :1; + +8965 +IO_WORD + + m_FRAM + :1; + +8966 +IO_WORD + + m_ATD2 + :1; + +8967 +IO_WORD + + m_ATD1 + :1; + +8968 +IO_WORD + + m_ATD0 + :1; + +8969 +IO_WORD + + m_EQ3 + :1; + +8970 +IO_WORD + + m_EQ2 + :1; + +8971 +IO_WORD + + m_EQ1 + :1; + +8972 +IO_WORD + + m_EQ0 + :1; + +8973 } + mb™ +; + +8975 +IO_WORD + + m_WTP + :2; + +8976 +IO_WORD + + m_WEXH + :2; + +8977 +IO_WORD + + m_WTC + :4; + +8978 + mIO_WORD + :1; + +8979 +IO_WORD + + m_ATD + :3; + +8980 +IO_WORD + + m_EQ + :4; + +8981 } + mb™c +; + +8982 } + tFMWTSTR +; + +8984 +IO_BYTE + + mby‹ +; + +8986 + mIO_BYTE + :1; + +8987 +IO_BYTE + + m_ALEH2 + :1; + +8988 +IO_BYTE + + m_ALEH1 + :1; + +8989 +IO_BYTE + + m_ALEH0 + :1; + +8990 + mIO_BYTE + :1; + +8991 + mIO_BYTE + :1; + +8992 + mIO_BYTE + :1; + +8993 + mIO_BYTE + :1; + +8994 } + mb™ +; + +8996 + mIO_BYTE + :1; + +8997 +IO_BYTE + + m_ALEH + :3; + +8998 } + mb™c +; + +8999 } + tFMWT2STR +; + +9001 +IO_BYTE + + mby‹ +; + +9003 + mIO_BYTE + :1; + +9004 + mIO_BYTE + :1; + +9005 + mIO_BYTE + :1; + +9006 + mIO_BYTE + :1; + +9007 + mIO_BYTE + :1; + +9008 +IO_BYTE + + m_PS2 + :1; + +9009 +IO_BYTE + + m_PS1 + :1; + +9010 +IO_BYTE + + m_PS0 + :1; + +9011 } + mb™ +; + +9013 + mIO_BYTE + :1; + +9014 + mIO_BYTE + :1; + +9015 + mIO_BYTE + :1; + +9016 + mIO_BYTE + :1; + +9017 + mIO_BYTE + :1; + +9018 +IO_BYTE + + m_PS + :3; + +9019 } + mb™c +; + +9020 } + tFMPSSTR +; + +9022 +IO_LWORD + + mlwÜd +; + +9024 +IO_LWORD + + m_CRC31 + :1; + +9025 +IO_LWORD + + m_CRC30 + :1; + +9026 +IO_LWORD + + m_CRC29 + :1; + +9027 +IO_LWORD + + m_CRC28 + :1; + +9028 +IO_LWORD + + m_CRC27 + :1; + +9029 +IO_LWORD + + m_CRC26 + :1; + +9030 +IO_LWORD + + m_CRC25 + :1; + +9031 +IO_LWORD + + m_CRC24 + :1; + +9032 +IO_LWORD + + m_CRC23 + :1; + +9033 +IO_LWORD + + m_CRC22 + :1; + +9034 +IO_LWORD + + m_CRC21 + :1; + +9035 +IO_LWORD + + m_CRC20 + :1; + +9036 +IO_LWORD + + m_CRC19 + :1; + +9037 +IO_LWORD + + m_CRC18 + :1; + +9038 +IO_LWORD + + m_CRC17 + :1; + +9039 +IO_LWORD + + m_CRC16 + :1; + +9040 +IO_LWORD + + m_CRC15 + :1; + +9041 +IO_LWORD + + m_CRC14 + :1; + +9042 +IO_LWORD + + m_CRC13 + :1; + +9043 +IO_LWORD + + m_CRC12 + :1; + +9044 +IO_LWORD + + m_CRC11 + :1; + +9045 +IO_LWORD + + m_CRC10 + :1; + +9046 +IO_LWORD + + m_CRC9 + :1; + +9047 +IO_LWORD + + m_CRC8 + :1; + +9048 +IO_LWORD + + m_CRC7 + :1; + +9049 +IO_LWORD + + m_CRC6 + :1; + +9050 +IO_LWORD + + m_CRC5 + :1; + +9051 +IO_LWORD + + m_CRC4 + :1; + +9052 +IO_LWORD + + m_CRC3 + :1; + +9053 +IO_LWORD + + m_CRC2 + :1; + +9054 +IO_LWORD + + m_CRC1 + :1; + +9055 +IO_LWORD + + m_CRC0 + :1; + +9056 } + mb™ +; + +9057 } + tFSCR0STR +; + +9059 +IO_LWORD + + mlwÜd +; + +9061 + mIO_LWORD + :1; + +9062 + mIO_LWORD + :1; + +9063 + mIO_LWORD + :1; + +9064 + mIO_LWORD + :1; + +9065 + mIO_LWORD + :1; + +9066 + mIO_LWORD + :1; + +9067 + mIO_LWORD + :1; + +9068 +IO_LWORD + + m_RDY + :1; + +9069 + mIO_LWORD + :1; + +9070 + mIO_LWORD + :1; + +9071 + mIO_LWORD + :1; + +9072 + mIO_LWORD + :1; + +9073 +IO_LWORD + + m_CSZ3 + :1; + +9074 +IO_LWORD + + m_CSZ2 + :1; + +9075 +IO_LWORD + + m_CSZ1 + :1; + +9076 +IO_LWORD + + m_CSZ0 + :1; + +9077 +IO_LWORD + + m_CSA15 + :1; + +9078 +IO_LWORD + + m_CSA14 + :1; + +9079 +IO_LWORD + + m_CSA13 + :1; + +9080 +IO_LWORD + + m_CSA12 + :1; + +9081 +IO_LWORD + + m_CSA11 + :1; + +9082 +IO_LWORD + + m_CSA10 + :1; + +9083 +IO_LWORD + + m_CSA9 + :1; + +9084 +IO_LWORD + + m_CSA8 + :1; + +9085 +IO_LWORD + + m_CSA7 + :1; + +9086 +IO_LWORD + + m_CSA6 + :1; + +9087 +IO_LWORD + + m_CSA5 + :1; + +9088 +IO_LWORD + + m_CSA4 + :1; + +9089 +IO_LWORD + + m_CSA3 + :1; + +9090 +IO_LWORD + + m_CSA2 + :1; + +9091 +IO_LWORD + + m_CSA1 + :1; + +9092 +IO_LWORD + + m_CSA0 + :1; + +9093 } + mb™ +; + +9095 + mIO_LWORD + :1; + +9096 + mIO_LWORD + :1; + +9097 + mIO_LWORD + :1; + +9098 + mIO_LWORD + :1; + +9099 + mIO_LWORD + :1; + +9100 + mIO_LWORD + :1; + +9101 + mIO_LWORD + :1; + +9102 + mIO_LWORD + :1; + +9103 + mIO_LWORD + :1; + +9104 + mIO_LWORD + :1; + +9105 + mIO_LWORD + :1; + +9106 + mIO_LWORD + :1; + +9107 +IO_LWORD + + m_CSZ + :4; + +9108 } + mb™c +; + +9109 } + tFSCR1STR +; + +9111 +IO_WORD + + mwÜd +; + +9113 + mIO_WORD + :1; + +9114 + mIO_WORD + :1; + +9115 + mIO_WORD + :1; + +9116 + mIO_WORD + :1; + +9117 + mIO_WORD + :1; + +9118 + mIO_WORD + :1; + +9119 + mIO_WORD + :1; + +9120 + mIO_WORD + :1; + +9121 +IO_WORD + + m_Te¡ + :1; + +9122 +IO_WORD + + m_CCE + :1; + +9123 +IO_WORD + + m_DAR + :1; + +9124 + mIO_WORD + :1; + +9125 +IO_WORD + + m_EIE + :1; + +9126 +IO_WORD + + m_SIE + :1; + +9127 +IO_WORD + + m_IE + :1; + +9128 +IO_WORD + + m_In™ + :1; + +9129 } + mb™ +; + +9130 } + tCTRLR4STR +; + +9132 +IO_WORD + + mwÜd +; + +9134 + mIO_WORD + :1; + +9135 + mIO_WORD + :1; + +9136 + mIO_WORD + :1; + +9137 + mIO_WORD + :1; + +9138 + mIO_WORD + :1; + +9139 + mIO_WORD + :1; + +9140 + mIO_WORD + :1; + +9141 + mIO_WORD + :1; + +9142 +IO_WORD + + m_BOff + :1; + +9143 +IO_WORD + + m_EW¬n + :1; + +9144 +IO_WORD + + m_EPass + :1; + +9145 +IO_WORD + + m_RxOK + :1; + +9146 +IO_WORD + + m_TxOK + :1; + +9147 +IO_WORD + + m_LEC2 + :1; + +9148 +IO_WORD + + m_LEC1 + :1; + +9149 +IO_WORD + + m_LEC0 + :1; + +9150 } + mb™ +; + +9152 + mIO_WORD + :1; + +9153 + mIO_WORD + :1; + +9154 + mIO_WORD + :1; + +9155 + mIO_WORD + :1; + +9156 + mIO_WORD + :1; + +9157 + mIO_WORD + :1; + +9158 + mIO_WORD + :1; + +9159 + mIO_WORD + :1; + +9160 + mIO_WORD + :1; + +9161 + mIO_WORD + :1; + +9162 + mIO_WORD + :1; + +9163 + mIO_WORD + :1; + +9164 + mIO_WORD + :1; + +9165 +IO_WORD + + m_LEC + :3; + +9166 } + mb™c +; + +9167 } + tSTATR4STR +; + +9169 +IO_WORD + + mwÜd +; + +9171 +IO_WORD + + m_RP + :1; + +9172 +IO_WORD + + m_REC6 + :1; + +9173 +IO_WORD + + m_REC5 + :1; + +9174 +IO_WORD + + m_REC4 + :1; + +9175 +IO_WORD + + m_REC3 + :1; + +9176 +IO_WORD + + m_REC2 + :1; + +9177 +IO_WORD + + m_REC1 + :1; + +9178 +IO_WORD + + m_REC0 + :1; + +9179 +IO_WORD + + m_TEC7 + :1; + +9180 +IO_WORD + + m_TEC6 + :1; + +9181 +IO_WORD + + m_TEC5 + :1; + +9182 +IO_WORD + + m_TEC4 + :1; + +9183 +IO_WORD + + m_TEC3 + :1; + +9184 +IO_WORD + + m_TEC2 + :1; + +9185 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+IO_LWORD + + gmsgv®124 +; + +15141  + #MSGVAL124 + +msgv®124 + + + ) + +15142 +__IO_EXTERN + +IO_WORD + + gmsgv®24 +; + +15143  + #MSGVAL24 + +msgv®24 + + + ) + +15144 +__IO_EXTERN + +IO_WORD + + gmsgv®14 +; + +15145  + #MSGVAL14 + +msgv®14 + + + ) + +15146 +__IO_EXTERN + +BCTRLSTR + + gbù¾ +; + +15147  + #BCTRL + +bù¾ +. +lwÜd + + + ) + +15148  + #BCTRL_SR + +bù¾ +. +b™ +. +_SR + + + ) + +15149  + #BCTRL_SW + +bù¾ +. +b™ +. +_SW + + + ) + +15150  + #BCTRL_SX + +bù¾ +. +b™ +. +_SX + + + ) + +15151  + #BCTRL_UR + +bù¾ +. +b™ +. +_UR + + + ) + +15152  + #BCTRL_UW + +bù¾ +. +b™ +. +_UW + + + ) + +15153  + #BCTRL_UX + +bù¾ +. +b™ +. +_UX + + + ) + +15154  + #BCTRL_FCPU + +bù¾ +. +b™ +. +_FCPU + + + ) + +15155  + #BCTRL_FDMA + +bù¾ +. +b™ +. +_FDMA + + + ) + +15156  + #BCTRL_EEMM + +bù¾ +. +b™ +. +_EEMM + + + ) + +15157  + #BCTRL_PFD + +bù¾ +. +b™ +. +_PFD + + + ) + +15158  + #BCTRL_SINT1 + +bù¾ +. +b™ +. +_SINT1 + + + ) + +15159  + #BCTRL_SINT0 + +bù¾ +. +b™ +. +_SINT0 + + + ) + +15160  + #BCTRL_EINT1 + +bù¾ +. +b™ +. +_EINT1 + + + ) + +15161  + #BCTRL_EINT0 + +bù¾ +. +b™ +. +_EINT0 + + + ) + +15162  + #BCTRL_EINTT + +bù¾ +. +b™ +. +_EINTT + + + ) + +15163  + #BCTRL_EINTR + +bù¾ +. +b™ +. +_EINTR + + + ) + +15164  + #BCTRL_SINT + +bù¾ +. +b™c +. +_SINT + + + ) + +15165  + #BCTRL_EINT + +bù¾ +. +b™c +. +_EINT + + + ) + +15166 +__IO_EXTERN + +BSTATSTR + + gb¡© +; + +15167  + #BSTAT + +b¡© +. +lwÜd + + + ) + +15168  + #BSTAT_IDX4 + +b¡© +. +b™ +. +_IDX4 + + + ) + +15169  + #BSTAT_IDX3 + +b¡© +. +b™ +. +_IDX3 + + + ) + +15170  + #BSTAT_IDX2 + +b¡© +. +b™ +. +_IDX2 + + + ) + +15171  + #BSTAT_IDX1 + +b¡© +. +b™ +. +_IDX1 + + + ) + +15172  + #BSTAT_IDX0 + +b¡© +. +b™ +. +_IDX0 + + + ) + +15173  + #BSTAT_CDMA + +b¡© +. +b™ +. +_CDMA + + + ) + +15174  + #BSTAT_CSZ1 + +b¡© +. +b™ +. +_CSZ1 + + + ) + +15175  + #BSTAT_CSZ0 + +b¡© +. +b™ +. +_CSZ0 + + + ) + +15176  + #BSTAT_CRW1 + +b¡© +. +b™ +. +_CRW1 + + + ) + +15177  + #BSTAT_CRW0 + +b¡© +. +b™ +. +_CRW0 + + + ) + +15178  + #BSTAT_PV + +b¡© +. +b™ +. +_PV + + + ) + +15179  + #BSTAT_RST + +b¡© +. +b™ +. +_RST + + + ) + +15180  + #BSTAT_INT1 + +b¡© +. +b™ +. +_INT1 + + + ) + +15181  + #BSTAT_INT0 + +b¡© +. +b™ +. +_INT0 + + + ) + +15182  + #BSTAT_INTT + +b¡© +. +b™ +. +_INTT + + + ) + +15183  + #BSTAT_INTR + +b¡© +. +b™ +. +_INTR + + + ) + +15184  + #BSTAT_IDX + +b¡© +. +b™c +. +_IDX + + + ) + +15185  + #BSTAT_CSZ + +b¡© +. +b™c +. +_CSZ + + + ) + +15186  + #BSTAT_CRW + +b¡© +. +b™c +. +_CRW + + + ) + +15187  + #BSTAT_INT + +b¡© +. +b™c +. +_INT + + + ) + +15188 +__IO_EXTERN + +IO_LWORD + + gbŸc +; + +15189  + #BIAC + +bŸc + + + ) + +15190 +__IO_EXTERN + +IO_LWORD + + gbßc +; + +15191  + #BOAC + +bßc + + + ) + +15192 +__IO_EXTERN + +BIRQSTR + + gbœq +; + +15193  + #BIRQ + +bœq +. +lwÜd + + + ) + +15194  + #BIRQ_BD31 + +bœq +. +b™ +. +_BD31 + + + ) + +15195  + #BIRQ_BD30 + +bœq +. +b™ +. +_BD30 + + + ) + +15196  + #BIRQ_BD29 + +bœq +. +b™ +. +_BD29 + + + ) + +15197  + #BIRQ_BD28 + +bœq +. +b™ +. +_BD28 + + + ) + +15198  + #BIRQ_BD27 + +bœq +. +b™ +. +_BD27 + + + ) + +15199  + #BIRQ_BD26 + +bœq +. +b™ +. +_BD26 + + + ) + +15200  + #BIRQ_BD25 + +bœq +. +b™ +. +_BD25 + + + ) + +15201  + #BIRQ_BD24 + +bœq +. +b™ +. +_BD24 + + + ) + +15202  + #BIRQ_BD23 + +bœq +. +b™ +. +_BD23 + + + ) + +15203  + #BIRQ_BD22 + +bœq +. +b™ +. +_BD22 + + + ) + +15204  + #BIRQ_BD21 + +bœq +. +b™ +. +_BD21 + + + ) + +15205  + #BIRQ_BD20 + +bœq +. +b™ +. +_BD20 + + + ) + +15206  + #BIRQ_BD19 + +bœq +. +b™ +. +_BD19 + + + ) + +15207  + #BIRQ_BD18 + +bœq +. +b™ +. +_BD18 + + + ) + +15208  + #BIRQ_BD17 + +bœq +. +b™ +. +_BD17 + + + ) + +15209  + #BIRQ_BD16 + +bœq +. +b™ +. +_BD16 + + + ) + +15210  + #BIRQ_BD15 + +bœq +. +b™ +. +_BD15 + + + ) + +15211  + #BIRQ_BD14 + +bœq +. +b™ +. +_BD14 + + + ) + +15212  + #BIRQ_BD13 + +bœq +. +b™ +. +_BD13 + + + ) + +15213  + #BIRQ_BD12 + +bœq +. +b™ +. +_BD12 + + + ) + +15214  + #BIRQ_BD11 + +bœq +. +b™ +. +_BD11 + + + ) + +15215  + #BIRQ_BD10 + +bœq +. +b™ +. +_BD10 + + + ) + +15216  + #BIRQ_BD9 + +bœq +. +b™ +. +_BD9 + + + ) + +15217  + #BIRQ_BD8 + +bœq +. +b™ +. +_BD8 + + + ) + +15218  + #BIRQ_BD7 + +bœq +. +b™ +. +_BD7 + + + ) + +15219  + #BIRQ_BD6 + +bœq +. +b™ +. +_BD6 + + + ) + +15220  + #BIRQ_BD5 + +bœq +. +b™ +. +_BD5 + + + ) + +15221  + #BIRQ_BD4 + +bœq +. +b™ +. +_BD4 + + + ) + +15222  + #BIRQ_BD3 + +bœq +. +b™ +. +_BD3 + + + ) + +15223  + #BIRQ_BD2 + +bœq +. +b™ +. +_BD2 + + + ) + +15224  + #BIRQ_BD1 + +bœq +. +b™ +. +_BD1 + + + ) + +15225  + #BIRQ_BD0 + +bœq +. +b™ +. +_BD0 + + + ) + +15226 +__IO_EXTERN + +BCR0STR + + gbü0 +; + +15227  + #BCR0 + +bü0 +. +lwÜd + + + ) + +15228  + #BCR0_SRX1 + +bü0 +. +b™ +. +_SRX1 + + + ) + +15229  + #BCR0_SW1 + +bü0 +. +b™ +. +_SW1 + + + ) + +15230  + #BCR0_SRX0 + +bü0 +. +b™ +. +_SRX0 + + + ) + +15231  + #BCR0_SW0 + +bü0 +. +b™ +. +_SW0 + + + ) + +15232  + #BCR0_URX1 + +bü0 +. +b™ +. +_URX1 + + + ) + +15233  + #BCR0_UW1 + +bü0 +. +b™ +. +_UW1 + + + ) + +15234  + #BCR0_URX0 + +bü0 +. +b™ +. +_URX0 + + + ) + +15235  + #BCR0_UW0 + +bü0 +. +b™ +. +_UW0 + + + ) + +15236  + #BCR0_MPE + +bü0 +. +b™ +. +_MPE + + + ) + +15237  + #BCR0_COMB + +bü0 +. +b™ +. +_COMB + + + ) + +15238  + #BCR0_CTC1 + +bü0 +. +b™ +. +_CTC1 + + + ) + +15239  + #BCR0_CTC0 + +bü0 +. +b™ +. +_CTC0 + + + ) + +15240  + #BCR0_OBS1 + +bü0 +. +b™ +. +_OBS1 + + + ) + +15241  + #BCR0_OBS0 + +bü0 +. +b™ +. +_OBS0 + + + ) + +15242  + #BCR0_OBT1 + +bü0 +. +b™ +. +_OBT1 + + + ) + +15243  + #BCR0_OBT0 + +bü0 +. +b™ +. +_OBT0 + + + ) + +15244  + #BCR0_EP3 + +bü0 +. +b™ +. +_EP3 + + + ) + +15245  + #BCR0_EP2 + +bü0 +. +b™ +. +_EP2 + + + ) + +15246  + #BCR0_EP1 + +bü0 +. +b™ +. +_EP1 + + + ) + +15247  + #BCR0_EP0 + +bü0 +. +b™ +. +_EP0 + + + ) + +15248  + #BCR0_EM1 + +bü0 +. +b™ +. +_EM1 + + + ) + +15249  + #BCR0_EM0 + +bü0 +. +b™ +. +_EM0 + + + ) + +15250  + #BCR0_ER1 + +bü0 +. +b™ +. +_ER1 + + + ) + +15251  + #BCR0_ER0 + +bü0 +. +b™ +. +_ER0 + + + ) + +15252  + #BCR0_CTC + +bü0 +. +b™c +. +_CTC + + + ) + +15253  + #BCR0_OBS + +bü0 +. +b™c +. +_OBS + + + ) + +15254  + #BCR0_OBT + +bü0 +. +b™c +. +_OBT + + + ) + +15255  + #BCR0_EP + +bü0 +. +b™c +. +_EP + + + ) + +15256  + #BCR0_EM + +bü0 +. +b™c +. +_EM + + + ) + +15257  + #BCR0_ER + +bü0 +. +b™c +. +_ER + + + ) + +15258 +__IO_EXTERN + +BCR1STR + + gbü1 +; + +15259  + #BCR1 + +bü1 +. +lwÜd + + + ) + +15260  + #BCR1_SRX1 + +bü1 +. +b™ +. +_SRX1 + + + ) + +15261  + #BCR1_SW1 + +bü1 +. +b™ +. +_SW1 + + + ) + +15262  + #BCR1_SRX0 + +bü1 +. +b™ +. +_SRX0 + + + ) + +15263  + #BCR1_SW0 + +bü1 +. +b™ +. +_SW0 + + + ) + +15264  + #BCR1_URX1 + +bü1 +. +b™ +. +_URX1 + + + ) + +15265  + #BCR1_UW1 + +bü1 +. +b™ +. +_UW1 + + + ) + +15266  + #BCR1_URX0 + +bü1 +. +b™ +. +_URX0 + + + ) + +15267  + #BCR1_UW0 + +bü1 +. +b™ +. +_UW0 + + + ) + +15268  + #BCR1_MPE + +bü1 +. +b™ +. +_MPE + + + ) + +15269  + #BCR1_COMB + +bü1 +. +b™ +. +_COMB + + + ) + +15270  + #BCR1_CTC1 + +bü1 +. +b™ +. +_CTC1 + + + ) + +15271  + #BCR1_CTC0 + +bü1 +. +b™ +. +_CTC0 + + + ) + +15272  + #BCR1_OBS1 + +bü1 +. +b™ +. +_OBS1 + + + ) + +15273  + #BCR1_OBS0 + +bü1 +. +b™ +. +_OBS0 + + + ) + +15274  + #BCR1_OBT1 + +bü1 +. +b™ +. +_OBT1 + + + ) + +15275  + #BCR1_OBT0 + +bü1 +. +b™ +. +_OBT0 + + + ) + +15276  + #BCR1_EP3 + +bü1 +. +b™ +. +_EP3 + + + ) + +15277  + #BCR1_EP2 + +bü1 +. +b™ +. +_EP2 + + + ) + +15278  + #BCR1_EP1 + +bü1 +. +b™ +. +_EP1 + + + ) + +15279  + #BCR1_EP0 + +bü1 +. +b™ +. +_EP0 + + + ) + +15280  + #BCR1_EM1 + +bü1 +. +b™ +. +_EM1 + + + ) + +15281  + #BCR1_EM0 + +bü1 +. +b™ +. +_EM0 + + + ) + +15282  + #BCR1_ER1 + +bü1 +. +b™ +. +_ER1 + + + ) + +15283  + #BCR1_ER0 + +bü1 +. +b™ +. +_ER0 + + + ) + +15284  + #BCR1_CTC + +bü1 +. +b™c +. +_CTC + + + ) + +15285  + #BCR1_OBS + +bü1 +. +b™c +. +_OBS + + + ) + +15286  + #BCR1_OBT + +bü1 +. +b™c +. +_OBT + + + ) + +15287  + #BCR1_EP + +bü1 +. +b™c +. +_EP + + + ) + +15288  + #BCR1_EM + +bü1 +. +b™c +. +_EM + + + ) + +15289  + #BCR1_ER + +bü1 +. +b™c +. +_ER + + + ) + +15290 +__IO_EXTERN + +IO_LWORD + + gbad0 +; + +15291  + #BAD0 + +bad0 + + + ) + +15292 +__IO_EXTERN + +IO_LWORD + + gbad1 +; + +15293  + #BAD1 + +bad1 + + + ) + +15294 +__IO_EXTERN + +IO_LWORD + + gbad2 +; + +15295  + #BAD2 + +bad2 + + + ) + +15296 +__IO_EXTERN + +IO_LWORD + + gbad3 +; + +15297  + #BAD3 + +bad3 + + + ) + +15298 +__IO_EXTERN + +IO_LWORD + + gbad4 +; + +15299  + #BAD4 + +bad4 + + + ) + +15300 +__IO_EXTERN + +IO_LWORD + + gbad5 +; + +15301  + #BAD5 + +bad5 + + + ) + +15302 +__IO_EXTERN + +IO_LWORD + + gbad6 +; + +15303  + #BAD6 + +bad6 + + + ) + +15304 +__IO_EXTERN + +IO_LWORD + + gbad7 +; + +15305  + #BAD7 + +bad7 + + + ) + +15306 +__IO_EXTERN + +IO_LWORD + + gfsv1 +; + +15307  + #FSV1 + +fsv1 + + + ) + +15308 +__IO_EXTERN + +IO_LWORD + + gbsv1 +; + +15309  + #BSV1 + +bsv1 + + + ) + +15310 +__IO_EXTERN + +IO_LWORD + + gfsv2 +; + +15311  + #FSV2 + +fsv2 + + + ) + +15312 +__IO_EXTERN + +IO_LWORD + + gbsv2 +; + +15313  + #BSV2 + +bsv2 + + + ) + +15318  + #RB_SYNC + if( +RBSYNC +) + + ) + +15319  + #CB_SYNC4 + if( +CBSYNC4 +) + + ) + + @uart.c + +7  + ~"mb91465k.h +" + +9 cÚ¡  + gASCII +[] = "0123456789ABCDEF"; + +11  + $In™U¬t4 +() + +15 +BGR04 + = 832; + +25 +SCR04 + = 0x17; + +26 +SMR04 + = 0x0d; + +27 +SSR04 + = 0x00; + +28 +PFR19 + = (PFR19 & 0xFC) | 0x03; + +29 +EPFR19 + = 0x00; + +30 + } +} + +32  + $Putch4 +( +ch +) + +34  +SSR04_TDRE + == 0); + +35 +TDR04 + = +ch +; + +36 + } +} + +38  + $G‘ch4 +() + +40 vÞ©ž +ch +; + +45  +SSR04_RDRF + == 0) + +46 +HWWD + = 0x00; + +48 +ch + = +RDR04 +; + +50 ià(( +SSR04 + & 0xE0) != 0) + +52 +SCR04_CRE + = 1; + +55  ( +ch +); + +57 + } +} + +60  + $Puts4 +(cÚ¡ * +Name2 +) + +62 vÞ©ž +i +, +Ën +; + +64 +Ën + = + `¡¾’ +( +Name2 +); + +66  +i +=0; i< + `¡¾’ +( +Name2 +); i++) + +68 ià( +Name2 +[ +i +] == 10) + +69 + `Putch4 +(13); + +70 + `Putch4 +( +Name2 +[ +i +]); + +72 + } +} + +75  + $Echo4 +() + +77  +ch +; + +79 + `Puts4 +("UART 4„eceive: "); + +80 +ch + = +RDR04 +; + +81 + `Putch4 +( +ch +); + +82 ià( +ch +==13) + +83 + `Putch4 +(10); + +85  ( +ch +); + +86 + } +} + +88  + $Puthex4 +( +n +,  +dig™s +) + +90  +dig™ +=0, +div +=0, +i +; + +92 +div +=(4*( +dig™s +-1)); + +93  +i +=0;i< +dig™s +;i++) + +95 +dig™ + = (( +n + >> +div +)&0xF); + +96 + `Putch4 +( +dig™ + + ((digit < 0xA) ? '0' : 'A' - 0xA)); + +97 +div +-=4; + +99 + } +} + +101  + $Putdec4 +( +x +,  +dig™s +) + +103  +i +; + +104  +buf +[10], +sign +=1; + +106 ià( +dig™s + < 0) { + +107 +dig™s + *= (-1); + +108 +sign + =1; + +110 +buf +[ +dig™s +]='\0'; + +112  +i += +dig™s +; i>0; i--) { + +113 +buf +[ +i +-1] = +ASCII +[ +x + % 10]; + +114 +x + = x/10; + +117 iàÐ +sign + ) + +119  +i +=0; +buf +[i]=='0'; i++) { + +120 iàÐ +i +< +dig™s +-1) + +121 +buf +[ +i +] = ' '; + +125 + `Puts4 +( +buf +); + +126 + } +} + + @vectors.c + +18  + ~"mb91465k.h +" + +19  + ~"RLT.h +" + +32  + $In™IrqLev–s +() + +38 +ICR01 + = 31; + +40 +ICR02 + = 31; + +42 +ICR03 + = 31; + +44 +ICR04 + = 31; + +46 +ICR05 + = 31; + +48 +ICR06 + = 31; + +50 +ICR07 + = 31; + +52 +ICR08 + = 30; + +54 +ICR09 + = 31; + +56 +ICR10 + = 31; + +58 +ICR11 + = 31; + +60 +ICR12 + = 31; + +62 +ICR13 + = 31; + +64 +ICR14 + = 31; + +66 +ICR15 + = 31; + +68 +ICR16 + = 31; + +70 +ICR17 + = 31; + +72 +ICR18 + = 31; + +74 +ICR19 + = 31; + +76 +ICR20 + = 31; + +78 +ICR21 + = 31; + +80 +ICR22 + = 31; + +82 +ICR23 + = 31; + +84 +ICR24 + = 31; + +86 +ICR25 + = 31; + +88 +ICR26 + = 31; + +90 +ICR27 + = 31; + +92 +ICR28 + = 31; + +94 +ICR29 + = 31; + +96 +ICR30 + = 31; + +98 +ICR31 + = 31; + +100 +ICR32 + = 31; + +102 +ICR33 + = 31; + +104 +ICR34 + = 31; + +106 +ICR35 + = 31; + +108 +ICR36 + = 31; + +110 +ICR37 + = 31; + +112 +ICR38 + = 31; + +114 +ICR39 + = 31; + +116 +ICR40 + = 31; + +118 +ICR41 + = 31; + +120 +ICR42 + = 31; + +122 +ICR43 + = 31; + +124 +ICR44 + = 31; + +126 +ICR45 + = 31; + +128 +ICR46 + = 31; + +130 +ICR47 + = 31; + +132 +ICR48 + = 31; + +134 +ICR49 + = 31; + +136 +ICR50 + = 31; + +138 +ICR51 + = 31; + +140 +ICR52 + = 31; + +142 +ICR53 + = 31; + +144 +ICR54 + = 31; + +146 +ICR55 + = 31; + +148 +ICR56 + = 31; + +150 +ICR57 + = 31; + +152 +ICR58 + = 31; + +154 +ICR59 + = 31; + +156 +ICR60 + = 31; + +158 +ICR61 + = 31; + +160 +ICR62 + = 31; + +162 +ICR63 + = 31; + +164 + } +} + +174 +__š‹¼u± +  +DeçuÉIRQHªdËr + (); + +175 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+ 35 + +209 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 36 + +210 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 37 + +211 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 38 + +212 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 39 + +213 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 40 + +214 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 41 + +215 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 42 + +216 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 43 + +217 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 44 + +218 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 45 + +219 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 46 + +220 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 47 + +221 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 48 + +222 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 49 + +223 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 50 + +224 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 51 + +225 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 52 + +226 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 53 + +227 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 54 + +228 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 55 + +229 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 56 + +230 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 57 + +231 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 58 + +232 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 59 + +233 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 60 + +234 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 61 + +235 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 62 + +236 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 63 + +237 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 64 + +238 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 65 + +239 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 66 + +240 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 67 + +241 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 68 + +242 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 69 + +243 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 70 + +244 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 71 + +245 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 72 + +246 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 73 + +247 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 74 + +248 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 75 + +249 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 76 + +250 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 77 + +251 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 78 + +252 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 79 + +253 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 80 + +254 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 81 + +255 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 82 + +256 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 83 + +257 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 84 + +258 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 85 + +259 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 86 + +260 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 87 + +261 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 88 + +262 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 89 + +263 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 90 + +264 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 91 + +265 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 92 + +266 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 93 + +267 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 94 + +268 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 95 + +269 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 96 + +270 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 97 + +271 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 98 + +272 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 99 + +273 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 100 + +274 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 101 + +275 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 102 + +276 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 103 + +277 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 104 + +278 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 105 + +279 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 106 + +280 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 107 + +281 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 108 + +282 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 109 + +283 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 110 + +284 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 111 + +285 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 112 + +286 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 113 + +287 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 114 + +288 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 115 + +289 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 116 + +290 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 117 + +291 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 118 + +292 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 119 + +293 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 120 + +294 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 121 + +295 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 122 + +296 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 123 + +297 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 124 + +298 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 125 + +299 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 126 + +300 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 127 + +301 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 128 + +302 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 129 + +303 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 130 + +304 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 131 + +305 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 132 + +306 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 133 + +307 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 134 + +308 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 135 + +309 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 136 + +310 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 137 + +311 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 138 + +312 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 139 + +313 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 140 + +314 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 141 + +315 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 142 + +316 #´agm¨ +štveù + +DeçuÉIRQHªdËr + 143 + +317 #´agm¨ +štveù + 0xFFFFFFFF 144 + +327 +__š‹¼u± + + +328  + $DeçuÉIRQHªdËr + () + +335 + `__DI +(); + +337 +HWWD_CL + = 0; + +339 + } +} + + @vectors.h + +13  +In™IrqLev–s +(); + + @ +1 +. +1 +/usr/include +9 +73 +Flash.c +Flash.h +MAIN.c +RLT.c +RLT.h +mb91465k.h +uart.c +vectors.c +vectors.h diff --git a/mb91465k.asm b/mb91465k.asm new file mode 100644 index 0000000..223f637 --- /dev/null +++ b/mb91465k.asm @@ -0,0 +1,14 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + mb91467d.asm + + + 1.00 UMa Initial Version +-----------------------------------------------------------------------------*/ + + +#define __IO_DEFINE +#include "mb91465k.h" diff --git a/mb91465k.h b/mb91465k.h new file mode 100644 index 0000000..0a9b916 --- /dev/null +++ b/mb91465k.h @@ -0,0 +1,15323 @@ +/* FR IO-MAP HEADER FILE */ +/* ===================== */ +/* CREATED BY IO-WIZARD V2.26 */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* */ +/* ************************************************************************* */ +/* Fujitsu Microelectronics Europe GmbH */ +/* Pittlerstrasse 47, 63225 Langen */ +/* Tel.: +49 (6103) 690-0, Fax -122 */ +/* */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* ---------------------------------------------------------------------- */ +/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */ +/* ---------------------------------------------------------------------- */ +/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */ +/* - removed LCD and Sound Controller */ +/* Id: MB91465K.h,v 1.4 2006/11/30 14:39:18 meffen Exp */ +/* - -added registers: ADER (32Bit access) */ +/* ADCS (16Bit access) */ +/* ADCR (16Bit access) */ +/* ADCT (16Bit access) */ + +/* ASSEMBLER DEFINITIONS : */ + +#ifdef __IO_DEFINE +#define __IO_EXTERN +#else +#define __IO_EXTERN extern volatile +#endif +#ifdef __IO_DEFINE +#pragma asm + .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19 + .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27 + .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1 + .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00 + .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00 + .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01 + .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02 + .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03 + .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04 + .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04 + .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001 + .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003 + .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0 + .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0 + .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11 + .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00 + .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01 + .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02 + .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03 + .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04 + .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05 + .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06 + .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07 + .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08 + .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09 + .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10 + .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11 + .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0 + .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0 + .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader + .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr + .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0 + .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1 + .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2 + .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3 + .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4 + .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6 + .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7 + .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1 + .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0 + .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3 + .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67 + .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67 + .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4 + .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7 + .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00 + .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06 + .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12 + .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18 + .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24 + .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30 + .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36 + .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42 + .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48 + .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54 + .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60 + .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr + .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm + .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1 + .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr + .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg + .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr + .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel + .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh + .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14 + .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20 + .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28 + .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18 + .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26 + .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16 + .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22 + .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14 + .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20 + .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29 + .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19 + .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27 + .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17 + .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24 + .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15 + .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21 + .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29 + .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19 + .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27 + .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17 + .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24 + .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0 + .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3 + .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt + .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0 + .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4 + .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124 + .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4 + .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24 + .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14 + .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124 + .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24 + .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14 + .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14 + .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24 + .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat + .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0 + .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6 + .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2 + +_pdr14 .EQU 0x00000E +PDR14 .EQU 0x00000E /* Port Data Register */ +_pdr15 .EQU 0x00000F +PDR15 .EQU 0x00000F +_pdr16 .EQU 0x000010 +PDR16 .EQU 0x000010 +_pdr17 .EQU 0x000011 +PDR17 .EQU 0x000011 +_pdr18 .EQU 0x000012 +PDR18 .EQU 0x000012 +_pdr19 .EQU 0x000013 +PDR19 .EQU 0x000013 +_pdr20 .EQU 0x000014 +PDR20 .EQU 0x000014 +_pdr21 .EQU 0x000015 +PDR21 .EQU 0x000015 +_pdr22 .EQU 0x000016 +PDR22 .EQU 0x000016 +_pdr24 .EQU 0x000018 +PDR24 .EQU 0x000018 +_pdr26 .EQU 0x00001A +PDR26 .EQU 0x00001A +_pdr27 .EQU 0x00001B +PDR27 .EQU 0x00001B +_pdr28 .EQU 0x00001C +PDR28 .EQU 0x00001C +_pdr29 .EQU 0x00001D +PDR29 .EQU 0x00001D +_eirr0 .EQU 0x000030 +EIRR0 .EQU 0x000030 /* External Interrupt 0-7 */ +_enir0 .EQU 0x000031 +ENIR0 .EQU 0x000031 +_elvr0 .EQU 0x000032 +ELVR0 .EQU 0x000032 +_eirr1 .EQU 0x000034 +EIRR1 .EQU 0x000034 /* External Interrupt 8-15 */ +_enir1 .EQU 0x000035 +ENIR1 .EQU 0x000035 +_elvr1 .EQU 0x000036 +ELVR1 .EQU 0x000036 +_dicr .EQU 0x000038 +DICR .EQU 0x000038 /* DLYI/I-unit */ +_hrcl .EQU 0x000039 +HRCL .EQU 0x000039 +_rbsync .EQU 0x00003A +RBSYNC .EQU 0x00003A /* R-Bus Sync */ +_scr00 .EQU 0x000040 +SCR00 .EQU 0x000040 /* USART (LIN) 0 */ +_smr00 .EQU 0x000041 +SMR00 .EQU 0x000041 +_ssr00 .EQU 0x000042 +SSR00 .EQU 0x000042 +_rdr00 .EQU 0x000043 +RDR00 .EQU 0x000043 +_tdr00 .EQU 0x000043 +TDR00 .EQU 0x000043 +_escr00 .EQU 0x000044 +ESCR00 .EQU 0x000044 +_eccr00 .EQU 0x000045 +ECCR00 .EQU 0x000045 +_scr01 .EQU 0x000048 +SCR01 .EQU 0x000048 /* USART (LIN) 1 */ +_smr01 .EQU 0x000049 +SMR01 .EQU 0x000049 +_ssr01 .EQU 0x00004A +SSR01 .EQU 0x00004A +_rdr01 .EQU 0x00004B +RDR01 .EQU 0x00004B +_tdr01 .EQU 0x00004B +TDR01 .EQU 0x00004B +_escr01 .EQU 0x00004C +ESCR01 .EQU 0x00004C +_eccr01 .EQU 0x00004D +ECCR01 .EQU 0x00004D +_scr02 .EQU 0x000050 +SCR02 .EQU 0x000050 /* USART (LIN) 2 */ +_smr02 .EQU 0x000051 +SMR02 .EQU 0x000051 +_ssr02 .EQU 0x000052 +SSR02 .EQU 0x000052 +_rdr02 .EQU 0x000053 +RDR02 .EQU 0x000053 +_tdr02 .EQU 0x000053 +TDR02 .EQU 0x000053 +_escr02 .EQU 0x000054 +ESCR02 .EQU 0x000054 +_eccr02 .EQU 0x000055 +ECCR02 .EQU 0x000055 +_scr03 .EQU 0x000058 +SCR03 .EQU 0x000058 /* USART (LIN) 3 */ +_smr03 .EQU 0x000059 +SMR03 .EQU 0x000059 +_ssr03 .EQU 0x00005A +SSR03 .EQU 0x00005A +_rdr03 .EQU 0x00005B +RDR03 .EQU 0x00005B +_tdr03 .EQU 0x00005B +TDR03 .EQU 0x00005B +_escr03 .EQU 0x00005C +ESCR03 .EQU 0x00005C +_eccr03 .EQU 0x00005D +ECCR03 .EQU 0x00005D +_scr04 .EQU 0x000060 +SCR04 .EQU 0x000060 /* USART (LIN) 4 with FIFO */ +_smr04 .EQU 0x000061 +SMR04 .EQU 0x000061 +_ssr04 .EQU 0x000062 +SSR04 .EQU 0x000062 +_rdr04 .EQU 0x000063 +RDR04 .EQU 0x000063 +_tdr04 .EQU 0x000063 +TDR04 .EQU 0x000063 +_escr04 .EQU 0x000064 +ESCR04 .EQU 0x000064 +_eccr04 .EQU 0x000065 +ECCR04 .EQU 0x000065 +_fsr04 .EQU 0x000066 +FSR04 .EQU 0x000066 +_fcr04 .EQU 0x000067 +FCR04 .EQU 0x000067 +_bgr00 .EQU 0x000080 +BGR00 .EQU 0x000080 /* Bauderate Generator USART (LIN) 0-7 */ +_bgr100 .EQU 0x000080 +BGR100 .EQU 0x000080 +_bgr000 .EQU 0x000081 +BGR000 .EQU 0x000081 +_bgr01 .EQU 0x000082 +BGR01 .EQU 0x000082 +_bgr101 .EQU 0x000082 +BGR101 .EQU 0x000082 +_bgr001 .EQU 0x000083 +BGR001 .EQU 0x000083 +_bgr02 .EQU 0x000084 +BGR02 .EQU 0x000084 +_bgr102 .EQU 0x000084 +BGR102 .EQU 0x000084 +_bgr002 .EQU 0x000085 +BGR002 .EQU 0x000085 +_bgr03 .EQU 0x000086 +BGR03 .EQU 0x000086 +_bgr103 .EQU 0x000086 +BGR103 .EQU 0x000086 +_bgr003 .EQU 0x000087 +BGR003 .EQU 0x000087 +_bgr04 .EQU 0x000088 +BGR04 .EQU 0x000088 +_bgr104 .EQU 0x000088 +BGR104 .EQU 0x000088 +_bgr004 .EQU 0x000089 +BGR004 .EQU 0x000089 +_ibcr0 .EQU 0x0000D0 +IBCR0 .EQU 0x0000D0 /* I2C 0 */ +_ibsr0 .EQU 0x0000D1 +IBSR0 .EQU 0x0000D1 +_itba0 .EQU 0x0000D2 +ITBA0 .EQU 0x0000D2 +_itbah0 .EQU 0x0000D2 +ITBAH0 .EQU 0x0000D2 +_itbal0 .EQU 0x0000D3 +ITBAL0 .EQU 0x0000D3 +_itmk0 .EQU 0x0000D4 +ITMK0 .EQU 0x0000D4 +_itmkh0 .EQU 0x0000D4 +ITMKH0 .EQU 0x0000D4 +_itmkl0 .EQU 0x0000D5 +ITMKL0 .EQU 0x0000D5 +_ismk0 .EQU 0x0000D6 +ISMK0 .EQU 0x0000D6 +_isba0 .EQU 0x0000D7 +ISBA0 .EQU 0x0000D7 +_idar0 .EQU 0x0000D9 +IDAR0 .EQU 0x0000D9 +_iccr0 .EQU 0x0000DA +ICCR0 .EQU 0x0000DA +_gcn10 .EQU 0x000100 +GCN10 .EQU 0x000100 /* PPG Control 0-3 */ +_gcn20 .EQU 0x000103 +GCN20 .EQU 0x000103 +_gcn11 .EQU 0x000104 +GCN11 .EQU 0x000104 /* PPG Control 4-7 */ +_gcn21 .EQU 0x000107 +GCN21 .EQU 0x000107 +_gcn12 .EQU 0x000108 +GCN12 .EQU 0x000108 /* PPG Control 8-11 */ +_gcn22 .EQU 0x00010B +GCN22 .EQU 0x00010B +_ptmr00 .EQU 0x000110 +PTMR00 .EQU 0x000110 /* PPG 0 */ +_pcsr00 .EQU 0x000112 +PCSR00 .EQU 0x000112 +_pdut00 .EQU 0x000114 +PDUT00 .EQU 0x000114 +_pcn00 .EQU 0x000116 +PCN00 .EQU 0x000116 +_pcnh00 .EQU 0x000116 +PCNH00 .EQU 0x000116 +_pcnl00 .EQU 0x000117 +PCNL00 .EQU 0x000117 +_ptmr01 .EQU 0x000118 +PTMR01 .EQU 0x000118 /* PPG 1 */ +_pcsr01 .EQU 0x00011A +PCSR01 .EQU 0x00011A +_pdut01 .EQU 0x00011C +PDUT01 .EQU 0x00011C +_pcn01 .EQU 0x00011E +PCN01 .EQU 0x00011E +_pcnh01 .EQU 0x00011E +PCNH01 .EQU 0x00011E +_pcnl01 .EQU 0x00011F +PCNL01 .EQU 0x00011F +_ptmr02 .EQU 0x000120 +PTMR02 .EQU 0x000120 /* PPG 2 */ +_pcsr02 .EQU 0x000122 +PCSR02 .EQU 0x000122 +_pdut02 .EQU 0x000124 +PDUT02 .EQU 0x000124 +_pcn02 .EQU 0x000126 +PCN02 .EQU 0x000126 +_pcnh02 .EQU 0x000126 +PCNH02 .EQU 0x000126 +_pcnl02 .EQU 0x000127 +PCNL02 .EQU 0x000127 +_ptmr03 .EQU 0x000128 +PTMR03 .EQU 0x000128 /* PPG 3 */ +_pcsr03 .EQU 0x00012A +PCSR03 .EQU 0x00012A +_pdut03 .EQU 0x00012C +PDUT03 .EQU 0x00012C +_pcn03 .EQU 0x00012E +PCN03 .EQU 0x00012E +_pcnh03 .EQU 0x00012E +PCNH03 .EQU 0x00012E +_pcnl03 .EQU 0x00012F +PCNL03 .EQU 0x00012F +_ptmr04 .EQU 0x000130 +PTMR04 .EQU 0x000130 /* PPG 4 */ +_pcsr04 .EQU 0x000132 +PCSR04 .EQU 0x000132 +_pdut04 .EQU 0x000134 +PDUT04 .EQU 0x000134 +_pcn04 .EQU 0x000136 +PCN04 .EQU 0x000136 +_pcnh04 .EQU 0x000136 +PCNH04 .EQU 0x000136 +_pcnl04 .EQU 0x000137 +PCNL04 .EQU 0x000137 +_ptmr05 .EQU 0x000138 +PTMR05 .EQU 0x000138 /* PPG 5 */ +_pcsr05 .EQU 0x00013A +PCSR05 .EQU 0x00013A +_pdut05 .EQU 0x00013C +PDUT05 .EQU 0x00013C +_pcn05 .EQU 0x00013E +PCN05 .EQU 0x00013E +_pcnh05 .EQU 0x00013E +PCNH05 .EQU 0x00013E +_pcnl05 .EQU 0x00013F +PCNL05 .EQU 0x00013F +_ptmr06 .EQU 0x000140 +PTMR06 .EQU 0x000140 /* PPG 6 */ +_pcsr06 .EQU 0x000142 +PCSR06 .EQU 0x000142 +_pdut06 .EQU 0x000144 +PDUT06 .EQU 0x000144 +_pcn06 .EQU 0x000146 +PCN06 .EQU 0x000146 +_pcnh06 .EQU 0x000146 +PCNH06 .EQU 0x000146 +_pcnl06 .EQU 0x000147 +PCNL06 .EQU 0x000147 +_ptmr07 .EQU 0x000148 +PTMR07 .EQU 0x000148 /* PPG 7 */ +_pcsr07 .EQU 0x00014A +PCSR07 .EQU 0x00014A +_pdut07 .EQU 0x00014C +PDUT07 .EQU 0x00014C +_pcn07 .EQU 0x00014E +PCN07 .EQU 0x00014E +_pcnh07 .EQU 0x00014E +PCNH07 .EQU 0x00014E +_pcnl07 .EQU 0x00014F +PCNL07 .EQU 0x00014F +_ptmr08 .EQU 0x000150 +PTMR08 .EQU 0x000150 /* PPG 8 */ +_pcsr08 .EQU 0x000152 +PCSR08 .EQU 0x000152 +_pdut08 .EQU 0x000154 +PDUT08 .EQU 0x000154 +_pcn08 .EQU 0x000156 +PCN08 .EQU 0x000156 +_pcnh08 .EQU 0x000156 +PCNH08 .EQU 0x000156 +_pcnl08 .EQU 0x000157 +PCNL08 .EQU 0x000157 +_ptmr09 .EQU 0x000158 +PTMR09 .EQU 0x000158 /* PPG 9 */ +_pcsr09 .EQU 0x00015A +PCSR09 .EQU 0x00015A +_pdut09 .EQU 0x00015C +PDUT09 .EQU 0x00015C +_pcn09 .EQU 0x00015E +PCN09 .EQU 0x00015E +_pcnh09 .EQU 0x00015E +PCNH09 .EQU 0x00015E +_pcnl09 .EQU 0x00015F +PCNL09 .EQU 0x00015F +_ptmr10 .EQU 0x000160 +PTMR10 .EQU 0x000160 /* PPG 10 */ +_pcsr10 .EQU 0x000162 +PCSR10 .EQU 0x000162 +_pdut10 .EQU 0x000164 +PDUT10 .EQU 0x000164 +_pcn10 .EQU 0x000166 +PCN10 .EQU 0x000166 +_pcnh10 .EQU 0x000166 +PCNH10 .EQU 0x000166 +_pcnl10 .EQU 0x000167 +PCNL10 .EQU 0x000167 +_ptmr11 .EQU 0x000168 +PTMR11 .EQU 0x000168 /* PPG 11 */ +_pcsr11 .EQU 0x00016A +PCSR11 .EQU 0x00016A +_pdut11 .EQU 0x00016C +PDUT11 .EQU 0x00016C +_pcn11 .EQU 0x00016E +PCN11 .EQU 0x00016E +_pcnh11 .EQU 0x00016E +PCNH11 .EQU 0x00016E +_pcnl11 .EQU 0x00016F +PCNL11 .EQU 0x00016F +_ics01 .EQU 0x000181 +ICS01 .EQU 0x000181 /* Input Capture 0-3 */ +_ics23 .EQU 0x000183 +ICS23 .EQU 0x000183 +_ipcp0 .EQU 0x000184 +IPCP0 .EQU 0x000184 +_ipcp1 .EQU 0x000186 +IPCP1 .EQU 0x000186 +_ipcp2 .EQU 0x000188 +IPCP2 .EQU 0x000188 +_ipcp3 .EQU 0x00018A +IPCP3 .EQU 0x00018A +_ocs01 .EQU 0x00018C +OCS01 .EQU 0x00018C /* Output Compare 0-3 */ +_ocs23 .EQU 0x00018E +OCS23 .EQU 0x00018E +_occp0 .EQU 0x000190 +OCCP0 .EQU 0x000190 +_occp1 .EQU 0x000192 +OCCP1 .EQU 0x000192 +_occp2 .EQU 0x000194 +OCCP2 .EQU 0x000194 +_occp3 .EQU 0x000196 +OCCP3 .EQU 0x000196 +_aderh .EQU 0x0001A0 +ADERH .EQU 0x0001A0 /* ADC */ +_aderl .EQU 0x0001A2 +ADERL .EQU 0x0001A2 +_ader .EQU 0x0001A0 +ADER .EQU 0x0001A0 +_adcs1 .EQU 0x0001A4 +ADCS1 .EQU 0x0001A4 +_adcs0 .EQU 0x0001A5 +ADCS0 .EQU 0x0001A5 +_adcs .EQU 0x0001A4 +ADCS .EQU 0x0001A4 +_adcr1 .EQU 0x0001A6 +ADCR1 .EQU 0x0001A6 +_adcr0 .EQU 0x0001A7 +ADCR0 .EQU 0x0001A7 +_adcr .EQU 0x0001A6 +ADCR .EQU 0x0001A6 +_adct1 .EQU 0x0001A8 +ADCT1 .EQU 0x0001A8 +_adct0 .EQU 0x0001A9 +ADCT0 .EQU 0x0001A9 +_adct .EQU 0x0001A8 +ADCT .EQU 0x0001A8 +_adsch .EQU 0x0001AA +ADSCH .EQU 0x0001AA +_adech .EQU 0x0001AB +ADECH .EQU 0x0001AB +_tmrlr0 .EQU 0x0001B0 +TMRLR0 .EQU 0x0001B0 /* Reload Timer 0 */ +_tmr0 .EQU 0x0001B2 +TMR0 .EQU 0x0001B2 +_tmcsr0 .EQU 0x0001B6 +TMCSR0 .EQU 0x0001B6 +_tmcsrh0 .EQU 0x0001B6 +TMCSRH0 .EQU 0x0001B6 +_tmcsrl0 .EQU 0x0001B7 +TMCSRL0 .EQU 0x0001B7 +_tmrlr1 .EQU 0x0001B8 +TMRLR1 .EQU 0x0001B8 /* Reload Timer 1 */ +_tmr1 .EQU 0x0001BA +TMR1 .EQU 0x0001BA +_tmcsr1 .EQU 0x0001BE +TMCSR1 .EQU 0x0001BE +_tmcsrh1 .EQU 0x0001BE +TMCSRH1 .EQU 0x0001BE +_tmcsrl1 .EQU 0x0001BF +TMCSRL1 .EQU 0x0001BF +_tmrlr2 .EQU 0x0001C0 +TMRLR2 .EQU 0x0001C0 /* Reload Timer 2 */ +_tmr2 .EQU 0x0001C2 +TMR2 .EQU 0x0001C2 +_tmcsr2 .EQU 0x0001C6 +TMCSR2 .EQU 0x0001C6 +_tmcsrh2 .EQU 0x0001C6 +TMCSRH2 .EQU 0x0001C6 +_tmcsrl2 .EQU 0x0001C7 +TMCSRL2 .EQU 0x0001C7 +_tmrlr3 .EQU 0x0001C8 +TMRLR3 .EQU 0x0001C8 /* Reload Timer 3 */ +_tmr3 .EQU 0x0001CA +TMR3 .EQU 0x0001CA +_tmcsr3 .EQU 0x0001CE +TMCSR3 .EQU 0x0001CE +_tmcsrh3 .EQU 0x0001CE +TMCSRH3 .EQU 0x0001CE +_tmcsrl3 .EQU 0x0001CF +TMCSRL3 .EQU 0x0001CF +_tmrlr4 .EQU 0x0001D0 +TMRLR4 .EQU 0x0001D0 /* Reload Timer 4 */ +_tmr4 .EQU 0x0001D2 +TMR4 .EQU 0x0001D2 +_tmcsr4 .EQU 0x0001D6 +TMCSR4 .EQU 0x0001D6 +_tmcsrh4 .EQU 0x0001D6 +TMCSRH4 .EQU 0x0001D6 +_tmcsrl4 .EQU 0x0001D7 +TMCSRL4 .EQU 0x0001D7 +_tmrlr5 .EQU 0x0001D8 +TMRLR5 .EQU 0x0001D8 /* Reload Timer 5 */ +_tmr5 .EQU 0x0001DA +TMR5 .EQU 0x0001DA +_tmcsr5 .EQU 0x0001DE +TMCSR5 .EQU 0x0001DE +_tmcsrh5 .EQU 0x0001DE +TMCSRH5 .EQU 0x0001DE +_tmcsrl5 .EQU 0x0001DF +TMCSRL5 .EQU 0x0001DF +_tmrlr6 .EQU 0x0001E0 +TMRLR6 .EQU 0x0001E0 /* Reload Timer 6 */ +_tmr6 .EQU 0x0001E2 +TMR6 .EQU 0x0001E2 +_tmcsr6 .EQU 0x0001E6 +TMCSR6 .EQU 0x0001E6 +_tmcsrh6 .EQU 0x0001E6 +TMCSRH6 .EQU 0x0001E6 +_tmcsrl6 .EQU 0x0001E7 +TMCSRL6 .EQU 0x0001E7 +_tmrlr7 .EQU 0x0001E8 +TMRLR7 .EQU 0x0001E8 /* Reload Timer 7 */ +_tmr7 .EQU 0x0001EA +TMR7 .EQU 0x0001EA +_tmcsr7 .EQU 0x0001EE +TMCSR7 .EQU 0x0001EE +_tmcsrh7 .EQU 0x0001EE +TMCSRH7 .EQU 0x0001EE +_tmcsrl7 .EQU 0x0001EF +TMCSRL7 .EQU 0x0001EF +_tcdt0 .EQU 0x0001F0 +TCDT0 .EQU 0x0001F0 /* Free Running Timer0 */ +_tccs0 .EQU 0x0001F3 +TCCS0 .EQU 0x0001F3 +_tcdt1 .EQU 0x0001F4 +TCDT1 .EQU 0x0001F4 /* Free Running Timer1 */ +_tccs1 .EQU 0x0001F7 +TCCS1 .EQU 0x0001F7 +_tcdt2 .EQU 0x0001F8 +TCDT2 .EQU 0x0001F8 /* Free Running Timer2 */ +_tccs2 .EQU 0x0001FB +TCCS2 .EQU 0x0001FB +_tcdt3 .EQU 0x0001FC +TCDT3 .EQU 0x0001FC /* Free Running Timer3 */ +_tccs3 .EQU 0x0001FF +TCCS3 .EQU 0x0001FF +_dmaca0 .EQU 0x000200 +DMACA0 .EQU 0x000200 /* DMAC */ +_dmacb0 .EQU 0x000204 +DMACB0 .EQU 0x000204 +_dmaca1 .EQU 0x000208 +DMACA1 .EQU 0x000208 +_dmacb1 .EQU 0x00020C +DMACB1 .EQU 0x00020C +_dmaca2 .EQU 0x000210 +DMACA2 .EQU 0x000210 +_dmacb2 .EQU 0x000214 +DMACB2 .EQU 0x000214 +_dmaca3 .EQU 0x000218 +DMACA3 .EQU 0x000218 +_dmacb3 .EQU 0x00021C +DMACB3 .EQU 0x00021C +_dmaca4 .EQU 0x000220 +DMACA4 .EQU 0x000220 +_dmacb4 .EQU 0x000224 +DMACB4 .EQU 0x000224 +_dmacr .EQU 0x000240 +DMACR .EQU 0x000240 +_ics45 .EQU 0x0002D1 +ICS45 .EQU 0x0002D1 /* Input Capture 4-7 */ +_ics67 .EQU 0x0002D3 +ICS67 .EQU 0x0002D3 +_ipcp4 .EQU 0x0002D4 +IPCP4 .EQU 0x0002D4 +_ipcp5 .EQU 0x0002D6 +IPCP5 .EQU 0x0002D6 +_ipcp6 .EQU 0x0002D8 +IPCP6 .EQU 0x0002D8 +_ipcp7 .EQU 0x0002DA +IPCP7 .EQU 0x0002DA +_ocs45 .EQU 0x0002DC +OCS45 .EQU 0x0002DC /* Output Compare 4-7 */ +_ocs67 .EQU 0x0002DE +OCS67 .EQU 0x0002DE +_occp4 .EQU 0x0002E0 +OCCP4 .EQU 0x0002E0 +_occp5 .EQU 0x0002E2 +OCCP5 .EQU 0x0002E2 +_occp6 .EQU 0x0002E4 +OCCP6 .EQU 0x0002E4 +_occp7 .EQU 0x0002E6 +OCCP7 .EQU 0x0002E6 +_tcdt4 .EQU 0x0002F0 +TCDT4 .EQU 0x0002F0 /* Free Running Timer4 */ +_tccs4 .EQU 0x0002F3 +TCCS4 .EQU 0x0002F3 +_tcdt5 .EQU 0x0002F4 +TCDT5 .EQU 0x0002F4 /* Free Running Timer5 */ +_tccs5 .EQU 0x0002F7 +TCCS5 .EQU 0x0002F7 +_tcdt6 .EQU 0x0002F8 +TCDT6 .EQU 0x0002F8 /* Free Running Timer6 */ +_tccs6 .EQU 0x0002FB +TCCS6 .EQU 0x0002FB +_tcdt7 .EQU 0x0002FC +TCDT7 .EQU 0x0002FC /* Free Running Timer7 */ +_tccs7 .EQU 0x0002FF +TCCS7 .EQU 0x0002FF +_roms .EQU 0x000390 +ROMS .EQU 0x000390 /* ROM Select Register */ +_bsd0 .EQU 0x0003F0 +BSD0 .EQU 0x0003F0 /* Bit Search Module */ +_bsd1 .EQU 0x0003F4 +BSD1 .EQU 0x0003F4 +_bsdc .EQU 0x0003F8 +BSDC .EQU 0x0003F8 +_bsrr .EQU 0x0003FC +BSRR .EQU 0x0003FC +_icr00 .EQU 0x000440 +ICR00 .EQU 0x000440 /* Interrupt Control Unit */ +_icr01 .EQU 0x000441 +ICR01 .EQU 0x000441 +_icr02 .EQU 0x000442 +ICR02 .EQU 0x000442 +_icr03 .EQU 0x000443 +ICR03 .EQU 0x000443 +_icr04 .EQU 0x000444 +ICR04 .EQU 0x000444 +_icr05 .EQU 0x000445 +ICR05 .EQU 0x000445 +_icr06 .EQU 0x000446 +ICR06 .EQU 0x000446 +_icr07 .EQU 0x000447 +ICR07 .EQU 0x000447 +_icr08 .EQU 0x000448 +ICR08 .EQU 0x000448 +_icr09 .EQU 0x000449 +ICR09 .EQU 0x000449 +_icr10 .EQU 0x00044A +ICR10 .EQU 0x00044A +_icr11 .EQU 0x00044B +ICR11 .EQU 0x00044B +_icr12 .EQU 0x00044C +ICR12 .EQU 0x00044C +_icr13 .EQU 0x00044D +ICR13 .EQU 0x00044D +_icr14 .EQU 0x00044E +ICR14 .EQU 0x00044E +_icr15 .EQU 0x00044F +ICR15 .EQU 0x00044F +_icr16 .EQU 0x000450 +ICR16 .EQU 0x000450 +_icr17 .EQU 0x000451 +ICR17 .EQU 0x000451 +_icr18 .EQU 0x000452 +ICR18 .EQU 0x000452 +_icr19 .EQU 0x000453 +ICR19 .EQU 0x000453 +_icr20 .EQU 0x000454 +ICR20 .EQU 0x000454 +_icr21 .EQU 0x000455 +ICR21 .EQU 0x000455 +_icr22 .EQU 0x000456 +ICR22 .EQU 0x000456 +_icr23 .EQU 0x000457 +ICR23 .EQU 0x000457 +_icr24 .EQU 0x000458 +ICR24 .EQU 0x000458 +_icr25 .EQU 0x000459 +ICR25 .EQU 0x000459 +_icr26 .EQU 0x00045A +ICR26 .EQU 0x00045A +_icr27 .EQU 0x00045B +ICR27 .EQU 0x00045B +_icr28 .EQU 0x00045C +ICR28 .EQU 0x00045C +_icr29 .EQU 0x00045D +ICR29 .EQU 0x00045D +_icr30 .EQU 0x00045E +ICR30 .EQU 0x00045E +_icr31 .EQU 0x00045F +ICR31 .EQU 0x00045F +_icr32 .EQU 0x000460 +ICR32 .EQU 0x000460 +_icr33 .EQU 0x000461 +ICR33 .EQU 0x000461 +_icr34 .EQU 0x000462 +ICR34 .EQU 0x000462 +_icr35 .EQU 0x000463 +ICR35 .EQU 0x000463 +_icr36 .EQU 0x000464 +ICR36 .EQU 0x000464 +_icr37 .EQU 0x000465 +ICR37 .EQU 0x000465 +_icr38 .EQU 0x000466 +ICR38 .EQU 0x000466 +_icr39 .EQU 0x000467 +ICR39 .EQU 0x000467 +_icr40 .EQU 0x000468 +ICR40 .EQU 0x000468 +_icr41 .EQU 0x000469 +ICR41 .EQU 0x000469 +_icr42 .EQU 0x00046A +ICR42 .EQU 0x00046A +_icr43 .EQU 0x00046B +ICR43 .EQU 0x00046B +_icr44 .EQU 0x00046C +ICR44 .EQU 0x00046C +_icr45 .EQU 0x00046D +ICR45 .EQU 0x00046D +_icr46 .EQU 0x00046E +ICR46 .EQU 0x00046E +_icr47 .EQU 0x00046F +ICR47 .EQU 0x00046F +_icr48 .EQU 0x000470 +ICR48 .EQU 0x000470 +_icr49 .EQU 0x000471 +ICR49 .EQU 0x000471 +_icr50 .EQU 0x000472 +ICR50 .EQU 0x000472 +_icr51 .EQU 0x000473 +ICR51 .EQU 0x000473 +_icr52 .EQU 0x000474 +ICR52 .EQU 0x000474 +_icr53 .EQU 0x000475 +ICR53 .EQU 0x000475 +_icr54 .EQU 0x000476 +ICR54 .EQU 0x000476 +_icr55 .EQU 0x000477 +ICR55 .EQU 0x000477 +_icr56 .EQU 0x000478 +ICR56 .EQU 0x000478 +_icr57 .EQU 0x000479 +ICR57 .EQU 0x000479 +_icr58 .EQU 0x00047A +ICR58 .EQU 0x00047A +_icr59 .EQU 0x00047B +ICR59 .EQU 0x00047B +_icr60 .EQU 0x00047C +ICR60 .EQU 0x00047C +_icr61 .EQU 0x00047D +ICR61 .EQU 0x00047D +_icr62 .EQU 0x00047E +ICR62 .EQU 0x00047E +_icr63 .EQU 0x00047F +ICR63 .EQU 0x00047F +_rsrr .EQU 0x000480 +RSRR .EQU 0x000480 /* Clock Control Unit */ +_stcr .EQU 0x000481 +STCR .EQU 0x000481 +_tbcr .EQU 0x000482 +TBCR .EQU 0x000482 +_ctbr .EQU 0x000483 +CTBR .EQU 0x000483 +_clkr .EQU 0x000484 +CLKR .EQU 0x000484 +_wpr .EQU 0x000485 +WPR .EQU 0x000485 +_divr0 .EQU 0x000486 +DIVR0 .EQU 0x000486 +_divr1 .EQU 0x000487 +DIVR1 .EQU 0x000487 +_plldivm .EQU 0x00048C +PLLDIVM .EQU 0x00048C /* PLL - Clock Gear Unit: */ +_plldivn .EQU 0x00048D +PLLDIVN .EQU 0x00048D +_plldivg .EQU 0x00048E +PLLDIVG .EQU 0x00048E +_pllmulg .EQU 0x00048F +PLLMULG .EQU 0x00048F +_pllctrl .EQU 0x000490 +PLLCTRL .EQU 0x000490 +_oscc1 .EQU 0x000494 +OSCC1 .EQU 0x000494 /* Main/Sub Oscillator Control */ +_oscs1 .EQU 0x000495 +OSCS1 .EQU 0x000495 +_oscc2 .EQU 0x000496 +OSCC2 .EQU 0x000496 +_oscs2 .EQU 0x000497 +OSCS2 .EQU 0x000497 +_porten .EQU 0x000498 +PORTEN .EQU 0x000498 /* Port Input Enable Control */ +_wtcer .EQU 0x0004A1 +WTCER .EQU 0x0004A1 /* Real Time Clock (Watch Timer) */ +_wtcr .EQU 0x0004A2 +WTCR .EQU 0x0004A2 +_wtbr .EQU 0x0004A4 +WTBR .EQU 0x0004A4 +_wthr .EQU 0x0004A8 +WTHR .EQU 0x0004A8 +_wtmr .EQU 0x0004A9 +WTMR .EQU 0x0004A9 +_wtsr .EQU 0x0004AA +WTSR .EQU 0x0004AA +_csvtr .EQU 0x0004AC +CSVTR .EQU 0x0004AC /* Clock-Supervisor / Selecor / Monitor */ +_csvcr .EQU 0x0004AD +CSVCR .EQU 0x0004AD +_cscfg .EQU 0x0004AE +CSCFG .EQU 0x0004AE +_cmcfg .EQU 0x0004AF +CMCFG .EQU 0x0004AF +_cucr .EQU 0x0004B0 +CUCR .EQU 0x0004B0 /* Calibration Unit of Sub Oszillation */ +_cutd .EQU 0x0004B2 +CUTD .EQU 0x0004B2 +_cutr1 .EQU 0x0004B4 +CUTR1 .EQU 0x0004B4 +_cutr2 .EQU 0x0004B6 +CUTR2 .EQU 0x0004B6 +_cmpr .EQU 0x0004B8 +CMPR .EQU 0x0004B8 /* Clock Modulator */ +_cmcr .EQU 0x0004BB +CMCR .EQU 0x0004BB +_cmt1 .EQU 0x0004BC +CMT1 .EQU 0x0004BC +_cmt2 .EQU 0x0004BE +CMT2 .EQU 0x0004BE +_canpre .EQU 0x0004C0 +CANPRE .EQU 0x0004C0 /* CAN clock control */ +_canckd .EQU 0x0004C1 +CANCKD .EQU 0x0004C1 +_lvsel .EQU 0x0004C4 +LVSEL .EQU 0x0004C4 /* LV Detection / Hardware-Watchdog */ +_lvdet .EQU 0x0004C5 +LVDET .EQU 0x0004C5 +_hwwde .EQU 0x0004C6 +HWWDE .EQU 0x0004C6 +_hwwd .EQU 0x0004C7 +HWWD .EQU 0x0004C7 +_oscrh .EQU 0x0004C8 +OSCRH .EQU 0x0004C8 /* Main-/Sub-Oscillatio Stabilization Timer */ +_oscrl .EQU 0x0004C9 +OSCRL .EQU 0x0004C9 +_wpcrh .EQU 0x0004CA +WPCRH .EQU 0x0004CA +_wpcrl .EQU 0x0004CB +WPCRL .EQU 0x0004CB +_osccr .EQU 0x0004CC +OSCCR .EQU 0x0004CC /* Main-/Sub-Oscillatio Standby Control */ +_regsel .EQU 0x0004CE +REGSEL .EQU 0x0004CE +_regctr .EQU 0x0004CF +REGCTR .EQU 0x0004CF +_modr .EQU 0x0007FD +MODR .EQU 0x0007FD /* Mode Register */ +_pdrd14 .EQU 0x000D0E +PDRD14 .EQU 0x000D0E /* R-bus Port Data Direct Read Register */ +_pdrd15 .EQU 0x000D0F +PDRD15 .EQU 0x000D0F +_pdrd16 .EQU 0x000D10 +PDRD16 .EQU 0x000D10 +_pdrd17 .EQU 0x000D11 +PDRD17 .EQU 0x000D11 +_pdrd18 .EQU 0x000D12 +PDRD18 .EQU 0x000D12 +_pdrd19 .EQU 0x000D13 +PDRD19 .EQU 0x000D13 +_pdrd20 .EQU 0x000D14 +PDRD20 .EQU 0x000D14 +_pdrd21 .EQU 0x000D15 +PDRD21 .EQU 0x000D15 +_pdrd22 .EQU 0x000D16 +PDRD22 .EQU 0x000D16 +_pdrd24 .EQU 0x000D18 +PDRD24 .EQU 0x000D18 +_pdrd26 .EQU 0x000D1A +PDRD26 .EQU 0x000D1A +_pdrd27 .EQU 0x000D1B +PDRD27 .EQU 0x000D1B +_pdrd28 .EQU 0x000D1C +PDRD28 .EQU 0x000D1C +_pdrd29 .EQU 0x000D1D +PDRD29 .EQU 0x000D1D +_ddr14 .EQU 0x000D4E +DDR14 .EQU 0x000D4E /* R-bus Port Direction Register */ +_ddr15 .EQU 0x000D4F +DDR15 .EQU 0x000D4F +_ddr16 .EQU 0x000D50 +DDR16 .EQU 0x000D50 +_ddr17 .EQU 0x000D51 +DDR17 .EQU 0x000D51 +_ddr18 .EQU 0x000D52 +DDR18 .EQU 0x000D52 +_ddr19 .EQU 0x000D53 +DDR19 .EQU 0x000D53 +_ddr20 .EQU 0x000D54 +DDR20 .EQU 0x000D54 +_ddr21 .EQU 0x000D55 +DDR21 .EQU 0x000D55 +_ddr22 .EQU 0x000D56 +DDR22 .EQU 0x000D56 +_ddr24 .EQU 0x000D58 +DDR24 .EQU 0x000D58 +_ddr26 .EQU 0x000D5A +DDR26 .EQU 0x000D5A +_ddr27 .EQU 0x000D5B +DDR27 .EQU 0x000D5B +_ddr28 .EQU 0x000D5C +DDR28 .EQU 0x000D5C +_ddr29 .EQU 0x000D5D +DDR29 .EQU 0x000D5D +_pfr14 .EQU 0x000D8E +PFR14 .EQU 0x000D8E /* R-bus Port Function Register */ +_pfr15 .EQU 0x000D8F +PFR15 .EQU 0x000D8F +_pfr16 .EQU 0x000D90 +PFR16 .EQU 0x000D90 +_pfr17 .EQU 0x000D91 +PFR17 .EQU 0x000D91 +_pfr18 .EQU 0x000D92 +PFR18 .EQU 0x000D92 +_pfr19 .EQU 0x000D93 +PFR19 .EQU 0x000D93 +_pfr20 .EQU 0x000D94 +PFR20 .EQU 0x000D94 +_pfr21 .EQU 0x000D95 +PFR21 .EQU 0x000D95 +_pfr22 .EQU 0x000D96 +PFR22 .EQU 0x000D96 +_pfr24 .EQU 0x000D98 +PFR24 .EQU 0x000D98 +_pfr26 .EQU 0x000D9A +PFR26 .EQU 0x000D9A +_pfr27 .EQU 0x000D9B +PFR27 .EQU 0x000D9B +_pfr28 .EQU 0x000D9C +PFR28 .EQU 0x000D9C +_pfr29 .EQU 0x000D9D +PFR29 .EQU 0x000D9D +_epfr14 .EQU 0x000DCE +EPFR14 .EQU 0x000DCE /* R-bus Port Extra Function Register */ +_epfr15 .EQU 0x000DCF +EPFR15 .EQU 0x000DCF +_epfr16 .EQU 0x000DD0 +EPFR16 .EQU 0x000DD0 +_epfr17 .EQU 0x000DD1 +EPFR17 .EQU 0x000DD1 +_epfr18 .EQU 0x000DD2 +EPFR18 .EQU 0x000DD2 +_epfr19 .EQU 0x000DD3 +EPFR19 .EQU 0x000DD3 +_epfr20 .EQU 0x000DD4 +EPFR20 .EQU 0x000DD4 +_epfr21 .EQU 0x000DD5 +EPFR21 .EQU 0x000DD5 +_epfr22 .EQU 0x000DD6 +EPFR22 .EQU 0x000DD6 +_epfr24 .EQU 0x000DD8 +EPFR24 .EQU 0x000DD8 +_epfr26 .EQU 0x000DDA +EPFR26 .EQU 0x000DDA +_epfr27 .EQU 0x000DDB +EPFR27 .EQU 0x000DDB +_epfr29 .EQU 0x000DDD +EPFR29 .EQU 0x000DDD +_podr14 .EQU 0x000E0E +PODR14 .EQU 0x000E0E /* R-bus Port Output Drive Select Register */ +_podr15 .EQU 0x000E0F +PODR15 .EQU 0x000E0F +_podr16 .EQU 0x000E10 +PODR16 .EQU 0x000E10 +_podr17 .EQU 0x000E11 +PODR17 .EQU 0x000E11 +_podr18 .EQU 0x000E12 +PODR18 .EQU 0x000E12 +_podr19 .EQU 0x000E13 +PODR19 .EQU 0x000E13 +_podr20 .EQU 0x000E14 +PODR20 .EQU 0x000E14 +_podr21 .EQU 0x000E15 +PODR21 .EQU 0x000E15 +_podr22 .EQU 0x000E16 +PODR22 .EQU 0x000E16 +_podr24 .EQU 0x000E18 +PODR24 .EQU 0x000E18 +_podr26 .EQU 0x000E1A +PODR26 .EQU 0x000E1A +_podr27 .EQU 0x000E1B +PODR27 .EQU 0x000E1B +_podr28 .EQU 0x000E1C +PODR28 .EQU 0x000E1C +_podr29 .EQU 0x000E1D +PODR29 .EQU 0x000E1D +_pilr14 .EQU 0x000E4E +PILR14 .EQU 0x000E4E /* R-bus Port Input Level Select Register */ +_pilr15 .EQU 0x000E4F +PILR15 .EQU 0x000E4F +_pilr16 .EQU 0x000E50 +PILR16 .EQU 0x000E50 +_pilr17 .EQU 0x000E51 +PILR17 .EQU 0x000E51 +_pilr18 .EQU 0x000E52 +PILR18 .EQU 0x000E52 +_pilr19 .EQU 0x000E53 +PILR19 .EQU 0x000E53 +_pilr20 .EQU 0x000E54 +PILR20 .EQU 0x000E54 +_pilr21 .EQU 0x000E55 +PILR21 .EQU 0x000E55 +_pilr22 .EQU 0x000E56 +PILR22 .EQU 0x000E56 +_pilr24 .EQU 0x000E58 +PILR24 .EQU 0x000E58 +_pilr26 .EQU 0x000E5A +PILR26 .EQU 0x000E5A +_pilr27 .EQU 0x000E5B +PILR27 .EQU 0x000E5B +_pilr28 .EQU 0x000E5C +PILR28 .EQU 0x000E5C +_pilr29 .EQU 0x000E5D +PILR29 .EQU 0x000E5D +_epilr14 .EQU 0x000E8E +EPILR14 .EQU 0x000E8E /* R-bus Port Extra Input Level Select Register */ +_epilr15 .EQU 0x000E8F +EPILR15 .EQU 0x000E8F +_epilr16 .EQU 0x000E90 +EPILR16 .EQU 0x000E90 +_epilr17 .EQU 0x000E91 +EPILR17 .EQU 0x000E91 +_epilr18 .EQU 0x000E92 +EPILR18 .EQU 0x000E92 +_epilr19 .EQU 0x000E93 +EPILR19 .EQU 0x000E93 +_epilr20 .EQU 0x000E94 +EPILR20 .EQU 0x000E94 +_epilr21 .EQU 0x000E95 +EPILR21 .EQU 0x000E95 +_epilr22 .EQU 0x000E96 +EPILR22 .EQU 0x000E96 +_epilr24 .EQU 0x000E98 +EPILR24 .EQU 0x000E98 +_epilr26 .EQU 0x000E9A +EPILR26 .EQU 0x000E9A +_epilr27 .EQU 0x000E9B +EPILR27 .EQU 0x000E9B +_epilr28 .EQU 0x000E9C +EPILR28 .EQU 0x000E9C +_epilr29 .EQU 0x000E9D +EPILR29 .EQU 0x000E9D +_pper14 .EQU 0x000ECE +PPER14 .EQU 0x000ECE /* R-bus Port Pull-Up/Down Enable Register */ +_pper15 .EQU 0x000ECF +PPER15 .EQU 0x000ECF +_pper16 .EQU 0x000ED0 +PPER16 .EQU 0x000ED0 +_pper17 .EQU 0x000ED1 +PPER17 .EQU 0x000ED1 +_pper18 .EQU 0x000ED1 +PPER18 .EQU 0x000ED1 +_pper19 .EQU 0x000ED2 +PPER19 .EQU 0x000ED2 +_pper20 .EQU 0x000ED4 +PPER20 .EQU 0x000ED4 +_pper21 .EQU 0x000ED5 +PPER21 .EQU 0x000ED5 +_pper22 .EQU 0x000ED6 +PPER22 .EQU 0x000ED6 +_pper24 .EQU 0x000ED8 +PPER24 .EQU 0x000ED8 +_pper26 .EQU 0x000EDA +PPER26 .EQU 0x000EDA +_pper27 .EQU 0x000EDB +PPER27 .EQU 0x000EDB +_pper28 .EQU 0x000EDC +PPER28 .EQU 0x000EDC +_pper29 .EQU 0x000EDD +PPER29 .EQU 0x000EDD +_ppcr14 .EQU 0x000F0E +PPCR14 .EQU 0x000F0E /* R-bus Port Pull-Up/Down Control Register */ +_ppcr15 .EQU 0x000F0F +PPCR15 .EQU 0x000F0F +_ppcr16 .EQU 0x000F10 +PPCR16 .EQU 0x000F10 +_ppcr17 .EQU 0x000F11 +PPCR17 .EQU 0x000F11 +_ppcr18 .EQU 0x000F12 +PPCR18 .EQU 0x000F12 +_ppcr19 .EQU 0x000F13 +PPCR19 .EQU 0x000F13 +_ppcr20 .EQU 0x000F14 +PPCR20 .EQU 0x000F14 +_ppcr21 .EQU 0x000F15 +PPCR21 .EQU 0x000F15 +_ppcr22 .EQU 0x000F16 +PPCR22 .EQU 0x000F16 +_ppcr24 .EQU 0x000F18 +PPCR24 .EQU 0x000F18 +_ppcr26 .EQU 0x000F1A +PPCR26 .EQU 0x000F1A +_ppcr27 .EQU 0x000F1B +PPCR27 .EQU 0x000F1B +_ppcr28 .EQU 0x000F1C +PPCR28 .EQU 0x000F1C +_ppcr29 .EQU 0x000F1D +PPCR29 .EQU 0x000F1D +_dmasa0 .EQU 0x001000 +DMASA0 .EQU 0x001000 /* DMAC */ +_dmada0 .EQU 0x001004 +DMADA0 .EQU 0x001004 +_dmasa1 .EQU 0x001008 +DMASA1 .EQU 0x001008 +_dmada1 .EQU 0x00100C +DMADA1 .EQU 0x00100C +_dmasa2 .EQU 0x001010 +DMASA2 .EQU 0x001010 +_dmada2 .EQU 0x001014 +DMADA2 .EQU 0x001014 +_dmasa3 .EQU 0x001018 +DMASA3 .EQU 0x001018 +_dmada3 .EQU 0x00101C +DMADA3 .EQU 0x00101C +_dmasa4 .EQU 0x001020 +DMASA4 .EQU 0x001020 +_dmada4 .EQU 0x001024 +DMADA4 .EQU 0x001024 +_fmcs .EQU 0x007000 +FMCS .EQU 0x007000 /* Flash Memory/I-Cache Control Register */ +_fmcr .EQU 0x007001 +FMCR .EQU 0x007001 +_fchcr .EQU 0x007002 +FCHCR .EQU 0x007002 +_fmwt .EQU 0x007004 +FMWT .EQU 0x007004 +_fmwt2 .EQU 0x007006 +FMWT2 .EQU 0x007006 +_fmps .EQU 0x007007 +FMPS .EQU 0x007007 +_fmac .EQU 0x007008 +FMAC .EQU 0x007008 +_fcha0 .EQU 0x00700C +FCHA0 .EQU 0x00700C /* I_Cache Nonchachable area settings Register */ +_fcha1 .EQU 0x007010 +FCHA1 .EQU 0x007010 +_fscr0 .EQU 0x007100 +FSCR0 .EQU 0x007100 /* Flash Security Control Register */ +_fscr1 .EQU 0x007104 +FSCR1 .EQU 0x007104 +_ctrlr4 .EQU 0x00C400 +CTRLR4 .EQU 0x00C400 /* CAN 4 Control Register */ +_statr4 .EQU 0x00C402 +STATR4 .EQU 0x00C402 +_errcnt4 .EQU 0x00C404 +ERRCNT4 .EQU 0x00C404 +_btr4 .EQU 0x00C406 +BTR4 .EQU 0x00C406 +_intr4 .EQU 0x00C408 +INTR4 .EQU 0x00C408 +_testr4 .EQU 0x00C40A +TESTR4 .EQU 0x00C40A +_brper4 .EQU 0x00C40C +BRPER4 .EQU 0x00C40C +_brpe4 .EQU 0x00C40C +BRPE4 .EQU 0x00C40C +_if1creq4 .EQU 0x00C410 +IF1CREQ4 .EQU 0x00C410 /* CAN 4 IF 1 */ +_if1cmsk4 .EQU 0x00C412 +IF1CMSK4 .EQU 0x00C412 +_if1msk124 .EQU 0x00C414 +IF1MSK124 .EQU 0x00C414 +_if1msk24 .EQU 0x00C414 +IF1MSK24 .EQU 0x00C414 +_if1msk14 .EQU 0x00C416 +IF1MSK14 .EQU 0x00C416 +_if1arb124 .EQU 0x00C418 +IF1ARB124 .EQU 0x00C418 +_if1arb24 .EQU 0x00C418 +IF1ARB24 .EQU 0x00C418 +_if1arb14 .EQU 0x00C41A +IF1ARB14 .EQU 0x00C41A +_if1mctr4 .EQU 0x00C41C +IF1MCTR4 .EQU 0x00C41C +_if1dta124 .EQU 0x00C420 +IF1DTA124 .EQU 0x00C420 +_if1dta14 .EQU 0x00C420 +IF1DTA14 .EQU 0x00C420 +_if1dta24 .EQU 0x00C422 +IF1DTA24 .EQU 0x00C422 +_if1dtb124 .EQU 0x00C424 +IF1DTB124 .EQU 0x00C424 +_if1dtb14 .EQU 0x00C424 +IF1DTB14 .EQU 0x00C424 +_if1dtb24 .EQU 0x00C426 +IF1DTB24 .EQU 0x00C426 +_if1dta_swp124 .EQU 0x00C430 +IF1DTA_SWP124 .EQU 0x00C430 +_if1dta_swp24 .EQU 0x00C430 +IF1DTA_SWP24 .EQU 0x00C430 +_if1dta_swp14 .EQU 0x00C432 +IF1DTA_SWP14 .EQU 0x00C432 +_if1dtb_swp124 .EQU 0x00C434 +IF1DTB_SWP124 .EQU 0x00C434 +_if1dtb_swp24 .EQU 0x00C434 +IF1DTB_SWP24 .EQU 0x00C434 +_if1dtb_swp14 .EQU 0x00C436 +IF1DTB_SWP14 .EQU 0x00C436 +_if2creq4 .EQU 0x00C440 +IF2CREQ4 .EQU 0x00C440 /* CAN 4 IF 2 */ +_if2cmsk4 .EQU 0x00C442 +IF2CMSK4 .EQU 0x00C442 +_if2msk124 .EQU 0x00C444 +IF2MSK124 .EQU 0x00C444 +_if2msk24 .EQU 0x00C444 +IF2MSK24 .EQU 0x00C444 +_if2msk14 .EQU 0x00C446 +IF2MSK14 .EQU 0x00C446 +_if2arb124 .EQU 0x00C448 +IF2ARB124 .EQU 0x00C448 +_if2arb24 .EQU 0x00C448 +IF2ARB24 .EQU 0x00C448 +_if2arb14 .EQU 0x00C44A +IF2ARB14 .EQU 0x00C44A +_if2mctr4 .EQU 0x00C44C +IF2MCTR4 .EQU 0x00C44C +_if2dta124 .EQU 0x00C450 +IF2DTA124 .EQU 0x00C450 +_if2dta14 .EQU 0x00C450 +IF2DTA14 .EQU 0x00C450 +_if2dta24 .EQU 0x00C452 +IF2DTA24 .EQU 0x00C452 +_if2dtb124 .EQU 0x00C454 +IF2DTB124 .EQU 0x00C454 +_if2dtb14 .EQU 0x00C454 +IF2DTB14 .EQU 0x00C454 +_if2dtb24 .EQU 0x00C456 +IF2DTB24 .EQU 0x00C456 +_if2dta_swp124 .EQU 0x00C460 +IF2DTA_SWP124 .EQU 0x00C460 +_if2dta_swp24 .EQU 0x00C460 +IF2DTA_SWP24 .EQU 0x00C460 +_if2dta_swp14 .EQU 0x00C462 +IF2DTA_SWP14 .EQU 0x00C462 +_if2dtb_swp124 .EQU 0x00C464 +IF2DTB_SWP124 .EQU 0x00C464 +_if2dtb_swp24 .EQU 0x00C464 +IF2DTB_SWP24 .EQU 0x00C464 +_if2dtb_swp14 .EQU 0x00C466 +IF2DTB_SWP14 .EQU 0x00C466 +_treqr124 .EQU 0x00C480 +TREQR124 .EQU 0x00C480 /* CAN 4 Status Flags */ +_treqr24 .EQU 0x00C480 +TREQR24 .EQU 0x00C480 +_treqr14 .EQU 0x00C482 +TREQR14 .EQU 0x00C482 +_treqr344 .EQU 0x00C484 +TREQR344 .EQU 0x00C484 +_newdt124 .EQU 0x00C490 +NEWDT124 .EQU 0x00C490 +_newdt24 .EQU 0x00C490 +NEWDT24 .EQU 0x00C490 +_newdt14 .EQU 0x00C492 +NEWDT14 .EQU 0x00C492 +_intpnd124 .EQU 0x00C4A0 +INTPND124 .EQU 0x00C4A0 +_intpnd24 .EQU 0x00C4A0 +INTPND24 .EQU 0x00C4A0 +_intpnd14 .EQU 0x00C4A2 +INTPND14 .EQU 0x00C4A2 +_msgval124 .EQU 0x00C4B0 +MSGVAL124 .EQU 0x00C4B0 +_msgval24 .EQU 0x00C4B0 +MSGVAL24 .EQU 0x00C4B0 +_msgval14 .EQU 0x00C4B2 +MSGVAL14 .EQU 0x00C4B2 +_bctrl .EQU 0x00F000 +BCTRL .EQU 0x00F000 /* EDSU/MPU Registers */ +_bstat .EQU 0x00F004 +BSTAT .EQU 0x00F004 +_biac .EQU 0x00F008 +BIAC .EQU 0x00F008 +_boac .EQU 0x00F00C +BOAC .EQU 0x00F00C +_birq .EQU 0x00F010 +BIRQ .EQU 0x00F010 +_bcr0 .EQU 0x00F020 +BCR0 .EQU 0x00F020 +_bcr1 .EQU 0x00F024 +BCR1 .EQU 0x00F024 +_bad0 .EQU 0x00F080 +BAD0 .EQU 0x00F080 +_bad1 .EQU 0x00F084 +BAD1 .EQU 0x00F084 +_bad2 .EQU 0x00F088 +BAD2 .EQU 0x00F088 +_bad3 .EQU 0x00F08C +BAD3 .EQU 0x00F08C +_bad4 .EQU 0x00F090 +BAD4 .EQU 0x00F090 +_bad5 .EQU 0x00F094 +BAD5 .EQU 0x00F094 +_bad6 .EQU 0x00F098 +BAD6 .EQU 0x00F098 +_bad7 .EQU 0x00F09C +BAD7 .EQU 0x00F09C +_fsv1 .EQU 0x148000 +FSV1 .EQU 0x148000 /* FSV & BSV Registers */ +_bsv1 .EQU 0x148004 +BSV1 .EQU 0x148004 +_fsv2 .EQU 0x148008 +FSV2 .EQU 0x148008 +_bsv2 .EQU 0x14800C +BSV2 .EQU 0x14800C +#pragma endasm +#else + +#ifndef _MB91XXX_H +#define _MB91XXX_H + +#ifdef __FASM__ +#pragma asm + .IMPORT _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19 + .IMPORT _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27 + .IMPORT _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1 + .IMPORT _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00 + .IMPORT _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00 + .IMPORT _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01 + .IMPORT _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02 + .IMPORT _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03 + .IMPORT _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04 + .IMPORT _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04 + .IMPORT _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001 + .IMPORT _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003 + .IMPORT _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0 + .IMPORT _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0 + .IMPORT _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11 + .IMPORT _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00 + .IMPORT _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01 + .IMPORT _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02 + .IMPORT _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03 + .IMPORT _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04 + .IMPORT _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05 + .IMPORT _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06 + .IMPORT _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07 + .IMPORT _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08 + .IMPORT _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09 + .IMPORT _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10 + .IMPORT _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11 + .IMPORT _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0 + .IMPORT _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0 + .IMPORT _occp1, _occp2, _occp3, _aderh, _aderl, _ader + .IMPORT _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr + .IMPORT _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0 + .IMPORT _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1 + .IMPORT _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2 + .IMPORT _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3 + .IMPORT _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4 + .IMPORT _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6 + .IMPORT _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7 + .IMPORT _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1 + .IMPORT _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0 + .IMPORT _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3 + .IMPORT _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67 + .IMPORT _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67 + .IMPORT _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4 + .IMPORT _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7 + .IMPORT _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00 + .IMPORT _icr01, _icr02, _icr03, _icr04, _icr05, _icr06 + .IMPORT _icr07, _icr08, _icr09, _icr10, _icr11, _icr12 + .IMPORT _icr13, _icr14, _icr15, _icr16, _icr17, _icr18 + .IMPORT _icr19, _icr20, _icr21, _icr22, _icr23, _icr24 + .IMPORT _icr25, _icr26, _icr27, _icr28, _icr29, _icr30 + .IMPORT _icr31, _icr32, _icr33, _icr34, _icr35, _icr36 + .IMPORT _icr37, _icr38, _icr39, _icr40, _icr41, _icr42 + .IMPORT _icr43, _icr44, _icr45, _icr46, _icr47, _icr48 + .IMPORT _icr49, _icr50, _icr51, _icr52, _icr53, _icr54 + .IMPORT _icr55, _icr56, _icr57, _icr58, _icr59, _icr60 + .IMPORT _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr + .IMPORT _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm + .IMPORT _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1 + .IMPORT _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr + .IMPORT _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg + .IMPORT _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr + .IMPORT _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel + .IMPORT _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh + .IMPORT _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14 + .IMPORT _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20 + .IMPORT _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28 + .IMPORT _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18 + .IMPORT _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26 + .IMPORT _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16 + .IMPORT _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22 + .IMPORT _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14 + .IMPORT _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20 + .IMPORT _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29 + .IMPORT _podr14, _podr15, _podr16, _podr17, _podr18, _podr19 + .IMPORT _podr20, _podr21, _podr22, _podr24, _podr26, _podr27 + .IMPORT _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17 + .IMPORT _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24 + .IMPORT _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15 + .IMPORT _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21 + .IMPORT _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29 + .IMPORT _pper14, _pper15, _pper16, _pper17, _pper18, _pper19 + .IMPORT _pper20, _pper21, _pper22, _pper24, _pper26, _pper27 + .IMPORT _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17 + .IMPORT _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24 + .IMPORT _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0 + .IMPORT _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3 + .IMPORT _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt + .IMPORT _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0 + .IMPORT _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4 + .IMPORT _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124 + .IMPORT _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4 + .IMPORT _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24 + .IMPORT _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14 + .IMPORT _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124 + .IMPORT _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24 + .IMPORT _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14 + .IMPORT _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14 + .IMPORT _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24 + .IMPORT _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat + .IMPORT _biac, _boac, _birq, _bcr0, _bcr1, _bad0 + .IMPORT _bad1, _bad2, _bad3, _bad4, _bad5, _bad6 + .IMPORT _bad7, _fsv1, _bsv1, _fsv2, _bsv2 +#pragma endasm +#else /* __FASM__ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* */ +/* ************************************************************************* */ +/* Fujitsu Microelectronics Europe GmbH */ +/* Pittlerstrasse 47, 63225 Langen */ +/* Tel.: +49 (6103) 690-0, Fax -122 */ +/* */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* ---------------------------------------------------------------------- */ +/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */ +/* ---------------------------------------------------------------------- */ +/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */ +/* - removed LCD and Sound Controller */ +/* Id: MB91465K.iow,v 1.5 2006/11/30 14:39:18 meffen Exp */ +/* - format of comment lines adapted */ +/* BIT-STRUCTURE-DEFINITIONS */ + +typedef unsigned char IO_BYTE; +typedef unsigned short IO_WORD; +typedef unsigned long IO_LWORD; +typedef const unsigned short IO_WORD_READ; + +typedef union{ /* Port Data Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR29STR; +typedef union{ /* External Interrupt 0-7 */ + IO_BYTE byte; + struct{ + IO_BYTE _ER7 :1; + IO_BYTE _ER6 :1; + IO_BYTE _ER5 :1; + IO_BYTE _ER4 :1; + IO_BYTE _ER3 :1; + IO_BYTE _ER2 :1; + IO_BYTE _ER1 :1; + IO_BYTE _ER0 :1; + }bit; + }EIRR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN7 :1; + IO_BYTE _EN6 :1; + IO_BYTE _EN5 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }ENIR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LB7 :1; + IO_WORD _LA7 :1; + IO_WORD _LB6 :1; + IO_WORD _LA6 :1; + IO_WORD _LB5 :1; + IO_WORD _LA5 :1; + IO_WORD _LB4 :1; + IO_WORD _LA4 :1; + IO_WORD _LB3 :1; + IO_WORD _LA3 :1; + IO_WORD _LB2 :1; + IO_WORD _LA2 :1; + IO_WORD _LB1 :1; + IO_WORD _LA1 :1; + IO_WORD _LB0 :1; + IO_WORD _LA0 :1; + }bit; + }ELVR0STR; +typedef union{ /* External Interrupt 8-15 */ + IO_BYTE byte; + struct{ + IO_BYTE _ER15 :1; + IO_BYTE _ER14 :1; + IO_BYTE _ER13 :1; + IO_BYTE _ER12 :1; + IO_BYTE _ER11 :1; + IO_BYTE _ER10 :1; + IO_BYTE _ER9 :1; + IO_BYTE _ER8 :1; + }bit; + }EIRR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN15 :1; + IO_BYTE _EN14 :1; + IO_BYTE _EN13 :1; + IO_BYTE _EN12 :1; + IO_BYTE _EN11 :1; + IO_BYTE _EN10 :1; + IO_BYTE _EN9 :1; + IO_BYTE _EN8 :1; + }bit; + }ENIR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LB15 :1; + IO_WORD _LA15 :1; + IO_WORD _LB14 :1; + IO_WORD _LA14 :1; + IO_WORD _LB13 :1; + IO_WORD _LA13 :1; + IO_WORD _LB12 :1; + IO_WORD _LA12 :1; + IO_WORD _LB11 :1; + IO_WORD _LA11 :1; + IO_WORD _LB10 :1; + IO_WORD _LA10 :1; + IO_WORD _LB9 :1; + IO_WORD _LA9 :1; + IO_WORD _LB8 :1; + IO_WORD _LA8 :1; + }bit; + }ELVR1STR; +typedef union{ /* DLYI/I-unit */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DLYI :1; + }bit; + }DICRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MHALTI :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LVL4 :1; + IO_BYTE _LVL3 :1; + IO_BYTE _LVL2 :1; + IO_BYTE _LVL1 :1; + IO_BYTE _LVL0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LVL :5; + }bitc; + }HRCLSTR; +typedef union{ /* USART (LIN) 0 */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR00STR; +typedef union{ /* USART (LIN) 1 */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR01STR; +typedef union{ /* USART (LIN) 2 */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR02STR; +typedef union{ /* USART (LIN) 3 */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR03STR; +typedef union{ /* USART (LIN) 4 with FIFO */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RXL3 :1; + IO_BYTE _RXL2 :1; + IO_BYTE _RXL1 :1; + IO_BYTE _RXL0 :1; + IO_BYTE :1; + IO_BYTE _ERX :1; + IO_BYTE _ETX :1; + IO_BYTE _SVD :1; + }bit; + struct{ + IO_BYTE _RXL :4; + }bitc; + }FCR04STR; +typedef union{ /* I2C 0 */ + IO_BYTE byte; + struct{ + IO_BYTE _BER :1; + IO_BYTE _BEIE :1; + IO_BYTE _SCC :1; + IO_BYTE _MSS :1; + IO_BYTE _ACK :1; + IO_BYTE _GCAA :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + }bit; + }IBCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BB :1; + IO_BYTE _RSC :1; + IO_BYTE _AL :1; + IO_BYTE _LRB :1; + IO_BYTE _TRX :1; + IO_BYTE _AAS :1; + IO_BYTE _GCA :1; + IO_BYTE _ADT :1; + }bit; + }IBSR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TA9 :1; + IO_WORD _TA8 :1; + IO_WORD _TA7 :1; + IO_WORD _TA6 :1; + IO_WORD _TA5 :1; + IO_WORD _TA4 :1; + IO_WORD _TA3 :1; + IO_WORD _TA2 :1; + IO_WORD _TA1 :1; + IO_WORD _TA0 :1; + }bit; + }ITBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TA9 :1; + IO_BYTE _TA8 :1; + }bit; + }ITBAH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA7 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA0 :1; + }bit; + }ITBAL0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ENTB :1; + IO_WORD _RAL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TM9 :1; + IO_WORD _TM8 :1; + IO_WORD _TM7 :1; + IO_WORD _TM6 :1; + IO_WORD _TM5 :1; + IO_WORD _TM4 :1; + IO_WORD _TM3 :1; + IO_WORD _TM2 :1; + IO_WORD _TM1 :1; + IO_WORD _TM0 :1; + }bit; + }ITMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENTB :1; + IO_BYTE _RAL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TM9 :1; + IO_BYTE _TM8 :1; + }bit; + }ITMKH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM7 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM0 :1; + }bit; + }ITMKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENSB :1; + IO_BYTE _SM6 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM0 :1; + }bit; + }ISMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _SA6 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA0 :1; + }bit; + }ISBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }IDAR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _NSF :1; + IO_BYTE _EN :1; + IO_BYTE _CS4 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CS :5; + }bitc; + }ICCR0STR; +typedef union{ /* PPG Control 0-3 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN20STR; +typedef union{ /* PPG Control 4-7 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN21STR; +typedef union{ /* PPG Control 8-11 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL00STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL01STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL02STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL03STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL04STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL05STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL06STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL07STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL08STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL09STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL11STR; +typedef union{ /* Input Capture 0-3 */ + IO_BYTE byte; + struct{ + IO_BYTE _ICP1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICE0 :1; + IO_BYTE _EG11 :1; + IO_BYTE _EG10 :1; + IO_BYTE _EG01 :1; + IO_BYTE _EG00 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG1 :2; + IO_BYTE _EG0 :2; + }bitc; + }ICS01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ICP3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICE2 :1; + IO_BYTE _EG31 :1; + IO_BYTE _EG30 :1; + IO_BYTE _EG21 :1; + IO_BYTE _EG20 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG3 :2; + IO_BYTE _EG2 :2; + }bitc; + }ICS23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP3STR; +typedef union{ /* Output Compare 0-3 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD1 :1; + IO_WORD _OTD0 :1; + IO_WORD _ICP1 :1; + IO_WORD _ICP0 :1; + IO_WORD _ICE1 :1; + IO_WORD _ICE0 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST1 :1; + IO_WORD _CST0 :1; + }bit; + }OCS01STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD3 :1; + IO_WORD _OTD2 :1; + IO_WORD _ICP3 :1; + IO_WORD _ICP2 :1; + IO_WORD _ICE3 :1; + IO_WORD _ICE2 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST3 :1; + IO_WORD _CST2 :1; + }bit; + }OCS23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP3STR; +typedef union{ /* ADC */ + IO_WORD word; + struct{ + IO_WORD _ADE31 :1; + IO_WORD _ADE30 :1; + IO_WORD _ADE29 :1; + IO_WORD _ADE28 :1; + IO_WORD _ADE27 :1; + IO_WORD _ADE26 :1; + IO_WORD _ADE25 :1; + IO_WORD _ADE24 :1; + IO_WORD _ADE23 :1; + IO_WORD _ADE22 :1; + IO_WORD _ADE21 :1; + IO_WORD _ADE20 :1; + IO_WORD _ADE19 :1; + IO_WORD _ADE18 :1; + IO_WORD _ADE17 :1; + IO_WORD _ADE16 :1; + }bit; + }ADERHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ADE15 :1; + IO_WORD _ADE14 :1; + IO_WORD _ADE13 :1; + IO_WORD _ADE12 :1; + IO_WORD _ADE11 :1; + IO_WORD _ADE10 :1; + IO_WORD _ADE9 :1; + IO_WORD _ADE8 :1; + IO_WORD _ADE7 :1; + IO_WORD _ADE6 :1; + IO_WORD _ADE5 :1; + IO_WORD _ADE4 :1; + IO_WORD _ADE3 :1; + IO_WORD _ADE2 :1; + IO_WORD _ADE1 :1; + IO_WORD _ADE0 :1; + }bit; + }ADERLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BUSY :1; + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _PAUS :1; + IO_BYTE _STS1 :1; + IO_BYTE _STS0 :1; + IO_BYTE _STRT :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _STS :2; + }bitc; + }ADCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _S10 :1; + IO_BYTE _ACH4 :1; + IO_BYTE _ACH3 :1; + IO_BYTE _ACH2 :1; + IO_BYTE _ACH1 :1; + IO_BYTE _ACH0 :1; + }bit; + struct{ + IO_BYTE _MD :2; + IO_BYTE :1; + IO_BYTE _ACH :5; + }bitc; + }ADCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D9 :1; + IO_BYTE _D8 :1; + }bit; + }ADCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }ADCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CT5 :1; + IO_BYTE _CT4 :1; + IO_BYTE _CT3 :1; + IO_BYTE _CT2 :1; + IO_BYTE _CT1 :1; + IO_BYTE _CT0 :1; + IO_BYTE _ST9 :1; + IO_BYTE _ST8 :1; + }bit; + }ADCT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ST7 :1; + IO_BYTE _ST6 :1; + IO_BYTE _ST5 :1; + IO_BYTE _ST4 :1; + IO_BYTE _ST3 :1; + IO_BYTE _ST2 :1; + IO_BYTE _ST1 :1; + IO_BYTE _ST0 :1; + }bit; + }ADCT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANS4 :1; + IO_BYTE _ANS3 :1; + IO_BYTE _ANS2 :1; + IO_BYTE _ANS1 :1; + IO_BYTE _ASN0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANS :5; + }bitc; + }ADSCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANE4 :1; + IO_BYTE _ANE3 :1; + IO_BYTE _ANE2 :1; + IO_BYTE _ANE1 :1; + IO_BYTE _ANE0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANE :5; + }bitc; + }ADECHSTR; +typedef union{ /* Reload Timer 0 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL0STR; +typedef union{ /* Reload Timer 1 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL1STR; +typedef union{ /* Reload Timer 2 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL2STR; +typedef union{ /* Reload Timer 3 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL3STR; +typedef union{ /* Reload Timer 4 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL4STR; +typedef union{ /* Reload Timer 5 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL5STR; +typedef union{ /* Reload Timer 6 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL6STR; +typedef union{ /* Reload Timer 7 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OULT :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OULT :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL7STR; +typedef union{ /* Free Running Timer0 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS0STR; +typedef union{ /* Free Running Timer1 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS1STR; +typedef union{ /* Free Running Timer2 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS2STR; +typedef union{ /* Free Running Timer3 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS3STR; +typedef union{ /* DMAC */ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA2STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB2STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA3STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB3STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA4STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DMAE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PM01 :1; + IO_BYTE _DMAH3 :1; + IO_BYTE _DMAH2 :1; + IO_BYTE _DMAH1 :1; + IO_BYTE _DMAH0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DMAH :4; + }bitc; + }DMACRSTR; +typedef union{ /* Input Capture 4-7 */ + IO_BYTE byte; + struct{ + IO_BYTE _ICP5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICE4 :1; + IO_BYTE _EG51 :1; + IO_BYTE _EG50 :1; + IO_BYTE _EG41 :1; + IO_BYTE _EG40 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG5 :2; + IO_BYTE _EG4 :2; + }bitc; + }ICS45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ICP7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICE6 :1; + IO_BYTE _EG71 :1; + IO_BYTE _EG70 :1; + IO_BYTE _EG61 :1; + IO_BYTE _EG60 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG7 :2; + IO_BYTE _EG6 :2; + }bitc; + }ICS67STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP7STR; +typedef union{ /* Output Compare 4-7 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD5 :1; + IO_WORD _OTD4 :1; + IO_WORD _ICP5 :1; + IO_WORD _ICP4 :1; + IO_WORD _ICE5 :1; + IO_WORD _ICE4 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST5 :1; + IO_WORD _CST4 :1; + }bit; + }OCS45STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD7 :1; + IO_WORD _OTD6 :1; + IO_WORD _ICP7 :1; + IO_WORD _ICP6 :1; + IO_WORD _ICE7 :1; + IO_WORD _ICE6 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST7 :1; + IO_WORD _CST6 :1; + }bit; + }OCS67STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP7STR; +typedef union{ /* Free Running Timer4 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS4STR; +typedef union{ /* Free Running Timer5 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS5STR; +typedef union{ /* Free Running Timer6 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS6STR; +typedef union{ /* Free Running Timer7 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS7STR; +typedef union{ /* ROM Select Register */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }ROMSSTR; +typedef union{ /* Interrupt Control Unit */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR29STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR30STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR31STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR32STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR33STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR34STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR35STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR36STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR37STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR38STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR39STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR40STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR41STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR42STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR43STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR44STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR46STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR47STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR48STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR49STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR50STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR51STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR52STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR53STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR54STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR55STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR56STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR57STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR58STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR59STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR60STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR61STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR62STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR63STR; +typedef union{ /* Clock Control Unit */ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _HSTB :1; + IO_BYTE _WDOG :1; + IO_BYTE _ERST :1; + IO_BYTE _SRST :1; + IO_BYTE _LINIT :1; + IO_BYTE _WT1 :1; + IO_BYTE _WT0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WT :2; + }bitc; + }RSRRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _STOP :1; + IO_BYTE _SLEEP :1; + IO_BYTE _HIZ :1; + IO_BYTE _SRST :1; + IO_BYTE _OS1 :1; + IO_BYTE _OS0 :1; + IO_BYTE _OSCD2 :1; + IO_BYTE _OSCD1 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OS :2; + IO_BYTE _OSCD :2; + }bitc; + }STCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBIF :1; + IO_BYTE _TBIE :1; + IO_BYTE _TBC2 :1; + IO_BYTE _TBC1 :1; + IO_BYTE _TBC0 :1; + IO_BYTE :1; + IO_BYTE _SYNCR :1; + IO_BYTE _SYNCS :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TBC :3; + }bitc; + }TBCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }CTBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _SCKEN :1; + IO_BYTE _PLL1EN :1; + IO_BYTE _CLKS1 :1; + IO_BYTE _CLKS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLKS :2; + }bitc; + }CLKRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }WPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _B3 :1; + IO_BYTE _B2 :1; + IO_BYTE _B1 :1; + IO_BYTE _B0 :1; + IO_BYTE _P3 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + }bit; + struct{ + IO_BYTE _B :4; + IO_BYTE _P :4; + }bitc; + }DIVR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _T3 :1; + IO_BYTE _T2 :1; + IO_BYTE _T1 :1; + IO_BYTE _T0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _T :4; + }bitc; + }DIVR1STR; +typedef union{ /* PLL - Clock Gear Unit: */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVM3 :1; + IO_BYTE _DVM2 :1; + IO_BYTE _DVM1 :1; + IO_BYTE _DVM0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVM :4; + }bitc; + }PLLDIVMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVN5 :1; + IO_BYTE _DVN4 :1; + IO_BYTE _DVN3 :1; + IO_BYTE _DVN2 :1; + IO_BYTE _DVN1 :1; + IO_BYTE _DVN0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVN :6; + }bitc; + }PLLDIVNSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVG3 :1; + IO_BYTE _DVG2 :1; + IO_BYTE _DVG1 :1; + IO_BYTE _DVG0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVG :4; + }bitc; + }PLLDIVGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MLG7 :1; + IO_BYTE _MLG6 :1; + IO_BYTE _MLG5 :1; + IO_BYTE _MLG4 :1; + IO_BYTE _MLG3 :1; + IO_BYTE _MLG2 :1; + IO_BYTE _MLG1 :1; + IO_BYTE _MLG0 :1; + }bit; + struct{ + IO_BYTE _MLG :8; + }bitc; + }PLLMULGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IEDN :1; + IO_BYTE _GRDN :1; + IO_BYTE _IEUP :1; + IO_BYTE _GRUP :1; + }bit; + }PLLCTRLSTR; +typedef union{ /* Main/Sub Oscillator Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FCI :1; + IO_BYTE _RFBEN :1; + IO_BYTE _OSCR :1; + }bit; + }OSCC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSCS7 :1; + IO_BYTE _OSCS6 :1; + IO_BYTE _OSCS5 :1; + IO_BYTE _OSCS4 :1; + IO_BYTE _OSCS3 :1; + IO_BYTE _OSCS2 :1; + IO_BYTE _OSCS1 :1; + IO_BYTE _OSCS0 :1; + }bit; + }OSCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FCI :1; + IO_BYTE _RFBEN :1; + IO_BYTE _OSCR :1; + }bit; + }OSCC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSCS7 :1; + IO_BYTE _OSCS6 :1; + IO_BYTE _OSCS5 :1; + IO_BYTE _OSCS4 :1; + IO_BYTE _OSCS3 :1; + IO_BYTE _OSCS2 :1; + IO_BYTE _OSCS1 :1; + IO_BYTE _OSCS0 :1; + }bit; + }OSCS2STR; +typedef union{ /* Port Input Enable Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPORTEN :1; + IO_BYTE _GPORTEN :1; + }bit; + }PORTENSTR; +typedef union{ /* Real Time Clock (Watch Timer) */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _INTE4 :1; + IO_BYTE _INT4 :1; + }bit; + }WTCERSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTE3 :1; + IO_WORD _INT3 :1; + IO_WORD _INTE2 :1; + IO_WORD _INT2 :1; + IO_WORD _INTE1 :1; + IO_WORD _INT1 :1; + IO_WORD _INTE0 :1; + IO_WORD _INT0 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RUN :1; + IO_WORD _UPDT :1; + IO_WORD :1; + IO_WORD _ST :1; + }bit; + }WTCRSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _D20 :1; + IO_LWORD _D19 :1; + IO_LWORD _D18 :1; + IO_LWORD _D17 :1; + IO_LWORD _D16 :1; + IO_LWORD _D15 :1; + IO_LWORD _D14 :1; + IO_LWORD _D13 :1; + IO_LWORD _D12 :1; + IO_LWORD _D11 :1; + IO_LWORD _D10 :1; + IO_LWORD _D9 :1; + IO_LWORD _D8 :1; + IO_LWORD _D7 :1; + IO_LWORD _D6 :1; + IO_LWORD _D5 :1; + IO_LWORD _D4 :1; + IO_LWORD _D3 :1; + IO_LWORD _D2 :1; + IO_LWORD _D1 :1; + IO_LWORD _D0 :1; + }bit; + }WTBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _H4 :1; + IO_BYTE _H3 :1; + IO_BYTE _H2 :1; + IO_BYTE _H1 :1; + IO_BYTE _H0 :1; + }bit; + }WTHRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _M5 :1; + IO_BYTE _M4 :1; + IO_BYTE _M3 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + }WTMRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _S5 :1; + IO_BYTE _S4 :1; + IO_BYTE _S3 :1; + IO_BYTE _S2 :1; + IO_BYTE _S1 :1; + IO_BYTE _S0 :1; + }bit; + }WTSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCKS :1; + IO_BYTE _MM :1; + IO_BYTE _SM :1; + IO_BYTE _RCE :1; + IO_BYTE _MSVE :1; + IO_BYTE _SSVE :1; + IO_BYTE _SRST :1; + IO_BYTE _OUTE :1; + }bit; + }CSVCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EDSUEN :1; + IO_BYTE _PLLLOCK :1; + IO_BYTE _RCSEL :1; + IO_BYTE _MONCKI :1; + IO_BYTE _CSC3 :1; + IO_BYTE _CSC2 :1; + IO_BYTE _CSC1 :1; + IO_BYTE _CSC0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CSC :4; + }bitc; + }CSCFGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CMPRE3 :1; + IO_BYTE _CMPRE2 :1; + IO_BYTE _CMPRE1 :1; + IO_BYTE _CMPRE0 :1; + IO_BYTE _CMSEL3 :1; + IO_BYTE _CMSEL2 :1; + IO_BYTE _CMSEL1 :1; + IO_BYTE _CMSEL0 :1; + }bit; + struct{ + IO_BYTE _CMPRE :4; + IO_BYTE _CMSEL :4; + }bitc; + }CMCFGSTR; +typedef union{ /* Calibration Unit of Sub Oszillation */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _STRT :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _INT :1; + IO_WORD _INTEN :1; + }bit; + }CUCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDD15 :1; + IO_WORD _TDD14 :1; + IO_WORD _TDD13 :1; + IO_WORD _TDD12 :1; + IO_WORD _TDD11 :1; + IO_WORD _TDD10 :1; + IO_WORD _TDD9 :1; + IO_WORD _TDD8 :1; + IO_WORD _TDD7 :1; + IO_WORD _TDD6 :1; + IO_WORD _TDD5 :1; + IO_WORD _TDD4 :1; + IO_WORD _TDD3 :1; + IO_WORD _TDD2 :1; + IO_WORD _TDD1 :1; + IO_WORD _TDD0 :1; + }bit; + }CUTDSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TDR23 :1; + IO_WORD _TDR22 :1; + IO_WORD _TDR21 :1; + IO_WORD _TDR20 :1; + IO_WORD _TDR19 :1; + IO_WORD _TDR18 :1; + IO_WORD _TDR17 :1; + IO_WORD _TDR16 :1; + }bit; + }CUTR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR15 :1; + IO_WORD _TDR14 :1; + IO_WORD _TDR13 :1; + IO_WORD _TDR12 :1; + IO_WORD _TDR11 :1; + IO_WORD _TDR10 :1; + IO_WORD _TDR9 :1; + IO_WORD _TDR8 :1; + IO_WORD _TDR7 :1; + IO_WORD _TDR6 :1; + IO_WORD _TDR5 :1; + IO_WORD _TDR4 :1; + IO_WORD _TDR3 :1; + IO_WORD _TDR2 :1; + IO_WORD _TDR1 :1; + IO_WORD _TDR0 :1; + }bit; + }CUTR2STR; +typedef union{ /* Clock Modulator */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _MP13 :1; + IO_WORD _MP12 :1; + IO_WORD _MP11 :1; + IO_WORD _MP10 :1; + IO_WORD _MP9 :1; + IO_WORD _MP8 :1; + IO_WORD _MP7 :1; + IO_WORD _MP6 :1; + IO_WORD _MP5 :1; + IO_WORD _MP4 :1; + IO_WORD _MP3 :1; + IO_WORD _MP2 :1; + IO_WORD _MP1 :1; + IO_WORD _MP0 :1; + }bit; + }CMPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FMODRUN :1; + IO_BYTE :1; + IO_BYTE _FMOD :1; + IO_BYTE _PDX :1; + }bit; + }CMCRSTR; +typedef union{ /* CAN clock control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPCKS1 :1; + IO_BYTE _CPCKS0 :1; + IO_BYTE _DVC3 :1; + IO_BYTE _DVC2 :1; + IO_BYTE _DVC1 :1; + IO_BYTE _DVC0 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CPCKS :2; + IO_BYTE _DVC :4; + }bitc; + }CANPRESTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CANCKD5 :1; + IO_BYTE _CANCKD4 :1; + IO_BYTE _CANCKD3 :1; + IO_BYTE _CANCKD2 :1; + IO_BYTE _CANCKD1 :1; + IO_BYTE _CANCKD0 :1; + }bit; + }CANCKDSTR; +typedef union{ /* LV Detection / Hardware-Watchdog */ + IO_BYTE byte; + struct{ + IO_BYTE _LVESEL3 :1; + IO_BYTE _LVESEL2 :1; + IO_BYTE _LVESEL1 :1; + IO_BYTE _LVESEL0 :1; + IO_BYTE _LVISEL3 :1; + IO_BYTE _LVISEL2 :1; + IO_BYTE _LVISEL1 :1; + IO_BYTE _LVISEL0 :1; + }bit; + struct{ + IO_BYTE _LVESEL :4; + IO_BYTE _LVISEL :4; + }bitc; + }LVSELSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _LVSEL :1; + IO_BYTE _LVEPD :1; + IO_BYTE _LVIPD :1; + IO_BYTE _LVREN :1; + IO_BYTE :1; + IO_BYTE _LVIEN :1; + IO_BYTE _LVIRQ :1; + }bit; + }LVDETSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ED1 :1; + IO_BYTE _ED0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ED :2; + }bitc; + }HWWDESTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPUF :1; + }bit; + }HWWDSTR; +typedef union{ /* Main-/Sub-Oscillatio Stabilization Timer */ + IO_BYTE byte; + struct{ + IO_BYTE _WIF :1; + IO_BYTE _WIE :1; + IO_BYTE _WEN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS1 :1; + IO_BYTE _WS0 :1; + IO_BYTE _WCL :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS :2; + }bitc; + }OSCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WIF :1; + IO_BYTE _WIE :1; + IO_BYTE _WEN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS1 :1; + IO_BYTE _WS0 :1; + IO_BYTE _WCL :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS :2; + }bitc; + }WPCRHSTR; +typedef union{ /* Main-/Sub-Oscillatio Standby Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OSCDS1 :1; + }bit; + }OSCCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FLASHSEL :1; + IO_BYTE _MAINSEL :1; + IO_BYTE _SUBSEL3 :1; + IO_BYTE _SUBSEL2 :1; + IO_BYTE _SUBSEL1 :1; + IO_BYTE _SUBSEL0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _SUBSEL :4; + }bitc; + }REGSELSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MSTBO :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MAINKPEN :1; + IO_BYTE _MAINDSBL :1; + }bit; + }REGCTRSTR; +typedef union{ /* Mode Register */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ROMA :1; + IO_BYTE _WTH1 :1; + IO_BYTE _WTH0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WTH :2; + }bitc; + }MODRSTR; +typedef union{ /* R-bus Port Data Direct Read Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDRD18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD29STR; +typedef union{ /* R-bus Port Direction Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DDR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR29STR; +typedef union{ /* R-bus Port Function Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PFR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR29STR; +typedef union{ /* R-bus Port Extra Function Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR27STR; +typedef union{ /* R-bus Port Output Drive Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PODR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR29STR; +typedef union{ /* R-bus Port Input Level Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PILR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR29STR; +typedef union{ /* R-bus Port Extra Input Level Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPILR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR29STR; +typedef union{ /* R-bus Port Pull-Up/Down Enable Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PPER18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER29STR; +typedef union{ /* R-bus Port Pull-Up/Down Control Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PPCR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PPCR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR29STR; +typedef union{ /* Flash Memory/I-Cache Control Register */ + IO_BYTE byte; + struct{ + IO_BYTE _ASYNC :1; + IO_BYTE _FIXE :1; + IO_BYTE _BIRE :1; + IO_BYTE _RDYEG :1; + IO_BYTE _RDY :1; + IO_BYTE _RDYI :1; + IO_BYTE _RW16 :1; + IO_BYTE _LPM :1; + }bit; + }FMCSSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LOCK :1; + IO_BYTE _PHASE :1; + IO_BYTE _PF2I :1; + IO_BYTE _RD64 :1; + }bit; + }FMCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _REN :1; + IO_WORD _TAGE :1; + IO_WORD _FLUSH :1; + IO_WORD _DBEN :1; + IO_WORD _PFEN :1; + IO_WORD _PFMC :1; + IO_WORD _LOCK :1; + IO_WORD _ENAB :1; + IO_WORD _SIZE1 :1; + IO_WORD _SIZE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _SIZE :2; + }bitc; + }FCHCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _WTP1 :1; + IO_WORD _WTP0 :1; + IO_WORD _WEXH1 :1; + IO_WORD _WEXH0 :1; + IO_WORD _WTC3 :1; + IO_WORD _WTC2 :1; + IO_WORD _WTC1 :1; + IO_WORD _WTC0 :1; + IO_WORD _FRAM :1; + IO_WORD _ATD2 :1; + IO_WORD _ATD1 :1; + IO_WORD _ATD0 :1; + IO_WORD _EQ3 :1; + IO_WORD _EQ2 :1; + IO_WORD _EQ1 :1; + IO_WORD _EQ0 :1; + }bit; + struct{ + IO_WORD _WTP :2; + IO_WORD _WEXH :2; + IO_WORD _WTC :4; + IO_WORD :1; + IO_WORD _ATD :3; + IO_WORD _EQ :4; + }bitc; + }FMWTSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _ALEH2 :1; + IO_BYTE _ALEH1 :1; + IO_BYTE _ALEH0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ALEH :3; + }bitc; + }FMWT2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PS :3; + }bitc; + }FMPSSTR; +typedef union{ /* Flash Security Control Register */ + IO_LWORD lword; + struct{ + IO_LWORD _CRC31 :1; + IO_LWORD _CRC30 :1; + IO_LWORD _CRC29 :1; + IO_LWORD _CRC28 :1; + IO_LWORD _CRC27 :1; + IO_LWORD _CRC26 :1; + IO_LWORD _CRC25 :1; + IO_LWORD _CRC24 :1; + IO_LWORD _CRC23 :1; + IO_LWORD _CRC22 :1; + IO_LWORD _CRC21 :1; + IO_LWORD _CRC20 :1; + IO_LWORD _CRC19 :1; + IO_LWORD _CRC18 :1; + IO_LWORD _CRC17 :1; + IO_LWORD _CRC16 :1; + IO_LWORD _CRC15 :1; + IO_LWORD _CRC14 :1; + IO_LWORD _CRC13 :1; + IO_LWORD _CRC12 :1; + IO_LWORD _CRC11 :1; + IO_LWORD _CRC10 :1; + IO_LWORD _CRC9 :1; + IO_LWORD _CRC8 :1; + IO_LWORD _CRC7 :1; + IO_LWORD _CRC6 :1; + IO_LWORD _CRC5 :1; + IO_LWORD _CRC4 :1; + IO_LWORD _CRC3 :1; + IO_LWORD _CRC2 :1; + IO_LWORD _CRC1 :1; + IO_LWORD _CRC0 :1; + }bit; + }FSCR0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _RDY :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CSZ3 :1; + IO_LWORD _CSZ2 :1; + IO_LWORD _CSZ1 :1; + IO_LWORD _CSZ0 :1; + IO_LWORD _CSA15 :1; + IO_LWORD _CSA14 :1; + IO_LWORD _CSA13 :1; + IO_LWORD _CSA12 :1; + IO_LWORD _CSA11 :1; + IO_LWORD _CSA10 :1; + IO_LWORD _CSA9 :1; + IO_LWORD _CSA8 :1; + IO_LWORD _CSA7 :1; + IO_LWORD _CSA6 :1; + IO_LWORD _CSA5 :1; + IO_LWORD _CSA4 :1; + IO_LWORD _CSA3 :1; + IO_LWORD _CSA2 :1; + IO_LWORD _CSA1 :1; + IO_LWORD _CSA0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CSZ :4; + }bitc; + }FSCR1STR; +typedef union{ /* CAN 4 Control Register */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Test :1; + IO_WORD _CCE :1; + IO_WORD _DAR :1; + IO_WORD :1; + IO_WORD _EIE :1; + IO_WORD _SIE :1; + IO_WORD _IE :1; + IO_WORD _Init :1; + }bit; + }CTRLR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BOff :1; + IO_WORD _EWarn :1; + IO_WORD _EPass :1; + IO_WORD _RxOK :1; + IO_WORD _TxOK :1; + IO_WORD _LEC2 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _LEC :3; + }bitc; + }STATR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RP :1; + IO_WORD _REC6 :1; + IO_WORD _REC5 :1; + IO_WORD _REC4 :1; + IO_WORD _REC3 :1; + IO_WORD _REC2 :1; + IO_WORD _REC1 :1; + IO_WORD _REC0 :1; + IO_WORD _TEC7 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _REC :7; + IO_WORD _TEC :8; + }bitc; + }ERRCNT4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _Tseg22 :1; + IO_WORD _Tseg21 :1; + IO_WORD _Tseg20 :1; + IO_WORD _Tseg13 :1; + IO_WORD _Tseg12 :1; + IO_WORD _Tseg11 :1; + IO_WORD _Tseg10 :1; + IO_WORD _SJW1 :1; + IO_WORD _SJW0 :1; + IO_WORD _BRP5 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _Tseg2 :3; + IO_WORD _Tseg1 :4; + IO_WORD _SJW :2; + IO_WORD _BRP :6; + }bitc; + }BTR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Rx :1; + IO_WORD _Tx1 :1; + IO_WORD _Tx0 :1; + IO_WORD _LBack :1; + IO_WORD _Silent :1; + IO_WORD _Basic :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Tx :2; + }bitc; + }TESTR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE3 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE :4; + }bitc; + }BRPER4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }BRPE4STR; +typedef union{ /* CAN 4 IF 1 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF1CREQ4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF1CMSK4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1MSK24STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1ARB24STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF1MCTR4STR; +typedef union{ /* CAN 4 IF 2 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF2CREQ4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF2CMSK4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2MSK24STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2ARB24STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF2MCTR4STR; +typedef union{ /* EDSU/MPU Registers */ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SR :1; + IO_LWORD _SW :1; + IO_LWORD _SX :1; + IO_LWORD _UR :1; + IO_LWORD _UW :1; + IO_LWORD _UX :1; + IO_LWORD _FCPU :1; + IO_LWORD _FDMA :1; + IO_LWORD _EEMM :1; + IO_LWORD _PFD :1; + IO_LWORD _SINT1 :1; + IO_LWORD _SINT0 :1; + IO_LWORD _EINT1 :1; + IO_LWORD _EINT0 :1; + IO_LWORD _EINTT :1; + IO_LWORD _EINTR :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SINT :2; + IO_LWORD _EINT :2; + }bitc; + }BCTRLSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IDX4 :1; + IO_LWORD _IDX3 :1; + IO_LWORD _IDX2 :1; + IO_LWORD _IDX1 :1; + IO_LWORD _IDX0 :1; + IO_LWORD _CDMA :1; + IO_LWORD _CSZ1 :1; + IO_LWORD _CSZ0 :1; + IO_LWORD _CRW1 :1; + IO_LWORD _CRW0 :1; + IO_LWORD _PV :1; + IO_LWORD _RST :1; + IO_LWORD _INT1 :1; + IO_LWORD _INT0 :1; + IO_LWORD _INTT :1; + IO_LWORD _INTR :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IDX :5; + IO_LWORD :1; + IO_LWORD _CSZ :2; + IO_LWORD _CRW :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _INT :2; + }bitc; + }BSTATSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _BD31 :1; + IO_LWORD _BD30 :1; + IO_LWORD _BD29 :1; + IO_LWORD _BD28 :1; + IO_LWORD _BD27 :1; + IO_LWORD _BD26 :1; + IO_LWORD _BD25 :1; + IO_LWORD _BD24 :1; + IO_LWORD _BD23 :1; + IO_LWORD _BD22 :1; + IO_LWORD _BD21 :1; + IO_LWORD _BD20 :1; + IO_LWORD _BD19 :1; + IO_LWORD _BD18 :1; + IO_LWORD _BD17 :1; + IO_LWORD _BD16 :1; + IO_LWORD _BD15 :1; + IO_LWORD _BD14 :1; + IO_LWORD _BD13 :1; + IO_LWORD _BD12 :1; + IO_LWORD _BD11 :1; + IO_LWORD _BD10 :1; + IO_LWORD _BD9 :1; + IO_LWORD _BD8 :1; + IO_LWORD _BD7 :1; + IO_LWORD _BD6 :1; + IO_LWORD _BD5 :1; + IO_LWORD _BD4 :1; + IO_LWORD _BD3 :1; + IO_LWORD _BD2 :1; + IO_LWORD _BD1 :1; + IO_LWORD _BD0 :1; + }bit; + }BIRQSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR1STR; + +/* C-DECLARATIONS */ + +__IO_EXTERN __io PDR14STR pdr14; /* Port Data Register */ +#define PDR14 pdr14.byte +#define PDR14_D7 pdr14.bit._D7 +#define PDR14_D6 pdr14.bit._D6 +#define PDR14_D5 pdr14.bit._D5 +#define PDR14_D4 pdr14.bit._D4 +#define PDR14_D3 pdr14.bit._D3 +#define PDR14_D2 pdr14.bit._D2 +#define PDR14_D1 pdr14.bit._D1 +#define PDR14_D0 pdr14.bit._D0 +__IO_EXTERN __io PDR15STR pdr15; +#define PDR15 pdr15.byte +#define PDR15_D7 pdr15.bit._D7 +#define PDR15_D6 pdr15.bit._D6 +#define PDR15_D5 pdr15.bit._D5 +#define PDR15_D4 pdr15.bit._D4 +#define PDR15_D3 pdr15.bit._D3 +#define PDR15_D2 pdr15.bit._D2 +#define PDR15_D1 pdr15.bit._D1 +#define PDR15_D0 pdr15.bit._D0 +__IO_EXTERN __io PDR16STR pdr16; +#define PDR16 pdr16.byte +#define PDR16_D7 pdr16.bit._D7 +#define PDR16_D6 pdr16.bit._D6 +#define PDR16_D5 pdr16.bit._D5 +#define PDR16_D4 pdr16.bit._D4 +#define PDR16_D3 pdr16.bit._D3 +#define PDR16_D2 pdr16.bit._D2 +#define PDR16_D1 pdr16.bit._D1 +#define PDR16_D0 pdr16.bit._D0 +__IO_EXTERN __io PDR17STR pdr17; +#define PDR17 pdr17.byte +#define PDR17_D7 pdr17.bit._D7 +#define PDR17_D6 pdr17.bit._D6 +#define PDR17_D5 pdr17.bit._D5 +#define PDR17_D4 pdr17.bit._D4 +#define PDR17_D3 pdr17.bit._D3 +#define PDR17_D2 pdr17.bit._D2 +#define PDR17_D1 pdr17.bit._D1 +#define PDR17_D0 pdr17.bit._D0 +__IO_EXTERN __io PDR18STR pdr18; +#define PDR18 pdr18.byte +#define PDR18_D6 pdr18.bit._D6 +#define PDR18_D2 pdr18.bit._D2 +__IO_EXTERN __io PDR19STR pdr19; +#define PDR19 pdr19.byte +#define PDR19_D6 pdr19.bit._D6 +#define PDR19_D2 pdr19.bit._D2 +#define PDR19_D1 pdr19.bit._D1 +#define PDR19_D0 pdr19.bit._D0 +__IO_EXTERN __io PDR20STR pdr20; +#define PDR20 pdr20.byte +#define PDR20_D7 pdr20.bit._D7 +#define PDR20_D6 pdr20.bit._D6 +#define PDR20_D5 pdr20.bit._D5 +#define PDR20_D4 pdr20.bit._D4 +#define PDR20_D3 pdr20.bit._D3 +#define PDR20_D2 pdr20.bit._D2 +#define PDR20_D1 pdr20.bit._D1 +#define PDR20_D0 pdr20.bit._D0 +__IO_EXTERN __io PDR21STR pdr21; +#define PDR21 pdr21.byte +#define PDR21_D7 pdr21.bit._D7 +#define PDR21_D6 pdr21.bit._D6 +#define PDR21_D5 pdr21.bit._D5 +#define PDR21_D4 pdr21.bit._D4 +#define PDR21_D3 pdr21.bit._D3 +#define PDR21_D2 pdr21.bit._D2 +#define PDR21_D1 pdr21.bit._D1 +#define PDR21_D0 pdr21.bit._D0 +__IO_EXTERN __io PDR22STR pdr22; +#define PDR22 pdr22.byte +#define PDR22_D5 pdr22.bit._D5 +#define PDR22_D4 pdr22.bit._D4 +#define PDR22_D1 pdr22.bit._D1 +#define PDR22_D0 pdr22.bit._D0 +__IO_EXTERN __io PDR24STR pdr24; +#define PDR24 pdr24.byte +#define PDR24_D7 pdr24.bit._D7 +#define PDR24_D6 pdr24.bit._D6 +#define PDR24_D5 pdr24.bit._D5 +#define PDR24_D4 pdr24.bit._D4 +#define PDR24_D3 pdr24.bit._D3 +#define PDR24_D2 pdr24.bit._D2 +#define PDR24_D1 pdr24.bit._D1 +#define PDR24_D0 pdr24.bit._D0 +__IO_EXTERN __io PDR26STR pdr26; +#define PDR26 pdr26.byte +#define PDR26_D1 pdr26.bit._D1 +#define PDR26_D0 pdr26.bit._D0 +__IO_EXTERN __io PDR27STR pdr27; +#define PDR27 pdr27.byte +#define PDR27_D7 pdr27.bit._D7 +#define PDR27_D6 pdr27.bit._D6 +#define PDR27_D5 pdr27.bit._D5 +#define PDR27_D4 pdr27.bit._D4 +#define PDR27_D3 pdr27.bit._D3 +#define PDR27_D2 pdr27.bit._D2 +#define PDR27_D1 pdr27.bit._D1 +#define PDR27_D0 pdr27.bit._D0 +__IO_EXTERN __io PDR28STR pdr28; +#define PDR28 pdr28.byte +#define PDR28_D7 pdr28.bit._D7 +#define PDR28_D6 pdr28.bit._D6 +#define PDR28_D5 pdr28.bit._D5 +#define PDR28_D4 pdr28.bit._D4 +#define PDR28_D3 pdr28.bit._D3 +#define PDR28_D2 pdr28.bit._D2 +#define PDR28_D1 pdr28.bit._D1 +#define PDR28_D0 pdr28.bit._D0 +__IO_EXTERN __io PDR29STR pdr29; +#define PDR29 pdr29.byte +#define PDR29_D7 pdr29.bit._D7 +#define PDR29_D6 pdr29.bit._D6 +#define PDR29_D5 pdr29.bit._D5 +#define PDR29_D4 pdr29.bit._D4 +#define PDR29_D3 pdr29.bit._D3 +#define PDR29_D2 pdr29.bit._D2 +#define PDR29_D1 pdr29.bit._D1 +#define PDR29_D0 pdr29.bit._D0 +__IO_EXTERN __io EIRR0STR eirr0; /* External Interrupt 0-7 */ +#define EIRR0 eirr0.byte +#define EIRR0_ER7 eirr0.bit._ER7 +#define EIRR0_ER6 eirr0.bit._ER6 +#define EIRR0_ER5 eirr0.bit._ER5 +#define EIRR0_ER4 eirr0.bit._ER4 +#define EIRR0_ER3 eirr0.bit._ER3 +#define EIRR0_ER2 eirr0.bit._ER2 +#define EIRR0_ER1 eirr0.bit._ER1 +#define EIRR0_ER0 eirr0.bit._ER0 +__IO_EXTERN __io ENIR0STR enir0; +#define ENIR0 enir0.byte +#define ENIR0_EN7 enir0.bit._EN7 +#define ENIR0_EN6 enir0.bit._EN6 +#define ENIR0_EN5 enir0.bit._EN5 +#define ENIR0_EN4 enir0.bit._EN4 +#define ENIR0_EN3 enir0.bit._EN3 +#define ENIR0_EN2 enir0.bit._EN2 +#define ENIR0_EN1 enir0.bit._EN1 +#define ENIR0_EN0 enir0.bit._EN0 +__IO_EXTERN __io ELVR0STR elvr0; +#define ELVR0 elvr0.word +#define ELVR0_LB7 elvr0.bit._LB7 +#define ELVR0_LA7 elvr0.bit._LA7 +#define ELVR0_LB6 elvr0.bit._LB6 +#define ELVR0_LA6 elvr0.bit._LA6 +#define ELVR0_LB5 elvr0.bit._LB5 +#define ELVR0_LA5 elvr0.bit._LA5 +#define ELVR0_LB4 elvr0.bit._LB4 +#define ELVR0_LA4 elvr0.bit._LA4 +#define ELVR0_LB3 elvr0.bit._LB3 +#define ELVR0_LA3 elvr0.bit._LA3 +#define ELVR0_LB2 elvr0.bit._LB2 +#define ELVR0_LA2 elvr0.bit._LA2 +#define ELVR0_LB1 elvr0.bit._LB1 +#define ELVR0_LA1 elvr0.bit._LA1 +#define ELVR0_LB0 elvr0.bit._LB0 +#define ELVR0_LA0 elvr0.bit._LA0 +__IO_EXTERN __io EIRR1STR eirr1; /* External Interrupt 8-15 */ +#define EIRR1 eirr1.byte +#define EIRR1_ER15 eirr1.bit._ER15 +#define EIRR1_ER14 eirr1.bit._ER14 +#define EIRR1_ER13 eirr1.bit._ER13 +#define EIRR1_ER12 eirr1.bit._ER12 +#define EIRR1_ER11 eirr1.bit._ER11 +#define EIRR1_ER10 eirr1.bit._ER10 +#define EIRR1_ER9 eirr1.bit._ER9 +#define EIRR1_ER8 eirr1.bit._ER8 +__IO_EXTERN __io ENIR1STR enir1; +#define ENIR1 enir1.byte +#define ENIR1_EN15 enir1.bit._EN15 +#define ENIR1_EN14 enir1.bit._EN14 +#define ENIR1_EN13 enir1.bit._EN13 +#define ENIR1_EN12 enir1.bit._EN12 +#define ENIR1_EN11 enir1.bit._EN11 +#define ENIR1_EN10 enir1.bit._EN10 +#define ENIR1_EN9 enir1.bit._EN9 +#define ENIR1_EN8 enir1.bit._EN8 +__IO_EXTERN __io ELVR1STR elvr1; +#define ELVR1 elvr1.word +#define ELVR1_LB15 elvr1.bit._LB15 +#define ELVR1_LA15 elvr1.bit._LA15 +#define ELVR1_LB14 elvr1.bit._LB14 +#define ELVR1_LA14 elvr1.bit._LA14 +#define ELVR1_LB13 elvr1.bit._LB13 +#define ELVR1_LA13 elvr1.bit._LA13 +#define ELVR1_LB12 elvr1.bit._LB12 +#define ELVR1_LA12 elvr1.bit._LA12 +#define ELVR1_LB11 elvr1.bit._LB11 +#define ELVR1_LA11 elvr1.bit._LA11 +#define ELVR1_LB10 elvr1.bit._LB10 +#define ELVR1_LA10 elvr1.bit._LA10 +#define ELVR1_LB9 elvr1.bit._LB9 +#define ELVR1_LA9 elvr1.bit._LA9 +#define ELVR1_LB8 elvr1.bit._LB8 +#define ELVR1_LA8 elvr1.bit._LA8 +__IO_EXTERN __io DICRSTR dicr; /* DLYI/I-unit */ +#define DICR dicr.byte +#define DICR_DLYI dicr.bit._DLYI +__IO_EXTERN __io HRCLSTR hrcl; +#define HRCL hrcl.byte +#define HRCL_MHALTI hrcl.bit._MHALTI +#define HRCL_LVL4 hrcl.bit._LVL4 +#define HRCL_LVL3 hrcl.bit._LVL3 +#define HRCL_LVL2 hrcl.bit._LVL2 +#define HRCL_LVL1 hrcl.bit._LVL1 +#define HRCL_LVL0 hrcl.bit._LVL0 +#define HRCL_LVL hrcl.bitc._LVL +__IO_EXTERN __io IO_WORD rbsync; /* R-Bus Sync */ +#define RBSYNC rbsync +__IO_EXTERN __io SCR00STR scr00; /* USART (LIN) 0 */ +#define SCR00 scr00.byte +#define SCR00_PEN scr00.bit._PEN +#define SCR00_P scr00.bit._P +#define SCR00_SBL scr00.bit._SBL +#define SCR00_CL scr00.bit._CL +#define SCR00_AD scr00.bit._AD +#define SCR00_CRE scr00.bit._CRE +#define SCR00_RXE scr00.bit._RXE +#define SCR00_TXE scr00.bit._TXE +__IO_EXTERN __io SMR00STR smr00; +#define SMR00 smr00.byte +#define SMR00_MD1 smr00.bit._MD1 +#define SMR00_MD0 smr00.bit._MD0 +#define SMR00_OTO smr00.bit._OTO +#define SMR00_EXT smr00.bit._EXT +#define SMR00_REST smr00.bit._REST +#define SMR00_UPCL smr00.bit._UPCL +#define SMR00_SCKE smr00.bit._SCKE +#define SMR00_SOE smr00.bit._SOE +#define SMR00_MD smr00.bitc._MD +__IO_EXTERN __io SSR00STR ssr00; +#define SSR00 ssr00.byte +#define SSR00_PE ssr00.bit._PE +#define SSR00_ORE ssr00.bit._ORE +#define SSR00_FRE ssr00.bit._FRE +#define SSR00_RDRF ssr00.bit._RDRF +#define SSR00_TDRE ssr00.bit._TDRE +#define SSR00_BDS ssr00.bit._BDS +#define SSR00_RIE ssr00.bit._RIE +#define SSR00_TIE ssr00.bit._TIE +__IO_EXTERN __io IO_BYTE rdr00; +#define RDR00 rdr00 +__IO_EXTERN __io IO_BYTE tdr00; +#define TDR00 tdr00 +__IO_EXTERN __io ESCR00STR escr00; +#define ESCR00 escr00.byte +#define ESCR00_LBIE escr00.bit._LBIE +#define ESCR00_LBD escr00.bit._LBD +#define ESCR00_LBL1 escr00.bit._LBL1 +#define ESCR00_LBL0 escr00.bit._LBL0 +#define ESCR00_SOPE escr00.bit._SOPE +#define ESCR00_SIOP escr00.bit._SIOP +#define ESCR00_CCO escr00.bit._CCO +#define ESCR00_SCES escr00.bit._SCES +#define ESCR00_LBL escr00.bitc._LBL +__IO_EXTERN __io ECCR00STR eccr00; +#define ECCR00 eccr00.byte +#define ECCR00_INV eccr00.bit._INV +#define ECCR00_LBR eccr00.bit._LBR +#define ECCR00_MS eccr00.bit._MS +#define ECCR00_SCDE eccr00.bit._SCDE +#define ECCR00_SSM eccr00.bit._SSM +#define ECCR00_BIE eccr00.bit._BIE +#define ECCR00_RBI eccr00.bit._RBI +#define ECCR00_TBI eccr00.bit._TBI +__IO_EXTERN __io SCR01STR scr01; /* USART (LIN) 1 */ +#define SCR01 scr01.byte +#define SCR01_PEN scr01.bit._PEN +#define SCR01_P scr01.bit._P +#define SCR01_SBL scr01.bit._SBL +#define SCR01_CL scr01.bit._CL +#define SCR01_AD scr01.bit._AD +#define SCR01_CRE scr01.bit._CRE +#define SCR01_RXE scr01.bit._RXE +#define SCR01_TXE scr01.bit._TXE +__IO_EXTERN __io SMR01STR smr01; +#define SMR01 smr01.byte +#define SMR01_MD1 smr01.bit._MD1 +#define SMR01_MD0 smr01.bit._MD0 +#define SMR01_OTO smr01.bit._OTO +#define SMR01_EXT smr01.bit._EXT +#define SMR01_REST smr01.bit._REST +#define SMR01_UPCL smr01.bit._UPCL +#define SMR01_SCKE smr01.bit._SCKE +#define SMR01_SOE smr01.bit._SOE +#define SMR01_MD smr01.bitc._MD +__IO_EXTERN __io SSR01STR ssr01; +#define SSR01 ssr01.byte +#define SSR01_PE ssr01.bit._PE +#define SSR01_ORE ssr01.bit._ORE +#define SSR01_FRE ssr01.bit._FRE +#define SSR01_RDRF ssr01.bit._RDRF +#define SSR01_TDRE ssr01.bit._TDRE +#define SSR01_BDS ssr01.bit._BDS +#define SSR01_RIE ssr01.bit._RIE +#define SSR01_TIE ssr01.bit._TIE +__IO_EXTERN __io IO_BYTE rdr01; +#define RDR01 rdr01 +__IO_EXTERN __io IO_BYTE tdr01; +#define TDR01 tdr01 +__IO_EXTERN __io ESCR01STR escr01; +#define ESCR01 escr01.byte +#define ESCR01_LBIE escr01.bit._LBIE +#define ESCR01_LBD escr01.bit._LBD +#define ESCR01_LBL1 escr01.bit._LBL1 +#define ESCR01_LBL0 escr01.bit._LBL0 +#define ESCR01_SOPE escr01.bit._SOPE +#define ESCR01_SIOP escr01.bit._SIOP +#define ESCR01_CCO escr01.bit._CCO +#define ESCR01_SCES escr01.bit._SCES +#define ESCR01_LBL escr01.bitc._LBL +__IO_EXTERN __io ECCR01STR eccr01; +#define ECCR01 eccr01.byte +#define ECCR01_INV eccr01.bit._INV +#define ECCR01_LBR eccr01.bit._LBR +#define ECCR01_MS eccr01.bit._MS +#define ECCR01_SCDE eccr01.bit._SCDE +#define ECCR01_SSM eccr01.bit._SSM +#define ECCR01_BIE eccr01.bit._BIE +#define ECCR01_RBI eccr01.bit._RBI +#define ECCR01_TBI eccr01.bit._TBI +__IO_EXTERN __io SCR02STR scr02; /* USART (LIN) 2 */ +#define SCR02 scr02.byte +#define SCR02_PEN scr02.bit._PEN +#define SCR02_P scr02.bit._P +#define SCR02_SBL scr02.bit._SBL +#define SCR02_CL scr02.bit._CL +#define SCR02_AD scr02.bit._AD +#define SCR02_CRE scr02.bit._CRE +#define SCR02_RXE scr02.bit._RXE +#define SCR02_TXE scr02.bit._TXE +__IO_EXTERN __io SMR02STR smr02; +#define SMR02 smr02.byte +#define SMR02_MD1 smr02.bit._MD1 +#define SMR02_MD0 smr02.bit._MD0 +#define SMR02_OTO smr02.bit._OTO +#define SMR02_EXT smr02.bit._EXT +#define SMR02_REST smr02.bit._REST +#define SMR02_UPCL smr02.bit._UPCL +#define SMR02_SCKE smr02.bit._SCKE +#define SMR02_SOE smr02.bit._SOE +#define SMR02_MD smr02.bitc._MD +__IO_EXTERN __io SSR02STR ssr02; +#define SSR02 ssr02.byte +#define SSR02_PE ssr02.bit._PE +#define SSR02_ORE ssr02.bit._ORE +#define SSR02_FRE ssr02.bit._FRE +#define SSR02_RDRF ssr02.bit._RDRF +#define SSR02_TDRE ssr02.bit._TDRE +#define SSR02_BDS ssr02.bit._BDS +#define SSR02_RIE ssr02.bit._RIE +#define SSR02_TIE ssr02.bit._TIE +__IO_EXTERN __io IO_BYTE rdr02; +#define RDR02 rdr02 +__IO_EXTERN __io IO_BYTE tdr02; +#define TDR02 tdr02 +__IO_EXTERN __io ESCR02STR escr02; +#define ESCR02 escr02.byte +#define ESCR02_LBIE escr02.bit._LBIE +#define ESCR02_LBD escr02.bit._LBD +#define ESCR02_LBL1 escr02.bit._LBL1 +#define ESCR02_LBL0 escr02.bit._LBL0 +#define ESCR02_SOPE escr02.bit._SOPE +#define ESCR02_SIOP escr02.bit._SIOP +#define ESCR02_CCO escr02.bit._CCO +#define ESCR02_SCES escr02.bit._SCES +#define ESCR02_LBL escr02.bitc._LBL +__IO_EXTERN __io ECCR02STR eccr02; +#define ECCR02 eccr02.byte +#define ECCR02_INV eccr02.bit._INV +#define ECCR02_LBR eccr02.bit._LBR +#define ECCR02_MS eccr02.bit._MS +#define ECCR02_SCDE eccr02.bit._SCDE +#define ECCR02_SSM eccr02.bit._SSM +#define ECCR02_BIE eccr02.bit._BIE +#define ECCR02_RBI eccr02.bit._RBI +#define ECCR02_TBI eccr02.bit._TBI +__IO_EXTERN __io SCR03STR scr03; /* USART (LIN) 3 */ +#define SCR03 scr03.byte +#define SCR03_PEN scr03.bit._PEN +#define SCR03_P scr03.bit._P +#define SCR03_SBL scr03.bit._SBL +#define SCR03_CL scr03.bit._CL +#define SCR03_AD scr03.bit._AD +#define SCR03_CRE scr03.bit._CRE +#define SCR03_RXE scr03.bit._RXE +#define SCR03_TXE scr03.bit._TXE +__IO_EXTERN __io SMR03STR smr03; +#define SMR03 smr03.byte +#define SMR03_MD1 smr03.bit._MD1 +#define SMR03_MD0 smr03.bit._MD0 +#define SMR03_OTO smr03.bit._OTO +#define SMR03_EXT smr03.bit._EXT +#define SMR03_REST smr03.bit._REST +#define SMR03_UPCL smr03.bit._UPCL +#define SMR03_SCKE smr03.bit._SCKE +#define SMR03_SOE smr03.bit._SOE +#define SMR03_MD smr03.bitc._MD +__IO_EXTERN __io SSR03STR ssr03; +#define SSR03 ssr03.byte +#define SSR03_PE ssr03.bit._PE +#define SSR03_ORE ssr03.bit._ORE +#define SSR03_FRE ssr03.bit._FRE +#define SSR03_RDRF ssr03.bit._RDRF +#define SSR03_TDRE ssr03.bit._TDRE +#define SSR03_BDS ssr03.bit._BDS +#define SSR03_RIE ssr03.bit._RIE +#define SSR03_TIE ssr03.bit._TIE +__IO_EXTERN __io IO_BYTE rdr03; +#define RDR03 rdr03 +__IO_EXTERN __io IO_BYTE tdr03; +#define TDR03 tdr03 +__IO_EXTERN __io ESCR03STR escr03; +#define ESCR03 escr03.byte +#define ESCR03_LBIE escr03.bit._LBIE +#define ESCR03_LBD escr03.bit._LBD +#define ESCR03_LBL1 escr03.bit._LBL1 +#define ESCR03_LBL0 escr03.bit._LBL0 +#define ESCR03_SOPE escr03.bit._SOPE +#define ESCR03_SIOP escr03.bit._SIOP +#define ESCR03_CCO escr03.bit._CCO +#define ESCR03_SCES escr03.bit._SCES +#define ESCR03_LBL escr03.bitc._LBL +__IO_EXTERN __io ECCR03STR eccr03; +#define ECCR03 eccr03.byte +#define ECCR03_INV eccr03.bit._INV +#define ECCR03_LBR eccr03.bit._LBR +#define ECCR03_MS eccr03.bit._MS +#define ECCR03_SCDE eccr03.bit._SCDE +#define ECCR03_SSM eccr03.bit._SSM +#define ECCR03_BIE eccr03.bit._BIE +#define ECCR03_RBI eccr03.bit._RBI +#define ECCR03_TBI eccr03.bit._TBI +__IO_EXTERN __io SCR04STR scr04; /* USART (LIN) 4 with FIFO */ +#define SCR04 scr04.byte +#define SCR04_PEN scr04.bit._PEN +#define SCR04_P scr04.bit._P +#define SCR04_SBL scr04.bit._SBL +#define SCR04_CL scr04.bit._CL +#define SCR04_AD scr04.bit._AD +#define SCR04_CRE scr04.bit._CRE +#define SCR04_RXE scr04.bit._RXE +#define SCR04_TXE scr04.bit._TXE +__IO_EXTERN __io SMR04STR smr04; +#define SMR04 smr04.byte +#define SMR04_MD1 smr04.bit._MD1 +#define SMR04_MD0 smr04.bit._MD0 +#define SMR04_OTO smr04.bit._OTO +#define SMR04_EXT smr04.bit._EXT +#define SMR04_REST smr04.bit._REST +#define SMR04_UPCL smr04.bit._UPCL +#define SMR04_SCKE smr04.bit._SCKE +#define SMR04_SOE smr04.bit._SOE +#define SMR04_MD smr04.bitc._MD +__IO_EXTERN __io SSR04STR ssr04; +#define SSR04 ssr04.byte +#define SSR04_PE ssr04.bit._PE +#define SSR04_ORE ssr04.bit._ORE +#define SSR04_FRE ssr04.bit._FRE +#define SSR04_RDRF ssr04.bit._RDRF +#define SSR04_TDRE ssr04.bit._TDRE +#define SSR04_BDS ssr04.bit._BDS +#define SSR04_RIE ssr04.bit._RIE +#define SSR04_TIE ssr04.bit._TIE +__IO_EXTERN __io IO_BYTE rdr04; +#define RDR04 rdr04 +__IO_EXTERN __io IO_BYTE tdr04; +#define TDR04 tdr04 +__IO_EXTERN __io ESCR04STR escr04; +#define ESCR04 escr04.byte +#define ESCR04_LBIE escr04.bit._LBIE +#define ESCR04_LBD escr04.bit._LBD +#define ESCR04_LBL1 escr04.bit._LBL1 +#define ESCR04_LBL0 escr04.bit._LBL0 +#define ESCR04_SOPE escr04.bit._SOPE +#define ESCR04_SIOP escr04.bit._SIOP +#define ESCR04_CCO escr04.bit._CCO +#define ESCR04_SCES escr04.bit._SCES +#define ESCR04_LBL escr04.bitc._LBL +__IO_EXTERN __io ECCR04STR eccr04; +#define ECCR04 eccr04.byte +#define ECCR04_INV eccr04.bit._INV +#define ECCR04_LBR eccr04.bit._LBR +#define ECCR04_MS eccr04.bit._MS +#define ECCR04_SCDE eccr04.bit._SCDE +#define ECCR04_SSM eccr04.bit._SSM +#define ECCR04_BIE eccr04.bit._BIE +#define ECCR04_RBI eccr04.bit._RBI +#define ECCR04_TBI eccr04.bit._TBI +__IO_EXTERN __io IO_BYTE fsr04; +#define FSR04 fsr04 +__IO_EXTERN __io FCR04STR fcr04; +#define FCR04 fcr04.byte +#define FCR04_RXL3 fcr04.bit._RXL3 +#define FCR04_RXL2 fcr04.bit._RXL2 +#define FCR04_RXL1 fcr04.bit._RXL1 +#define FCR04_RXL0 fcr04.bit._RXL0 +#define FCR04_ERX fcr04.bit._ERX +#define FCR04_ETX fcr04.bit._ETX +#define FCR04_SVD fcr04.bit._SVD +#define FCR04_RXL fcr04.bitc._RXL +__IO_EXTERN __io IO_WORD bgr00; /* Bauderate Generator USART (LIN) 0-7 */ +#define BGR00 bgr00 +__IO_EXTERN __io IO_BYTE bgr100; +#define BGR100 bgr100 +__IO_EXTERN __io IO_BYTE bgr000; +#define BGR000 bgr000 +__IO_EXTERN __io IO_WORD bgr01; +#define BGR01 bgr01 +__IO_EXTERN __io IO_BYTE bgr101; +#define BGR101 bgr101 +__IO_EXTERN __io IO_BYTE bgr001; +#define BGR001 bgr001 +__IO_EXTERN __io IO_WORD bgr02; +#define BGR02 bgr02 +__IO_EXTERN __io IO_BYTE bgr102; +#define BGR102 bgr102 +__IO_EXTERN __io IO_BYTE bgr002; +#define BGR002 bgr002 +__IO_EXTERN __io IO_WORD bgr03; +#define BGR03 bgr03 +__IO_EXTERN __io IO_BYTE bgr103; +#define BGR103 bgr103 +__IO_EXTERN __io IO_BYTE bgr003; +#define BGR003 bgr003 +__IO_EXTERN __io IO_WORD bgr04; +#define BGR04 bgr04 +__IO_EXTERN __io IO_BYTE bgr104; +#define BGR104 bgr104 +__IO_EXTERN __io IO_BYTE bgr004; +#define BGR004 bgr004 +__IO_EXTERN __io IBCR0STR ibcr0; /* I2C 0 */ +#define IBCR0 ibcr0.byte +#define IBCR0_BER ibcr0.bit._BER +#define IBCR0_BEIE ibcr0.bit._BEIE +#define IBCR0_SCC ibcr0.bit._SCC +#define IBCR0_MSS ibcr0.bit._MSS +#define IBCR0_ACK ibcr0.bit._ACK +#define IBCR0_GCAA ibcr0.bit._GCAA +#define IBCR0_INTE ibcr0.bit._INTE +#define IBCR0_INT ibcr0.bit._INT +__IO_EXTERN __io IBSR0STR ibsr0; +#define IBSR0 ibsr0.byte +#define IBSR0_BB ibsr0.bit._BB +#define IBSR0_RSC ibsr0.bit._RSC +#define IBSR0_AL ibsr0.bit._AL +#define IBSR0_LRB ibsr0.bit._LRB +#define IBSR0_TRX ibsr0.bit._TRX +#define IBSR0_AAS ibsr0.bit._AAS +#define IBSR0_GCA ibsr0.bit._GCA +#define IBSR0_ADT ibsr0.bit._ADT +__IO_EXTERN __io ITBA0STR itba0; +#define ITBA0 itba0.word +#define ITBA0_TA9 itba0.bit._TA9 +#define ITBA0_TA8 itba0.bit._TA8 +#define ITBA0_TA7 itba0.bit._TA7 +#define ITBA0_TA6 itba0.bit._TA6 +#define ITBA0_TA5 itba0.bit._TA5 +#define ITBA0_TA4 itba0.bit._TA4 +#define ITBA0_TA3 itba0.bit._TA3 +#define ITBA0_TA2 itba0.bit._TA2 +#define ITBA0_TA1 itba0.bit._TA1 +#define ITBA0_TA0 itba0.bit._TA0 +__IO_EXTERN __io ITBAH0STR itbah0; +#define ITBAH0 itbah0.byte +#define ITBAH0_TA9 itbah0.bit._TA9 +#define ITBAH0_TA8 itbah0.bit._TA8 +__IO_EXTERN __io ITBAL0STR itbal0; +#define ITBAL0 itbal0.byte +#define ITBAL0_TA7 itbal0.bit._TA7 +#define ITBAL0_TA6 itbal0.bit._TA6 +#define ITBAL0_TA5 itbal0.bit._TA5 +#define ITBAL0_TA4 itbal0.bit._TA4 +#define ITBAL0_TA3 itbal0.bit._TA3 +#define ITBAL0_TA2 itbal0.bit._TA2 +#define ITBAL0_TA1 itbal0.bit._TA1 +#define ITBAL0_TA0 itbal0.bit._TA0 +__IO_EXTERN __io ITMK0STR itmk0; +#define ITMK0 itmk0.word +#define ITMK0_ENTB itmk0.bit._ENTB +#define ITMK0_RAL itmk0.bit._RAL +#define ITMK0_TM9 itmk0.bit._TM9 +#define ITMK0_TM8 itmk0.bit._TM8 +#define ITMK0_TM7 itmk0.bit._TM7 +#define ITMK0_TM6 itmk0.bit._TM6 +#define ITMK0_TM5 itmk0.bit._TM5 +#define ITMK0_TM4 itmk0.bit._TM4 +#define ITMK0_TM3 itmk0.bit._TM3 +#define ITMK0_TM2 itmk0.bit._TM2 +#define ITMK0_TM1 itmk0.bit._TM1 +#define ITMK0_TM0 itmk0.bit._TM0 +__IO_EXTERN __io ITMKH0STR itmkh0; +#define ITMKH0 itmkh0.byte +#define ITMKH0_ENTB itmkh0.bit._ENTB +#define ITMKH0_RAL itmkh0.bit._RAL +#define ITMKH0_TM9 itmkh0.bit._TM9 +#define ITMKH0_TM8 itmkh0.bit._TM8 +__IO_EXTERN __io ITMKL0STR itmkl0; +#define ITMKL0 itmkl0.byte +#define ITMKL0_TM7 itmkl0.bit._TM7 +#define ITMKL0_TM6 itmkl0.bit._TM6 +#define ITMKL0_TM5 itmkl0.bit._TM5 +#define ITMKL0_TM4 itmkl0.bit._TM4 +#define ITMKL0_TM3 itmkl0.bit._TM3 +#define ITMKL0_TM2 itmkl0.bit._TM2 +#define ITMKL0_TM1 itmkl0.bit._TM1 +#define ITMKL0_TM0 itmkl0.bit._TM0 +__IO_EXTERN __io ISMK0STR ismk0; +#define ISMK0 ismk0.byte +#define ISMK0_ENSB ismk0.bit._ENSB +#define ISMK0_SM6 ismk0.bit._SM6 +#define ISMK0_SM5 ismk0.bit._SM5 +#define ISMK0_SM4 ismk0.bit._SM4 +#define ISMK0_SM3 ismk0.bit._SM3 +#define ISMK0_SM2 ismk0.bit._SM2 +#define ISMK0_SM1 ismk0.bit._SM1 +#define ISMK0_SM0 ismk0.bit._SM0 +__IO_EXTERN __io ISBA0STR isba0; +#define ISBA0 isba0.byte +#define ISBA0_SA6 isba0.bit._SA6 +#define ISBA0_SA5 isba0.bit._SA5 +#define ISBA0_SA4 isba0.bit._SA4 +#define ISBA0_SA3 isba0.bit._SA3 +#define ISBA0_SA2 isba0.bit._SA2 +#define ISBA0_SA1 isba0.bit._SA1 +#define ISBA0_SA0 isba0.bit._SA0 +__IO_EXTERN __io IDAR0STR idar0; +#define IDAR0 idar0.byte +#define IDAR0_D7 idar0.bit._D7 +#define IDAR0_D6 idar0.bit._D6 +#define IDAR0_D5 idar0.bit._D5 +#define IDAR0_D4 idar0.bit._D4 +#define IDAR0_D3 idar0.bit._D3 +#define IDAR0_D2 idar0.bit._D2 +#define IDAR0_D1 idar0.bit._D1 +#define IDAR0_D0 idar0.bit._D0 +__IO_EXTERN __io ICCR0STR iccr0; +#define ICCR0 iccr0.byte +#define ICCR0_NSF iccr0.bit._NSF +#define ICCR0_EN iccr0.bit._EN +#define ICCR0_CS4 iccr0.bit._CS4 +#define ICCR0_CS3 iccr0.bit._CS3 +#define ICCR0_CS2 iccr0.bit._CS2 +#define ICCR0_CS1 iccr0.bit._CS1 +#define ICCR0_CS0 iccr0.bit._CS0 +#define ICCR0_CS iccr0.bitc._CS +__IO_EXTERN GCN10STR gcn10; /* PPG Control 0-3 */ +#define GCN10 gcn10.word +#define GCN10_TSEL33 gcn10.bit._TSEL33 +#define GCN10_TSEL32 gcn10.bit._TSEL32 +#define GCN10_TSEL31 gcn10.bit._TSEL31 +#define GCN10_TSEL30 gcn10.bit._TSEL30 +#define GCN10_TSEL23 gcn10.bit._TSEL23 +#define GCN10_TSEL22 gcn10.bit._TSEL22 +#define GCN10_TSEL21 gcn10.bit._TSEL21 +#define GCN10_TSEL20 gcn10.bit._TSEL20 +#define GCN10_TSEL13 gcn10.bit._TSEL13 +#define GCN10_TSEL12 gcn10.bit._TSEL12 +#define GCN10_TSEL11 gcn10.bit._TSEL11 +#define GCN10_TSEL10 gcn10.bit._TSEL10 +#define GCN10_TSEL03 gcn10.bit._TSEL03 +#define GCN10_TSEL02 gcn10.bit._TSEL02 +#define GCN10_TSEL01 gcn10.bit._TSEL01 +#define GCN10_TSEL00 gcn10.bit._TSEL00 +__IO_EXTERN GCN20STR gcn20; +#define GCN20 gcn20.byte +#define GCN20_EN3 gcn20.bit._EN3 +#define GCN20_EN2 gcn20.bit._EN2 +#define GCN20_EN1 gcn20.bit._EN1 +#define GCN20_EN0 gcn20.bit._EN0 +__IO_EXTERN GCN11STR gcn11; /* PPG Control 4-7 */ +#define GCN11 gcn11.word +#define GCN11_TSEL33 gcn11.bit._TSEL33 +#define GCN11_TSEL32 gcn11.bit._TSEL32 +#define GCN11_TSEL31 gcn11.bit._TSEL31 +#define GCN11_TSEL30 gcn11.bit._TSEL30 +#define GCN11_TSEL23 gcn11.bit._TSEL23 +#define GCN11_TSEL22 gcn11.bit._TSEL22 +#define GCN11_TSEL21 gcn11.bit._TSEL21 +#define GCN11_TSEL20 gcn11.bit._TSEL20 +#define GCN11_TSEL13 gcn11.bit._TSEL13 +#define GCN11_TSEL12 gcn11.bit._TSEL12 +#define GCN11_TSEL11 gcn11.bit._TSEL11 +#define GCN11_TSEL10 gcn11.bit._TSEL10 +#define GCN11_TSEL03 gcn11.bit._TSEL03 +#define GCN11_TSEL02 gcn11.bit._TSEL02 +#define GCN11_TSEL01 gcn11.bit._TSEL01 +#define GCN11_TSEL00 gcn11.bit._TSEL00 +__IO_EXTERN GCN21STR gcn21; +#define GCN21 gcn21.byte +#define GCN21_EN3 gcn21.bit._EN3 +#define GCN21_EN2 gcn21.bit._EN2 +#define GCN21_EN1 gcn21.bit._EN1 +#define GCN21_EN0 gcn21.bit._EN0 +__IO_EXTERN GCN12STR gcn12; /* PPG Control 8-11 */ +#define GCN12 gcn12.word +#define GCN12_TSEL33 gcn12.bit._TSEL33 +#define GCN12_TSEL32 gcn12.bit._TSEL32 +#define GCN12_TSEL31 gcn12.bit._TSEL31 +#define GCN12_TSEL30 gcn12.bit._TSEL30 +#define GCN12_TSEL23 gcn12.bit._TSEL23 +#define GCN12_TSEL22 gcn12.bit._TSEL22 +#define GCN12_TSEL21 gcn12.bit._TSEL21 +#define GCN12_TSEL20 gcn12.bit._TSEL20 +#define GCN12_TSEL13 gcn12.bit._TSEL13 +#define GCN12_TSEL12 gcn12.bit._TSEL12 +#define GCN12_TSEL11 gcn12.bit._TSEL11 +#define GCN12_TSEL10 gcn12.bit._TSEL10 +#define GCN12_TSEL03 gcn12.bit._TSEL03 +#define GCN12_TSEL02 gcn12.bit._TSEL02 +#define GCN12_TSEL01 gcn12.bit._TSEL01 +#define GCN12_TSEL00 gcn12.bit._TSEL00 +__IO_EXTERN GCN22STR gcn22; +#define GCN22 gcn22.byte +#define GCN22_EN3 gcn22.bit._EN3 +#define GCN22_EN2 gcn22.bit._EN2 +#define GCN22_EN1 gcn22.bit._EN1 +#define GCN22_EN0 gcn22.bit._EN0 +__IO_EXTERN IO_WORD ptmr00; /* PPG 0 */ +#define PTMR00 ptmr00 +__IO_EXTERN IO_WORD pcsr00; +#define PCSR00 pcsr00 +__IO_EXTERN IO_WORD pdut00; +#define PDUT00 pdut00 +__IO_EXTERN PCN00STR pcn00; +#define PCN00 pcn00.word +#define PCN00_CNTE pcn00.bit._CNTE +#define PCN00_STGR pcn00.bit._STGR +#define PCN00_MDSE pcn00.bit._MDSE +#define PCN00_RTRG pcn00.bit._RTRG +#define PCN00_CKS1 pcn00.bit._CKS1 +#define PCN00_CKS0 pcn00.bit._CKS0 +#define PCN00_PGMS pcn00.bit._PGMS +#define PCN00_EGS1 pcn00.bit._EGS1 +#define PCN00_EGS0 pcn00.bit._EGS0 +#define PCN00_IREN pcn00.bit._IREN +#define PCN00_IRQF pcn00.bit._IRQF +#define PCN00_IRS1 pcn00.bit._IRS1 +#define PCN00_IRS0 pcn00.bit._IRS0 +#define PCN00_OSEL pcn00.bit._OSEL +#define PCN00_CKS pcn00.bitc._CKS +#define PCN00_EGS pcn00.bitc._EGS +#define PCN00_IRS pcn00.bitc._IRS +__IO_EXTERN PCNH00STR pcnh00; +#define PCNH00 pcnh00.byte +#define PCNH00_CNTE pcnh00.bit._CNTE +#define PCNH00_STGR pcnh00.bit._STGR +#define PCNH00_MDSE pcnh00.bit._MDSE +#define PCNH00_RTRG pcnh00.bit._RTRG +#define PCNH00_CKS1 pcnh00.bit._CKS1 +#define PCNH00_CKS0 pcnh00.bit._CKS0 +#define PCNH00_PGMS pcnh00.bit._PGMS +#define PCNH00_CKS pcnh00.bitc._CKS +__IO_EXTERN PCNL00STR pcnl00; +#define PCNL00 pcnl00.byte +#define PCNL00_EGS1 pcnl00.bit._EGS1 +#define PCNL00_EGS0 pcnl00.bit._EGS0 +#define PCNL00_IREN pcnl00.bit._IREN +#define PCNL00_IRQF pcnl00.bit._IRQF +#define PCNL00_IRS1 pcnl00.bit._IRS1 +#define PCNL00_IRS0 pcnl00.bit._IRS0 +#define PCNL00_OSEL pcnl00.bit._OSEL +#define PCNL00_EGS pcnl00.bitc._EGS +#define PCNL00_IRS pcnl00.bitc._IRS +__IO_EXTERN IO_WORD ptmr01; /* PPG 1 */ +#define PTMR01 ptmr01 +__IO_EXTERN IO_WORD pcsr01; +#define PCSR01 pcsr01 +__IO_EXTERN IO_WORD pdut01; +#define PDUT01 pdut01 +__IO_EXTERN PCN01STR pcn01; +#define PCN01 pcn01.word +#define PCN01_CNTE pcn01.bit._CNTE +#define PCN01_STGR pcn01.bit._STGR +#define PCN01_MDSE pcn01.bit._MDSE +#define PCN01_RTRG pcn01.bit._RTRG +#define PCN01_CKS1 pcn01.bit._CKS1 +#define PCN01_CKS0 pcn01.bit._CKS0 +#define PCN01_PGMS pcn01.bit._PGMS +#define PCN01_EGS1 pcn01.bit._EGS1 +#define PCN01_EGS0 pcn01.bit._EGS0 +#define PCN01_IREN pcn01.bit._IREN +#define PCN01_IRQF pcn01.bit._IRQF +#define PCN01_IRS1 pcn01.bit._IRS1 +#define PCN01_IRS0 pcn01.bit._IRS0 +#define PCN01_OSEL pcn01.bit._OSEL +#define PCN01_CKS pcn01.bitc._CKS +#define PCN01_EGS pcn01.bitc._EGS +#define PCN01_IRS pcn01.bitc._IRS +__IO_EXTERN PCNH01STR pcnh01; +#define PCNH01 pcnh01.byte +#define PCNH01_CNTE pcnh01.bit._CNTE +#define PCNH01_STGR pcnh01.bit._STGR +#define PCNH01_MDSE pcnh01.bit._MDSE +#define PCNH01_RTRG pcnh01.bit._RTRG +#define PCNH01_CKS1 pcnh01.bit._CKS1 +#define PCNH01_CKS0 pcnh01.bit._CKS0 +#define PCNH01_PGMS pcnh01.bit._PGMS +#define PCNH01_CKS pcnh01.bitc._CKS +__IO_EXTERN PCNL01STR pcnl01; +#define PCNL01 pcnl01.byte +#define PCNL01_EGS1 pcnl01.bit._EGS1 +#define PCNL01_EGS0 pcnl01.bit._EGS0 +#define PCNL01_IREN pcnl01.bit._IREN +#define PCNL01_IRQF pcnl01.bit._IRQF +#define PCNL01_IRS1 pcnl01.bit._IRS1 +#define PCNL01_IRS0 pcnl01.bit._IRS0 +#define PCNL01_OSEL pcnl01.bit._OSEL +#define PCNL01_EGS pcnl01.bitc._EGS +#define PCNL01_IRS pcnl01.bitc._IRS +__IO_EXTERN IO_WORD ptmr02; /* PPG 2 */ +#define PTMR02 ptmr02 +__IO_EXTERN IO_WORD pcsr02; +#define PCSR02 pcsr02 +__IO_EXTERN IO_WORD pdut02; +#define PDUT02 pdut02 +__IO_EXTERN PCN02STR pcn02; +#define PCN02 pcn02.word +#define PCN02_CNTE pcn02.bit._CNTE +#define PCN02_STGR pcn02.bit._STGR +#define PCN02_MDSE pcn02.bit._MDSE +#define PCN02_RTRG pcn02.bit._RTRG +#define PCN02_CKS1 pcn02.bit._CKS1 +#define PCN02_CKS0 pcn02.bit._CKS0 +#define PCN02_PGMS pcn02.bit._PGMS +#define PCN02_EGS1 pcn02.bit._EGS1 +#define PCN02_EGS0 pcn02.bit._EGS0 +#define PCN02_IREN pcn02.bit._IREN +#define PCN02_IRQF pcn02.bit._IRQF +#define PCN02_IRS1 pcn02.bit._IRS1 +#define PCN02_IRS0 pcn02.bit._IRS0 +#define PCN02_OSEL pcn02.bit._OSEL +#define PCN02_CKS pcn02.bitc._CKS +#define PCN02_EGS pcn02.bitc._EGS +#define PCN02_IRS pcn02.bitc._IRS +__IO_EXTERN PCNH02STR pcnh02; +#define PCNH02 pcnh02.byte +#define PCNH02_CNTE pcnh02.bit._CNTE +#define PCNH02_STGR pcnh02.bit._STGR +#define PCNH02_MDSE pcnh02.bit._MDSE +#define PCNH02_RTRG pcnh02.bit._RTRG +#define PCNH02_CKS1 pcnh02.bit._CKS1 +#define PCNH02_CKS0 pcnh02.bit._CKS0 +#define PCNH02_PGMS pcnh02.bit._PGMS +#define PCNH02_CKS pcnh02.bitc._CKS +__IO_EXTERN PCNL02STR pcnl02; +#define PCNL02 pcnl02.byte +#define PCNL02_EGS1 pcnl02.bit._EGS1 +#define PCNL02_EGS0 pcnl02.bit._EGS0 +#define PCNL02_IREN pcnl02.bit._IREN +#define PCNL02_IRQF pcnl02.bit._IRQF +#define PCNL02_IRS1 pcnl02.bit._IRS1 +#define PCNL02_IRS0 pcnl02.bit._IRS0 +#define PCNL02_OSEL pcnl02.bit._OSEL +#define PCNL02_EGS pcnl02.bitc._EGS +#define PCNL02_IRS pcnl02.bitc._IRS +__IO_EXTERN IO_WORD ptmr03; /* PPG 3 */ +#define PTMR03 ptmr03 +__IO_EXTERN IO_WORD pcsr03; +#define PCSR03 pcsr03 +__IO_EXTERN IO_WORD pdut03; +#define PDUT03 pdut03 +__IO_EXTERN PCN03STR pcn03; +#define PCN03 pcn03.word +#define PCN03_CNTE pcn03.bit._CNTE +#define PCN03_STGR pcn03.bit._STGR +#define PCN03_MDSE pcn03.bit._MDSE +#define PCN03_RTRG pcn03.bit._RTRG +#define PCN03_CKS1 pcn03.bit._CKS1 +#define PCN03_CKS0 pcn03.bit._CKS0 +#define PCN03_PGMS pcn03.bit._PGMS +#define PCN03_EGS1 pcn03.bit._EGS1 +#define PCN03_EGS0 pcn03.bit._EGS0 +#define PCN03_IREN pcn03.bit._IREN +#define PCN03_IRQF pcn03.bit._IRQF +#define PCN03_IRS1 pcn03.bit._IRS1 +#define PCN03_IRS0 pcn03.bit._IRS0 +#define PCN03_OSEL pcn03.bit._OSEL +#define PCN03_CKS pcn03.bitc._CKS +#define PCN03_EGS pcn03.bitc._EGS +#define PCN03_IRS pcn03.bitc._IRS +__IO_EXTERN PCNH03STR pcnh03; +#define PCNH03 pcnh03.byte +#define PCNH03_CNTE pcnh03.bit._CNTE +#define PCNH03_STGR pcnh03.bit._STGR +#define PCNH03_MDSE pcnh03.bit._MDSE +#define PCNH03_RTRG pcnh03.bit._RTRG +#define PCNH03_CKS1 pcnh03.bit._CKS1 +#define PCNH03_CKS0 pcnh03.bit._CKS0 +#define PCNH03_PGMS pcnh03.bit._PGMS +#define PCNH03_CKS pcnh03.bitc._CKS +__IO_EXTERN PCNL03STR pcnl03; +#define PCNL03 pcnl03.byte +#define PCNL03_EGS1 pcnl03.bit._EGS1 +#define PCNL03_EGS0 pcnl03.bit._EGS0 +#define PCNL03_IREN pcnl03.bit._IREN +#define PCNL03_IRQF pcnl03.bit._IRQF +#define PCNL03_IRS1 pcnl03.bit._IRS1 +#define PCNL03_IRS0 pcnl03.bit._IRS0 +#define PCNL03_OSEL pcnl03.bit._OSEL +#define PCNL03_EGS pcnl03.bitc._EGS +#define PCNL03_IRS pcnl03.bitc._IRS +__IO_EXTERN IO_WORD ptmr04; /* PPG 4 */ +#define PTMR04 ptmr04 +__IO_EXTERN IO_WORD pcsr04; +#define PCSR04 pcsr04 +__IO_EXTERN IO_WORD pdut04; +#define PDUT04 pdut04 +__IO_EXTERN PCN04STR pcn04; +#define PCN04 pcn04.word +#define PCN04_CNTE pcn04.bit._CNTE +#define PCN04_STGR pcn04.bit._STGR +#define PCN04_MDSE pcn04.bit._MDSE +#define PCN04_RTRG pcn04.bit._RTRG +#define PCN04_CKS1 pcn04.bit._CKS1 +#define PCN04_CKS0 pcn04.bit._CKS0 +#define PCN04_PGMS pcn04.bit._PGMS +#define PCN04_EGS1 pcn04.bit._EGS1 +#define PCN04_EGS0 pcn04.bit._EGS0 +#define PCN04_IREN pcn04.bit._IREN +#define PCN04_IRQF pcn04.bit._IRQF +#define PCN04_IRS1 pcn04.bit._IRS1 +#define PCN04_IRS0 pcn04.bit._IRS0 +#define PCN04_OSEL pcn04.bit._OSEL +#define PCN04_CKS pcn04.bitc._CKS +#define PCN04_EGS pcn04.bitc._EGS +#define PCN04_IRS pcn04.bitc._IRS +__IO_EXTERN PCNH04STR pcnh04; +#define PCNH04 pcnh04.byte +#define PCNH04_CNTE pcnh04.bit._CNTE +#define PCNH04_STGR pcnh04.bit._STGR +#define PCNH04_MDSE pcnh04.bit._MDSE +#define PCNH04_RTRG pcnh04.bit._RTRG +#define PCNH04_CKS1 pcnh04.bit._CKS1 +#define PCNH04_CKS0 pcnh04.bit._CKS0 +#define PCNH04_PGMS pcnh04.bit._PGMS +#define PCNH04_CKS pcnh04.bitc._CKS +__IO_EXTERN PCNL04STR pcnl04; +#define PCNL04 pcnl04.byte +#define PCNL04_EGS1 pcnl04.bit._EGS1 +#define PCNL04_EGS0 pcnl04.bit._EGS0 +#define PCNL04_IREN pcnl04.bit._IREN +#define PCNL04_IRQF pcnl04.bit._IRQF +#define PCNL04_IRS1 pcnl04.bit._IRS1 +#define PCNL04_IRS0 pcnl04.bit._IRS0 +#define PCNL04_OSEL pcnl04.bit._OSEL +#define PCNL04_EGS pcnl04.bitc._EGS +#define PCNL04_IRS pcnl04.bitc._IRS +__IO_EXTERN IO_WORD ptmr05; /* PPG 5 */ +#define PTMR05 ptmr05 +__IO_EXTERN IO_WORD pcsr05; +#define PCSR05 pcsr05 +__IO_EXTERN IO_WORD pdut05; +#define PDUT05 pdut05 +__IO_EXTERN PCN05STR pcn05; +#define PCN05 pcn05.word +#define PCN05_CNTE pcn05.bit._CNTE +#define PCN05_STGR pcn05.bit._STGR +#define PCN05_MDSE pcn05.bit._MDSE +#define PCN05_RTRG pcn05.bit._RTRG +#define PCN05_CKS1 pcn05.bit._CKS1 +#define PCN05_CKS0 pcn05.bit._CKS0 +#define PCN05_PGMS pcn05.bit._PGMS +#define PCN05_EGS1 pcn05.bit._EGS1 +#define PCN05_EGS0 pcn05.bit._EGS0 +#define PCN05_IREN pcn05.bit._IREN +#define PCN05_IRQF pcn05.bit._IRQF +#define PCN05_IRS1 pcn05.bit._IRS1 +#define PCN05_IRS0 pcn05.bit._IRS0 +#define PCN05_OSEL pcn05.bit._OSEL +#define PCN05_CKS pcn05.bitc._CKS +#define PCN05_EGS pcn05.bitc._EGS +#define PCN05_IRS pcn05.bitc._IRS +__IO_EXTERN PCNH05STR pcnh05; +#define PCNH05 pcnh05.byte +#define PCNH05_CNTE pcnh05.bit._CNTE +#define PCNH05_STGR pcnh05.bit._STGR +#define PCNH05_MDSE pcnh05.bit._MDSE +#define PCNH05_RTRG pcnh05.bit._RTRG +#define PCNH05_CKS1 pcnh05.bit._CKS1 +#define PCNH05_CKS0 pcnh05.bit._CKS0 +#define PCNH05_PGMS pcnh05.bit._PGMS +#define PCNH05_CKS pcnh05.bitc._CKS +__IO_EXTERN PCNL05STR pcnl05; +#define PCNL05 pcnl05.byte +#define PCNL05_EGS1 pcnl05.bit._EGS1 +#define PCNL05_EGS0 pcnl05.bit._EGS0 +#define PCNL05_IREN pcnl05.bit._IREN +#define PCNL05_IRQF pcnl05.bit._IRQF +#define PCNL05_IRS1 pcnl05.bit._IRS1 +#define PCNL05_IRS0 pcnl05.bit._IRS0 +#define PCNL05_OSEL pcnl05.bit._OSEL +#define PCNL05_EGS pcnl05.bitc._EGS +#define PCNL05_IRS pcnl05.bitc._IRS +__IO_EXTERN IO_WORD ptmr06; /* PPG 6 */ +#define PTMR06 ptmr06 +__IO_EXTERN IO_WORD pcsr06; +#define PCSR06 pcsr06 +__IO_EXTERN IO_WORD pdut06; +#define PDUT06 pdut06 +__IO_EXTERN PCN06STR pcn06; +#define PCN06 pcn06.word +#define PCN06_CNTE pcn06.bit._CNTE +#define PCN06_STGR pcn06.bit._STGR +#define PCN06_MDSE pcn06.bit._MDSE +#define PCN06_RTRG pcn06.bit._RTRG +#define PCN06_CKS1 pcn06.bit._CKS1 +#define PCN06_CKS0 pcn06.bit._CKS0 +#define PCN06_PGMS pcn06.bit._PGMS +#define PCN06_EGS1 pcn06.bit._EGS1 +#define PCN06_EGS0 pcn06.bit._EGS0 +#define PCN06_IREN pcn06.bit._IREN +#define PCN06_IRQF pcn06.bit._IRQF +#define PCN06_IRS1 pcn06.bit._IRS1 +#define PCN06_IRS0 pcn06.bit._IRS0 +#define PCN06_OSEL pcn06.bit._OSEL +#define PCN06_CKS pcn06.bitc._CKS +#define PCN06_EGS pcn06.bitc._EGS +#define PCN06_IRS pcn06.bitc._IRS +__IO_EXTERN PCNH06STR pcnh06; +#define PCNH06 pcnh06.byte +#define PCNH06_CNTE pcnh06.bit._CNTE +#define PCNH06_STGR pcnh06.bit._STGR +#define PCNH06_MDSE pcnh06.bit._MDSE +#define PCNH06_RTRG pcnh06.bit._RTRG +#define PCNH06_CKS1 pcnh06.bit._CKS1 +#define PCNH06_CKS0 pcnh06.bit._CKS0 +#define PCNH06_PGMS pcnh06.bit._PGMS +#define PCNH06_CKS pcnh06.bitc._CKS +__IO_EXTERN PCNL06STR pcnl06; +#define PCNL06 pcnl06.byte +#define PCNL06_EGS1 pcnl06.bit._EGS1 +#define PCNL06_EGS0 pcnl06.bit._EGS0 +#define PCNL06_IREN pcnl06.bit._IREN +#define PCNL06_IRQF pcnl06.bit._IRQF +#define PCNL06_IRS1 pcnl06.bit._IRS1 +#define PCNL06_IRS0 pcnl06.bit._IRS0 +#define PCNL06_OSEL pcnl06.bit._OSEL +#define PCNL06_EGS pcnl06.bitc._EGS +#define PCNL06_IRS pcnl06.bitc._IRS +__IO_EXTERN IO_WORD ptmr07; /* PPG 7 */ +#define PTMR07 ptmr07 +__IO_EXTERN IO_WORD pcsr07; +#define PCSR07 pcsr07 +__IO_EXTERN IO_WORD pdut07; +#define PDUT07 pdut07 +__IO_EXTERN PCN07STR pcn07; +#define PCN07 pcn07.word +#define PCN07_CNTE pcn07.bit._CNTE +#define PCN07_STGR pcn07.bit._STGR +#define PCN07_MDSE pcn07.bit._MDSE +#define PCN07_RTRG pcn07.bit._RTRG +#define PCN07_CKS1 pcn07.bit._CKS1 +#define PCN07_CKS0 pcn07.bit._CKS0 +#define PCN07_PGMS pcn07.bit._PGMS +#define PCN07_EGS1 pcn07.bit._EGS1 +#define PCN07_EGS0 pcn07.bit._EGS0 +#define PCN07_IREN pcn07.bit._IREN +#define PCN07_IRQF pcn07.bit._IRQF +#define PCN07_IRS1 pcn07.bit._IRS1 +#define PCN07_IRS0 pcn07.bit._IRS0 +#define PCN07_OSEL pcn07.bit._OSEL +#define PCN07_CKS pcn07.bitc._CKS +#define PCN07_EGS pcn07.bitc._EGS +#define PCN07_IRS pcn07.bitc._IRS +__IO_EXTERN PCNH07STR pcnh07; +#define PCNH07 pcnh07.byte +#define PCNH07_CNTE pcnh07.bit._CNTE +#define PCNH07_STGR pcnh07.bit._STGR +#define PCNH07_MDSE pcnh07.bit._MDSE +#define PCNH07_RTRG pcnh07.bit._RTRG +#define PCNH07_CKS1 pcnh07.bit._CKS1 +#define PCNH07_CKS0 pcnh07.bit._CKS0 +#define PCNH07_PGMS pcnh07.bit._PGMS +#define PCNH07_CKS pcnh07.bitc._CKS +__IO_EXTERN PCNL07STR pcnl07; +#define PCNL07 pcnl07.byte +#define PCNL07_EGS1 pcnl07.bit._EGS1 +#define PCNL07_EGS0 pcnl07.bit._EGS0 +#define PCNL07_IREN pcnl07.bit._IREN +#define PCNL07_IRQF pcnl07.bit._IRQF +#define PCNL07_IRS1 pcnl07.bit._IRS1 +#define PCNL07_IRS0 pcnl07.bit._IRS0 +#define PCNL07_OSEL pcnl07.bit._OSEL +#define PCNL07_EGS pcnl07.bitc._EGS +#define PCNL07_IRS pcnl07.bitc._IRS +__IO_EXTERN IO_WORD ptmr08; /* PPG 8 */ +#define PTMR08 ptmr08 +__IO_EXTERN IO_WORD pcsr08; +#define PCSR08 pcsr08 +__IO_EXTERN IO_WORD pdut08; +#define PDUT08 pdut08 +__IO_EXTERN PCN08STR pcn08; +#define PCN08 pcn08.word +#define PCN08_CNTE pcn08.bit._CNTE +#define PCN08_STGR pcn08.bit._STGR +#define PCN08_MDSE pcn08.bit._MDSE +#define PCN08_RTRG pcn08.bit._RTRG +#define PCN08_CKS1 pcn08.bit._CKS1 +#define PCN08_CKS0 pcn08.bit._CKS0 +#define PCN08_PGMS pcn08.bit._PGMS +#define PCN08_EGS1 pcn08.bit._EGS1 +#define PCN08_EGS0 pcn08.bit._EGS0 +#define PCN08_IREN pcn08.bit._IREN +#define PCN08_IRQF pcn08.bit._IRQF +#define PCN08_IRS1 pcn08.bit._IRS1 +#define PCN08_IRS0 pcn08.bit._IRS0 +#define PCN08_OSEL pcn08.bit._OSEL +#define PCN08_CKS pcn08.bitc._CKS +#define PCN08_EGS pcn08.bitc._EGS +#define PCN08_IRS pcn08.bitc._IRS +__IO_EXTERN PCNH08STR pcnh08; +#define PCNH08 pcnh08.byte +#define PCNH08_CNTE pcnh08.bit._CNTE +#define PCNH08_STGR pcnh08.bit._STGR +#define PCNH08_MDSE pcnh08.bit._MDSE +#define PCNH08_RTRG pcnh08.bit._RTRG +#define PCNH08_CKS1 pcnh08.bit._CKS1 +#define PCNH08_CKS0 pcnh08.bit._CKS0 +#define PCNH08_PGMS pcnh08.bit._PGMS +#define PCNH08_CKS pcnh08.bitc._CKS +__IO_EXTERN PCNL08STR pcnl08; +#define PCNL08 pcnl08.byte +#define PCNL08_EGS1 pcnl08.bit._EGS1 +#define PCNL08_EGS0 pcnl08.bit._EGS0 +#define PCNL08_IREN pcnl08.bit._IREN +#define PCNL08_IRQF pcnl08.bit._IRQF +#define PCNL08_IRS1 pcnl08.bit._IRS1 +#define PCNL08_IRS0 pcnl08.bit._IRS0 +#define PCNL08_OSEL pcnl08.bit._OSEL +#define PCNL08_EGS pcnl08.bitc._EGS +#define PCNL08_IRS pcnl08.bitc._IRS +__IO_EXTERN IO_WORD ptmr09; /* PPG 9 */ +#define PTMR09 ptmr09 +__IO_EXTERN IO_WORD pcsr09; +#define PCSR09 pcsr09 +__IO_EXTERN IO_WORD pdut09; +#define PDUT09 pdut09 +__IO_EXTERN PCN09STR pcn09; +#define PCN09 pcn09.word +#define PCN09_CNTE pcn09.bit._CNTE +#define PCN09_STGR pcn09.bit._STGR +#define PCN09_MDSE pcn09.bit._MDSE +#define PCN09_RTRG pcn09.bit._RTRG +#define PCN09_CKS1 pcn09.bit._CKS1 +#define PCN09_CKS0 pcn09.bit._CKS0 +#define PCN09_PGMS pcn09.bit._PGMS +#define PCN09_EGS1 pcn09.bit._EGS1 +#define PCN09_EGS0 pcn09.bit._EGS0 +#define PCN09_IREN pcn09.bit._IREN +#define PCN09_IRQF pcn09.bit._IRQF +#define PCN09_IRS1 pcn09.bit._IRS1 +#define PCN09_IRS0 pcn09.bit._IRS0 +#define PCN09_OSEL pcn09.bit._OSEL +#define PCN09_CKS pcn09.bitc._CKS +#define PCN09_EGS pcn09.bitc._EGS +#define PCN09_IRS pcn09.bitc._IRS +__IO_EXTERN PCNH09STR pcnh09; +#define PCNH09 pcnh09.byte +#define PCNH09_CNTE pcnh09.bit._CNTE +#define PCNH09_STGR pcnh09.bit._STGR +#define PCNH09_MDSE pcnh09.bit._MDSE +#define PCNH09_RTRG pcnh09.bit._RTRG +#define PCNH09_CKS1 pcnh09.bit._CKS1 +#define PCNH09_CKS0 pcnh09.bit._CKS0 +#define PCNH09_PGMS pcnh09.bit._PGMS +#define PCNH09_CKS pcnh09.bitc._CKS +__IO_EXTERN PCNL09STR pcnl09; +#define PCNL09 pcnl09.byte +#define PCNL09_EGS1 pcnl09.bit._EGS1 +#define PCNL09_EGS0 pcnl09.bit._EGS0 +#define PCNL09_IREN pcnl09.bit._IREN +#define PCNL09_IRQF pcnl09.bit._IRQF +#define PCNL09_IRS1 pcnl09.bit._IRS1 +#define PCNL09_IRS0 pcnl09.bit._IRS0 +#define PCNL09_OSEL pcnl09.bit._OSEL +#define PCNL09_EGS pcnl09.bitc._EGS +#define PCNL09_IRS pcnl09.bitc._IRS +__IO_EXTERN IO_WORD ptmr10; /* PPG 10 */ +#define PTMR10 ptmr10 +__IO_EXTERN IO_WORD pcsr10; +#define PCSR10 pcsr10 +__IO_EXTERN IO_WORD pdut10; +#define PDUT10 pdut10 +__IO_EXTERN PCN10STR pcn10; +#define PCN10 pcn10.word +#define PCN10_CNTE pcn10.bit._CNTE +#define PCN10_STGR pcn10.bit._STGR +#define PCN10_MDSE pcn10.bit._MDSE +#define PCN10_RTRG pcn10.bit._RTRG +#define PCN10_CKS1 pcn10.bit._CKS1 +#define PCN10_CKS0 pcn10.bit._CKS0 +#define PCN10_PGMS pcn10.bit._PGMS +#define PCN10_EGS1 pcn10.bit._EGS1 +#define PCN10_EGS0 pcn10.bit._EGS0 +#define PCN10_IREN pcn10.bit._IREN +#define PCN10_IRQF pcn10.bit._IRQF +#define PCN10_IRS1 pcn10.bit._IRS1 +#define PCN10_IRS0 pcn10.bit._IRS0 +#define PCN10_OSEL pcn10.bit._OSEL +#define PCN10_CKS pcn10.bitc._CKS +#define PCN10_EGS pcn10.bitc._EGS +#define PCN10_IRS pcn10.bitc._IRS +__IO_EXTERN PCNH10STR pcnh10; +#define PCNH10 pcnh10.byte +#define PCNH10_CNTE pcnh10.bit._CNTE +#define PCNH10_STGR pcnh10.bit._STGR +#define PCNH10_MDSE pcnh10.bit._MDSE +#define PCNH10_RTRG pcnh10.bit._RTRG +#define PCNH10_CKS1 pcnh10.bit._CKS1 +#define PCNH10_CKS0 pcnh10.bit._CKS0 +#define PCNH10_PGMS pcnh10.bit._PGMS +#define PCNH10_CKS pcnh10.bitc._CKS +__IO_EXTERN PCNL10STR pcnl10; +#define PCNL10 pcnl10.byte +#define PCNL10_EGS1 pcnl10.bit._EGS1 +#define PCNL10_EGS0 pcnl10.bit._EGS0 +#define PCNL10_IREN pcnl10.bit._IREN +#define PCNL10_IRQF pcnl10.bit._IRQF +#define PCNL10_IRS1 pcnl10.bit._IRS1 +#define PCNL10_IRS0 pcnl10.bit._IRS0 +#define PCNL10_OSEL pcnl10.bit._OSEL +#define PCNL10_EGS pcnl10.bitc._EGS +#define PCNL10_IRS pcnl10.bitc._IRS +__IO_EXTERN IO_WORD ptmr11; /* PPG 11 */ +#define PTMR11 ptmr11 +__IO_EXTERN IO_WORD pcsr11; +#define PCSR11 pcsr11 +__IO_EXTERN IO_WORD pdut11; +#define PDUT11 pdut11 +__IO_EXTERN PCN11STR pcn11; +#define PCN11 pcn11.word +#define PCN11_CNTE pcn11.bit._CNTE +#define PCN11_STGR pcn11.bit._STGR +#define PCN11_MDSE pcn11.bit._MDSE +#define PCN11_RTRG pcn11.bit._RTRG +#define PCN11_CKS1 pcn11.bit._CKS1 +#define PCN11_CKS0 pcn11.bit._CKS0 +#define PCN11_PGMS pcn11.bit._PGMS +#define PCN11_EGS1 pcn11.bit._EGS1 +#define PCN11_EGS0 pcn11.bit._EGS0 +#define PCN11_IREN pcn11.bit._IREN +#define PCN11_IRQF pcn11.bit._IRQF +#define PCN11_IRS1 pcn11.bit._IRS1 +#define PCN11_IRS0 pcn11.bit._IRS0 +#define PCN11_OSEL pcn11.bit._OSEL +#define PCN11_CKS pcn11.bitc._CKS +#define PCN11_EGS pcn11.bitc._EGS +#define PCN11_IRS pcn11.bitc._IRS +__IO_EXTERN PCNH11STR pcnh11; +#define PCNH11 pcnh11.byte +#define PCNH11_CNTE pcnh11.bit._CNTE +#define PCNH11_STGR pcnh11.bit._STGR +#define PCNH11_MDSE pcnh11.bit._MDSE +#define PCNH11_RTRG pcnh11.bit._RTRG +#define PCNH11_CKS1 pcnh11.bit._CKS1 +#define PCNH11_CKS0 pcnh11.bit._CKS0 +#define PCNH11_PGMS pcnh11.bit._PGMS +#define PCNH11_CKS pcnh11.bitc._CKS +__IO_EXTERN PCNL11STR pcnl11; +#define PCNL11 pcnl11.byte +#define PCNL11_EGS1 pcnl11.bit._EGS1 +#define PCNL11_EGS0 pcnl11.bit._EGS0 +#define PCNL11_IREN pcnl11.bit._IREN +#define PCNL11_IRQF pcnl11.bit._IRQF +#define PCNL11_IRS1 pcnl11.bit._IRS1 +#define PCNL11_IRS0 pcnl11.bit._IRS0 +#define PCNL11_OSEL pcnl11.bit._OSEL +#define PCNL11_EGS pcnl11.bitc._EGS +#define PCNL11_IRS pcnl11.bitc._IRS +__IO_EXTERN ICS01STR ics01; /* Input Capture 0-3 */ +#define ICS01 ics01.byte +#define ICS01_ICP1 ics01.bit._ICP1 +#define ICS01_ICP0 ics01.bit._ICP0 +#define ICS01_ICE1 ics01.bit._ICE1 +#define ICS01_ICE0 ics01.bit._ICE0 +#define ICS01_EG11 ics01.bit._EG11 +#define ICS01_EG10 ics01.bit._EG10 +#define ICS01_EG01 ics01.bit._EG01 +#define ICS01_EG00 ics01.bit._EG00 +#define ICS01_EG1 ics01.bitc._EG1 +#define ICS01_EG0 ics01.bitc._EG0 +__IO_EXTERN ICS23STR ics23; +#define ICS23 ics23.byte +#define ICS23_ICP3 ics23.bit._ICP3 +#define ICS23_ICP2 ics23.bit._ICP2 +#define ICS23_ICE3 ics23.bit._ICE3 +#define ICS23_ICE2 ics23.bit._ICE2 +#define ICS23_EG31 ics23.bit._EG31 +#define ICS23_EG30 ics23.bit._EG30 +#define ICS23_EG21 ics23.bit._EG21 +#define ICS23_EG20 ics23.bit._EG20 +#define ICS23_EG3 ics23.bitc._EG3 +#define ICS23_EG2 ics23.bitc._EG2 +__IO_EXTERN IPCP0STR ipcp0; +#define IPCP0 ipcp0.word +#define IPCP0_CP15 ipcp0.bit._CP15 +#define IPCP0_CP14 ipcp0.bit._CP14 +#define IPCP0_CP13 ipcp0.bit._CP13 +#define IPCP0_CP12 ipcp0.bit._CP12 +#define IPCP0_CP11 ipcp0.bit._CP11 +#define IPCP0_CP10 ipcp0.bit._CP10 +#define IPCP0_CP9 ipcp0.bit._CP9 +#define IPCP0_CP8 ipcp0.bit._CP8 +#define IPCP0_CP7 ipcp0.bit._CP7 +#define IPCP0_CP6 ipcp0.bit._CP6 +#define IPCP0_CP5 ipcp0.bit._CP5 +#define IPCP0_CP4 ipcp0.bit._CP4 +#define IPCP0_CP3 ipcp0.bit._CP3 +#define IPCP0_CP2 ipcp0.bit._CP2 +#define IPCP0_CP1 ipcp0.bit._CP1 +#define IPCP0_CP0 ipcp0.bit._CP0 +__IO_EXTERN IPCP1STR ipcp1; +#define IPCP1 ipcp1.word +#define IPCP1_CP15 ipcp1.bit._CP15 +#define IPCP1_CP14 ipcp1.bit._CP14 +#define IPCP1_CP13 ipcp1.bit._CP13 +#define IPCP1_CP12 ipcp1.bit._CP12 +#define IPCP1_CP11 ipcp1.bit._CP11 +#define IPCP1_CP10 ipcp1.bit._CP10 +#define IPCP1_CP9 ipcp1.bit._CP9 +#define IPCP1_CP8 ipcp1.bit._CP8 +#define IPCP1_CP7 ipcp1.bit._CP7 +#define IPCP1_CP6 ipcp1.bit._CP6 +#define IPCP1_CP5 ipcp1.bit._CP5 +#define IPCP1_CP4 ipcp1.bit._CP4 +#define IPCP1_CP3 ipcp1.bit._CP3 +#define IPCP1_CP2 ipcp1.bit._CP2 +#define IPCP1_CP1 ipcp1.bit._CP1 +#define IPCP1_CP0 ipcp1.bit._CP0 +__IO_EXTERN IPCP2STR ipcp2; +#define IPCP2 ipcp2.word +#define IPCP2_CP15 ipcp2.bit._CP15 +#define IPCP2_CP14 ipcp2.bit._CP14 +#define IPCP2_CP13 ipcp2.bit._CP13 +#define IPCP2_CP12 ipcp2.bit._CP12 +#define IPCP2_CP11 ipcp2.bit._CP11 +#define IPCP2_CP10 ipcp2.bit._CP10 +#define IPCP2_CP9 ipcp2.bit._CP9 +#define IPCP2_CP8 ipcp2.bit._CP8 +#define IPCP2_CP7 ipcp2.bit._CP7 +#define IPCP2_CP6 ipcp2.bit._CP6 +#define IPCP2_CP5 ipcp2.bit._CP5 +#define IPCP2_CP4 ipcp2.bit._CP4 +#define IPCP2_CP3 ipcp2.bit._CP3 +#define IPCP2_CP2 ipcp2.bit._CP2 +#define IPCP2_CP1 ipcp2.bit._CP1 +#define IPCP2_CP0 ipcp2.bit._CP0 +__IO_EXTERN IPCP3STR ipcp3; +#define IPCP3 ipcp3.word +#define IPCP3_CP15 ipcp3.bit._CP15 +#define IPCP3_CP14 ipcp3.bit._CP14 +#define IPCP3_CP13 ipcp3.bit._CP13 +#define IPCP3_CP12 ipcp3.bit._CP12 +#define IPCP3_CP11 ipcp3.bit._CP11 +#define IPCP3_CP10 ipcp3.bit._CP10 +#define IPCP3_CP9 ipcp3.bit._CP9 +#define IPCP3_CP8 ipcp3.bit._CP8 +#define IPCP3_CP7 ipcp3.bit._CP7 +#define IPCP3_CP6 ipcp3.bit._CP6 +#define IPCP3_CP5 ipcp3.bit._CP5 +#define IPCP3_CP4 ipcp3.bit._CP4 +#define IPCP3_CP3 ipcp3.bit._CP3 +#define IPCP3_CP2 ipcp3.bit._CP2 +#define IPCP3_CP1 ipcp3.bit._CP1 +#define IPCP3_CP0 ipcp3.bit._CP0 +__IO_EXTERN OCS01STR ocs01; /* Output Compare 0-3 */ +#define OCS01 ocs01.word +#define OCS01_CMOD ocs01.bit._CMOD +#define OCS01_OTD1 ocs01.bit._OTD1 +#define OCS01_OTD0 ocs01.bit._OTD0 +#define OCS01_ICP1 ocs01.bit._ICP1 +#define OCS01_ICP0 ocs01.bit._ICP0 +#define OCS01_ICE1 ocs01.bit._ICE1 +#define OCS01_ICE0 ocs01.bit._ICE0 +#define OCS01_CST1 ocs01.bit._CST1 +#define OCS01_CST0 ocs01.bit._CST0 +__IO_EXTERN OCS23STR ocs23; +#define OCS23 ocs23.word +#define OCS23_CMOD ocs23.bit._CMOD +#define OCS23_OTD3 ocs23.bit._OTD3 +#define OCS23_OTD2 ocs23.bit._OTD2 +#define OCS23_ICP3 ocs23.bit._ICP3 +#define OCS23_ICP2 ocs23.bit._ICP2 +#define OCS23_ICE3 ocs23.bit._ICE3 +#define OCS23_ICE2 ocs23.bit._ICE2 +#define OCS23_CST3 ocs23.bit._CST3 +#define OCS23_CST2 ocs23.bit._CST2 +__IO_EXTERN OCCP0STR occp0; +#define OCCP0 occp0.word +#define OCCP0_C15 occp0.bit._C15 +#define OCCP0_C14 occp0.bit._C14 +#define OCCP0_C13 occp0.bit._C13 +#define OCCP0_C12 occp0.bit._C12 +#define OCCP0_C11 occp0.bit._C11 +#define OCCP0_C10 occp0.bit._C10 +#define OCCP0_C9 occp0.bit._C9 +#define OCCP0_C8 occp0.bit._C8 +#define OCCP0_C7 occp0.bit._C7 +#define OCCP0_C6 occp0.bit._C6 +#define OCCP0_C5 occp0.bit._C5 +#define OCCP0_C4 occp0.bit._C4 +#define OCCP0_C3 occp0.bit._C3 +#define OCCP0_C2 occp0.bit._C2 +#define OCCP0_C1 occp0.bit._C1 +#define OCCP0_C0 occp0.bit._C0 +__IO_EXTERN OCCP1STR occp1; +#define OCCP1 occp1.word +#define OCCP1_C15 occp1.bit._C15 +#define OCCP1_C14 occp1.bit._C14 +#define OCCP1_C13 occp1.bit._C13 +#define OCCP1_C12 occp1.bit._C12 +#define OCCP1_C11 occp1.bit._C11 +#define OCCP1_C10 occp1.bit._C10 +#define OCCP1_C9 occp1.bit._C9 +#define OCCP1_C8 occp1.bit._C8 +#define OCCP1_C7 occp1.bit._C7 +#define OCCP1_C6 occp1.bit._C6 +#define OCCP1_C5 occp1.bit._C5 +#define OCCP1_C4 occp1.bit._C4 +#define OCCP1_C3 occp1.bit._C3 +#define OCCP1_C2 occp1.bit._C2 +#define OCCP1_C1 occp1.bit._C1 +#define OCCP1_C0 occp1.bit._C0 +__IO_EXTERN OCCP2STR occp2; +#define OCCP2 occp2.word +#define OCCP2_C15 occp2.bit._C15 +#define OCCP2_C14 occp2.bit._C14 +#define OCCP2_C13 occp2.bit._C13 +#define OCCP2_C12 occp2.bit._C12 +#define OCCP2_C11 occp2.bit._C11 +#define OCCP2_C10 occp2.bit._C10 +#define OCCP2_C9 occp2.bit._C9 +#define OCCP2_C8 occp2.bit._C8 +#define OCCP2_C7 occp2.bit._C7 +#define OCCP2_C6 occp2.bit._C6 +#define OCCP2_C5 occp2.bit._C5 +#define OCCP2_C4 occp2.bit._C4 +#define OCCP2_C3 occp2.bit._C3 +#define OCCP2_C2 occp2.bit._C2 +#define OCCP2_C1 occp2.bit._C1 +#define OCCP2_C0 occp2.bit._C0 +__IO_EXTERN OCCP3STR occp3; +#define OCCP3 occp3.word +#define OCCP3_C15 occp3.bit._C15 +#define OCCP3_C14 occp3.bit._C14 +#define OCCP3_C13 occp3.bit._C13 +#define OCCP3_C12 occp3.bit._C12 +#define OCCP3_C11 occp3.bit._C11 +#define OCCP3_C10 occp3.bit._C10 +#define OCCP3_C9 occp3.bit._C9 +#define OCCP3_C8 occp3.bit._C8 +#define OCCP3_C7 occp3.bit._C7 +#define OCCP3_C6 occp3.bit._C6 +#define OCCP3_C5 occp3.bit._C5 +#define OCCP3_C4 occp3.bit._C4 +#define OCCP3_C3 occp3.bit._C3 +#define OCCP3_C2 occp3.bit._C2 +#define OCCP3_C1 occp3.bit._C1 +#define OCCP3_C0 occp3.bit._C0 +__IO_EXTERN ADERHSTR aderh; /* ADC */ +#define ADERH aderh.word +#define ADERH_ADE31 aderh.bit._ADE31 +#define ADERH_ADE30 aderh.bit._ADE30 +#define ADERH_ADE29 aderh.bit._ADE29 +#define ADERH_ADE28 aderh.bit._ADE28 +#define ADERH_ADE27 aderh.bit._ADE27 +#define ADERH_ADE26 aderh.bit._ADE26 +#define ADERH_ADE25 aderh.bit._ADE25 +#define ADERH_ADE24 aderh.bit._ADE24 +#define ADERH_ADE23 aderh.bit._ADE23 +#define ADERH_ADE22 aderh.bit._ADE22 +#define ADERH_ADE21 aderh.bit._ADE21 +#define ADERH_ADE20 aderh.bit._ADE20 +#define ADERH_ADE19 aderh.bit._ADE19 +#define ADERH_ADE18 aderh.bit._ADE18 +#define ADERH_ADE17 aderh.bit._ADE17 +#define ADERH_ADE16 aderh.bit._ADE16 +__IO_EXTERN ADERLSTR aderl; +#define ADERL aderl.word +#define ADERL_ADE15 aderl.bit._ADE15 +#define ADERL_ADE14 aderl.bit._ADE14 +#define ADERL_ADE13 aderl.bit._ADE13 +#define ADERL_ADE12 aderl.bit._ADE12 +#define ADERL_ADE11 aderl.bit._ADE11 +#define ADERL_ADE10 aderl.bit._ADE10 +#define ADERL_ADE9 aderl.bit._ADE9 +#define ADERL_ADE8 aderl.bit._ADE8 +#define ADERL_ADE7 aderl.bit._ADE7 +#define ADERL_ADE6 aderl.bit._ADE6 +#define ADERL_ADE5 aderl.bit._ADE5 +#define ADERL_ADE4 aderl.bit._ADE4 +#define ADERL_ADE3 aderl.bit._ADE3 +#define ADERL_ADE2 aderl.bit._ADE2 +#define ADERL_ADE1 aderl.bit._ADE1 +#define ADERL_ADE0 aderl.bit._ADE0 +__IO_EXTERN IO_LWORD ader; +#define ADER ader +__IO_EXTERN ADCS1STR adcs1; +#define ADCS1 adcs1.byte +#define ADCS1_BUSY adcs1.bit._BUSY +#define ADCS1_INT adcs1.bit._INT +#define ADCS1_INTE adcs1.bit._INTE +#define ADCS1_PAUS adcs1.bit._PAUS +#define ADCS1_STS1 adcs1.bit._STS1 +#define ADCS1_STS0 adcs1.bit._STS0 +#define ADCS1_STRT adcs1.bit._STRT +#define ADCS1_STS adcs1.bitc._STS +__IO_EXTERN ADCS0STR adcs0; +#define ADCS0 adcs0.byte +#define ADCS0_MD1 adcs0.bit._MD1 +#define ADCS0_MD0 adcs0.bit._MD0 +#define ADCS0_S10 adcs0.bit._S10 +#define ADCS0_ACH4 adcs0.bit._ACH4 +#define ADCS0_ACH3 adcs0.bit._ACH3 +#define ADCS0_ACH2 adcs0.bit._ACH2 +#define ADCS0_ACH1 adcs0.bit._ACH1 +#define ADCS0_ACH0 adcs0.bit._ACH0 +#define ADCS0_MD adcs0.bitc._MD +#define ADCS0_ACH adcs0.bitc._ACH +__IO_EXTERN IO_WORD adcs; +#define ADCS adcs +__IO_EXTERN ADCR1STR adcr1; +#define ADCR1 adcr1.byte +#define ADCR1_D9 adcr1.bit._D9 +#define ADCR1_D8 adcr1.bit._D8 +__IO_EXTERN ADCR0STR adcr0; +#define ADCR0 adcr0.byte +#define ADCR0_D7 adcr0.bit._D7 +#define ADCR0_D6 adcr0.bit._D6 +#define ADCR0_D5 adcr0.bit._D5 +#define ADCR0_D4 adcr0.bit._D4 +#define ADCR0_D3 adcr0.bit._D3 +#define ADCR0_D2 adcr0.bit._D2 +#define ADCR0_D1 adcr0.bit._D1 +#define ADCR0_D0 adcr0.bit._D0 +__IO_EXTERN IO_WORD adcr; +#define ADCR adcr +__IO_EXTERN ADCT1STR adct1; +#define ADCT1 adct1.byte +#define ADCT1_CT5 adct1.bit._CT5 +#define ADCT1_CT4 adct1.bit._CT4 +#define ADCT1_CT3 adct1.bit._CT3 +#define ADCT1_CT2 adct1.bit._CT2 +#define ADCT1_CT1 adct1.bit._CT1 +#define ADCT1_CT0 adct1.bit._CT0 +#define ADCT1_ST9 adct1.bit._ST9 +#define ADCT1_ST8 adct1.bit._ST8 +__IO_EXTERN ADCT0STR adct0; +#define ADCT0 adct0.byte +#define ADCT0_ST7 adct0.bit._ST7 +#define ADCT0_ST6 adct0.bit._ST6 +#define ADCT0_ST5 adct0.bit._ST5 +#define ADCT0_ST4 adct0.bit._ST4 +#define ADCT0_ST3 adct0.bit._ST3 +#define ADCT0_ST2 adct0.bit._ST2 +#define ADCT0_ST1 adct0.bit._ST1 +#define ADCT0_ST0 adct0.bit._ST0 +__IO_EXTERN IO_WORD adct; +#define ADCT adct +__IO_EXTERN ADSCHSTR adsch; +#define ADSCH adsch.byte +#define ADSCH_ANS4 adsch.bit._ANS4 +#define ADSCH_ANS3 adsch.bit._ANS3 +#define ADSCH_ANS2 adsch.bit._ANS2 +#define ADSCH_ANS1 adsch.bit._ANS1 +#define ADSCH_ASN0 adsch.bit._ASN0 +#define ADSCH_ANS adsch.bitc._ANS +__IO_EXTERN ADECHSTR adech; +#define ADECH adech.byte +#define ADECH_ANE4 adech.bit._ANE4 +#define ADECH_ANE3 adech.bit._ANE3 +#define ADECH_ANE2 adech.bit._ANE2 +#define ADECH_ANE1 adech.bit._ANE1 +#define ADECH_ANE0 adech.bit._ANE0 +#define ADECH_ANE adech.bitc._ANE +__IO_EXTERN TMRLR0STR tmrlr0; /* Reload Timer 0 */ +#define TMRLR0 tmrlr0.word +#define TMRLR0_D15 tmrlr0.bit._D15 +#define TMRLR0_D14 tmrlr0.bit._D14 +#define TMRLR0_D13 tmrlr0.bit._D13 +#define TMRLR0_D12 tmrlr0.bit._D12 +#define TMRLR0_D11 tmrlr0.bit._D11 +#define TMRLR0_D10 tmrlr0.bit._D10 +#define TMRLR0_D9 tmrlr0.bit._D9 +#define TMRLR0_D8 tmrlr0.bit._D8 +#define TMRLR0_D7 tmrlr0.bit._D7 +#define TMRLR0_D6 tmrlr0.bit._D6 +#define TMRLR0_D5 tmrlr0.bit._D5 +#define TMRLR0_D4 tmrlr0.bit._D4 +#define TMRLR0_D3 tmrlr0.bit._D3 +#define TMRLR0_D2 tmrlr0.bit._D2 +#define TMRLR0_D1 tmrlr0.bit._D1 +#define TMRLR0_D0 tmrlr0.bit._D0 +__IO_EXTERN TMR0STR tmr0; +#define TMR0 tmr0.word +#define TMR0_D15 tmr0.bit._D15 +#define TMR0_D14 tmr0.bit._D14 +#define TMR0_D13 tmr0.bit._D13 +#define TMR0_D12 tmr0.bit._D12 +#define TMR0_D11 tmr0.bit._D11 +#define TMR0_D10 tmr0.bit._D10 +#define TMR0_D9 tmr0.bit._D9 +#define TMR0_D8 tmr0.bit._D8 +#define TMR0_D7 tmr0.bit._D7 +#define TMR0_D6 tmr0.bit._D6 +#define TMR0_D5 tmr0.bit._D5 +#define TMR0_D4 tmr0.bit._D4 +#define TMR0_D3 tmr0.bit._D3 +#define TMR0_D2 tmr0.bit._D2 +#define TMR0_D1 tmr0.bit._D1 +#define TMR0_D0 tmr0.bit._D0 +__IO_EXTERN TMCSR0STR tmcsr0; +#define TMCSR0 tmcsr0.word +#define TMCSR0_CSL2 tmcsr0.bit._CSL2 +#define TMCSR0_CSL1 tmcsr0.bit._CSL1 +#define TMCSR0_CSL0 tmcsr0.bit._CSL0 +#define TMCSR0_MOD2 tmcsr0.bit._MOD2 +#define TMCSR0_MOD1 tmcsr0.bit._MOD1 +#define TMCSR0_MOD0 tmcsr0.bit._MOD0 +#define TMCSR0_OULT tmcsr0.bit._OULT +#define TMCSR0_RELD tmcsr0.bit._RELD +#define TMCSR0_INTE tmcsr0.bit._INTE +#define TMCSR0_UF tmcsr0.bit._UF +#define TMCSR0_CNTE tmcsr0.bit._CNTE +#define TMCSR0_TRG tmcsr0.bit._TRG +#define TMCSR0_CSL tmcsr0.bitc._CSL +#define TMCSR0_MOD tmcsr0.bitc._MOD +__IO_EXTERN TMCSRH0STR tmcsrh0; +#define TMCSRH0 tmcsrh0.byte +#define TMCSRH0_CSL2 tmcsrh0.bit._CSL2 +#define TMCSRH0_CSL1 tmcsrh0.bit._CSL1 +#define TMCSRH0_CSL0 tmcsrh0.bit._CSL0 +#define TMCSRH0_MOD2 tmcsrh0.bit._MOD2 +#define TMCSRH0_MOD1 tmcsrh0.bit._MOD1 +#define TMCSRH0_CSL tmcsrh0.bitc._CSL +__IO_EXTERN TMCSRL0STR tmcsrl0; +#define TMCSRL0 tmcsrl0.byte +#define TMCSRL0_MOD0 tmcsrl0.bit._MOD0 +#define TMCSRL0_OULT tmcsrl0.bit._OULT +#define TMCSRL0_RELD tmcsrl0.bit._RELD +#define TMCSRL0_INTE tmcsrl0.bit._INTE +#define TMCSRL0_UF tmcsrl0.bit._UF +#define TMCSRL0_CNTE tmcsrl0.bit._CNTE +#define TMCSRL0_TRG tmcsrl0.bit._TRG +__IO_EXTERN TMRLR1STR tmrlr1; /* Reload Timer 1 */ +#define TMRLR1 tmrlr1.word +#define TMRLR1_D15 tmrlr1.bit._D15 +#define TMRLR1_D14 tmrlr1.bit._D14 +#define TMRLR1_D13 tmrlr1.bit._D13 +#define TMRLR1_D12 tmrlr1.bit._D12 +#define TMRLR1_D11 tmrlr1.bit._D11 +#define TMRLR1_D10 tmrlr1.bit._D10 +#define TMRLR1_D9 tmrlr1.bit._D9 +#define TMRLR1_D8 tmrlr1.bit._D8 +#define TMRLR1_D7 tmrlr1.bit._D7 +#define TMRLR1_D6 tmrlr1.bit._D6 +#define TMRLR1_D5 tmrlr1.bit._D5 +#define TMRLR1_D4 tmrlr1.bit._D4 +#define TMRLR1_D3 tmrlr1.bit._D3 +#define TMRLR1_D2 tmrlr1.bit._D2 +#define TMRLR1_D1 tmrlr1.bit._D1 +#define TMRLR1_D0 tmrlr1.bit._D0 +__IO_EXTERN TMR1STR tmr1; +#define TMR1 tmr1.word +#define TMR1_D15 tmr1.bit._D15 +#define TMR1_D14 tmr1.bit._D14 +#define TMR1_D13 tmr1.bit._D13 +#define TMR1_D12 tmr1.bit._D12 +#define TMR1_D11 tmr1.bit._D11 +#define TMR1_D10 tmr1.bit._D10 +#define TMR1_D9 tmr1.bit._D9 +#define TMR1_D8 tmr1.bit._D8 +#define TMR1_D7 tmr1.bit._D7 +#define TMR1_D6 tmr1.bit._D6 +#define TMR1_D5 tmr1.bit._D5 +#define TMR1_D4 tmr1.bit._D4 +#define TMR1_D3 tmr1.bit._D3 +#define TMR1_D2 tmr1.bit._D2 +#define TMR1_D1 tmr1.bit._D1 +#define TMR1_D0 tmr1.bit._D0 +__IO_EXTERN TMCSR1STR tmcsr1; +#define TMCSR1 tmcsr1.word +#define TMCSR1_CSL2 tmcsr1.bit._CSL2 +#define TMCSR1_CSL1 tmcsr1.bit._CSL1 +#define TMCSR1_CSL0 tmcsr1.bit._CSL0 +#define TMCSR1_MOD2 tmcsr1.bit._MOD2 +#define TMCSR1_MOD1 tmcsr1.bit._MOD1 +#define TMCSR1_MOD0 tmcsr1.bit._MOD0 +#define TMCSR1_OULT tmcsr1.bit._OULT +#define TMCSR1_RELD tmcsr1.bit._RELD +#define TMCSR1_INTE tmcsr1.bit._INTE +#define TMCSR1_UF tmcsr1.bit._UF +#define TMCSR1_CNTE tmcsr1.bit._CNTE +#define TMCSR1_TRG tmcsr1.bit._TRG +#define TMCSR1_CSL tmcsr1.bitc._CSL +#define TMCSR1_MOD tmcsr1.bitc._MOD +__IO_EXTERN TMCSRH1STR tmcsrh1; +#define TMCSRH1 tmcsrh1.byte +#define TMCSRH1_CSL2 tmcsrh1.bit._CSL2 +#define TMCSRH1_CSL1 tmcsrh1.bit._CSL1 +#define TMCSRH1_CSL0 tmcsrh1.bit._CSL0 +#define TMCSRH1_MOD2 tmcsrh1.bit._MOD2 +#define TMCSRH1_MOD1 tmcsrh1.bit._MOD1 +#define TMCSRH1_CSL tmcsrh1.bitc._CSL +__IO_EXTERN TMCSRL1STR tmcsrl1; +#define TMCSRL1 tmcsrl1.byte +#define TMCSRL1_MOD0 tmcsrl1.bit._MOD0 +#define TMCSRL1_OULT tmcsrl1.bit._OULT +#define TMCSRL1_RELD tmcsrl1.bit._RELD +#define TMCSRL1_INTE tmcsrl1.bit._INTE +#define TMCSRL1_UF tmcsrl1.bit._UF +#define TMCSRL1_CNTE tmcsrl1.bit._CNTE +#define TMCSRL1_TRG tmcsrl1.bit._TRG +__IO_EXTERN TMRLR2STR tmrlr2; /* Reload Timer 2 */ +#define TMRLR2 tmrlr2.word +#define TMRLR2_D15 tmrlr2.bit._D15 +#define TMRLR2_D14 tmrlr2.bit._D14 +#define TMRLR2_D13 tmrlr2.bit._D13 +#define TMRLR2_D12 tmrlr2.bit._D12 +#define TMRLR2_D11 tmrlr2.bit._D11 +#define TMRLR2_D10 tmrlr2.bit._D10 +#define TMRLR2_D9 tmrlr2.bit._D9 +#define TMRLR2_D8 tmrlr2.bit._D8 +#define TMRLR2_D7 tmrlr2.bit._D7 +#define TMRLR2_D6 tmrlr2.bit._D6 +#define TMRLR2_D5 tmrlr2.bit._D5 +#define TMRLR2_D4 tmrlr2.bit._D4 +#define TMRLR2_D3 tmrlr2.bit._D3 +#define TMRLR2_D2 tmrlr2.bit._D2 +#define TMRLR2_D1 tmrlr2.bit._D1 +#define TMRLR2_D0 tmrlr2.bit._D0 +__IO_EXTERN TMR2STR tmr2; +#define TMR2 tmr2.word +#define TMR2_D15 tmr2.bit._D15 +#define TMR2_D14 tmr2.bit._D14 +#define TMR2_D13 tmr2.bit._D13 +#define TMR2_D12 tmr2.bit._D12 +#define TMR2_D11 tmr2.bit._D11 +#define TMR2_D10 tmr2.bit._D10 +#define TMR2_D9 tmr2.bit._D9 +#define TMR2_D8 tmr2.bit._D8 +#define TMR2_D7 tmr2.bit._D7 +#define TMR2_D6 tmr2.bit._D6 +#define TMR2_D5 tmr2.bit._D5 +#define TMR2_D4 tmr2.bit._D4 +#define TMR2_D3 tmr2.bit._D3 +#define TMR2_D2 tmr2.bit._D2 +#define TMR2_D1 tmr2.bit._D1 +#define TMR2_D0 tmr2.bit._D0 +__IO_EXTERN TMCSR2STR tmcsr2; +#define TMCSR2 tmcsr2.word +#define TMCSR2_CSL2 tmcsr2.bit._CSL2 +#define TMCSR2_CSL1 tmcsr2.bit._CSL1 +#define TMCSR2_CSL0 tmcsr2.bit._CSL0 +#define TMCSR2_MOD2 tmcsr2.bit._MOD2 +#define TMCSR2_MOD1 tmcsr2.bit._MOD1 +#define TMCSR2_MOD0 tmcsr2.bit._MOD0 +#define TMCSR2_OULT tmcsr2.bit._OULT +#define TMCSR2_RELD tmcsr2.bit._RELD +#define TMCSR2_INTE tmcsr2.bit._INTE +#define TMCSR2_UF tmcsr2.bit._UF +#define TMCSR2_CNTE tmcsr2.bit._CNTE +#define TMCSR2_TRG tmcsr2.bit._TRG +#define TMCSR2_CSL tmcsr2.bitc._CSL +#define TMCSR2_MOD tmcsr2.bitc._MOD +__IO_EXTERN TMCSRH2STR tmcsrh2; +#define TMCSRH2 tmcsrh2.byte +#define TMCSRH2_CSL2 tmcsrh2.bit._CSL2 +#define TMCSRH2_CSL1 tmcsrh2.bit._CSL1 +#define TMCSRH2_CSL0 tmcsrh2.bit._CSL0 +#define TMCSRH2_MOD2 tmcsrh2.bit._MOD2 +#define TMCSRH2_MOD1 tmcsrh2.bit._MOD1 +#define TMCSRH2_CSL tmcsrh2.bitc._CSL +__IO_EXTERN TMCSRL2STR tmcsrl2; +#define TMCSRL2 tmcsrl2.byte +#define TMCSRL2_MOD0 tmcsrl2.bit._MOD0 +#define TMCSRL2_OULT tmcsrl2.bit._OULT +#define TMCSRL2_RELD tmcsrl2.bit._RELD +#define TMCSRL2_INTE tmcsrl2.bit._INTE +#define TMCSRL2_UF tmcsrl2.bit._UF +#define TMCSRL2_CNTE tmcsrl2.bit._CNTE +#define TMCSRL2_TRG tmcsrl2.bit._TRG +__IO_EXTERN TMRLR3STR tmrlr3; /* Reload Timer 3 */ +#define TMRLR3 tmrlr3.word +#define TMRLR3_D15 tmrlr3.bit._D15 +#define TMRLR3_D14 tmrlr3.bit._D14 +#define TMRLR3_D13 tmrlr3.bit._D13 +#define TMRLR3_D12 tmrlr3.bit._D12 +#define TMRLR3_D11 tmrlr3.bit._D11 +#define TMRLR3_D10 tmrlr3.bit._D10 +#define TMRLR3_D9 tmrlr3.bit._D9 +#define TMRLR3_D8 tmrlr3.bit._D8 +#define TMRLR3_D7 tmrlr3.bit._D7 +#define TMRLR3_D6 tmrlr3.bit._D6 +#define TMRLR3_D5 tmrlr3.bit._D5 +#define TMRLR3_D4 tmrlr3.bit._D4 +#define TMRLR3_D3 tmrlr3.bit._D3 +#define TMRLR3_D2 tmrlr3.bit._D2 +#define TMRLR3_D1 tmrlr3.bit._D1 +#define TMRLR3_D0 tmrlr3.bit._D0 +__IO_EXTERN TMR3STR tmr3; +#define TMR3 tmr3.word +#define TMR3_D15 tmr3.bit._D15 +#define TMR3_D14 tmr3.bit._D14 +#define TMR3_D13 tmr3.bit._D13 +#define TMR3_D12 tmr3.bit._D12 +#define TMR3_D11 tmr3.bit._D11 +#define TMR3_D10 tmr3.bit._D10 +#define TMR3_D9 tmr3.bit._D9 +#define TMR3_D8 tmr3.bit._D8 +#define TMR3_D7 tmr3.bit._D7 +#define TMR3_D6 tmr3.bit._D6 +#define TMR3_D5 tmr3.bit._D5 +#define TMR3_D4 tmr3.bit._D4 +#define TMR3_D3 tmr3.bit._D3 +#define TMR3_D2 tmr3.bit._D2 +#define TMR3_D1 tmr3.bit._D1 +#define TMR3_D0 tmr3.bit._D0 +__IO_EXTERN TMCSR3STR tmcsr3; +#define TMCSR3 tmcsr3.word +#define TMCSR3_CSL2 tmcsr3.bit._CSL2 +#define TMCSR3_CSL1 tmcsr3.bit._CSL1 +#define TMCSR3_CSL0 tmcsr3.bit._CSL0 +#define TMCSR3_MOD2 tmcsr3.bit._MOD2 +#define TMCSR3_MOD1 tmcsr3.bit._MOD1 +#define TMCSR3_MOD0 tmcsr3.bit._MOD0 +#define TMCSR3_OULT tmcsr3.bit._OULT +#define TMCSR3_RELD tmcsr3.bit._RELD +#define TMCSR3_INTE tmcsr3.bit._INTE +#define TMCSR3_UF tmcsr3.bit._UF +#define TMCSR3_CNTE tmcsr3.bit._CNTE +#define TMCSR3_TRG tmcsr3.bit._TRG +#define TMCSR3_CSL tmcsr3.bitc._CSL +#define TMCSR3_MOD tmcsr3.bitc._MOD +__IO_EXTERN TMCSRH3STR tmcsrh3; +#define TMCSRH3 tmcsrh3.byte +#define TMCSRH3_CSL2 tmcsrh3.bit._CSL2 +#define TMCSRH3_CSL1 tmcsrh3.bit._CSL1 +#define TMCSRH3_CSL0 tmcsrh3.bit._CSL0 +#define TMCSRH3_MOD2 tmcsrh3.bit._MOD2 +#define TMCSRH3_MOD1 tmcsrh3.bit._MOD1 +#define TMCSRH3_CSL tmcsrh3.bitc._CSL +__IO_EXTERN TMCSRL3STR tmcsrl3; +#define TMCSRL3 tmcsrl3.byte +#define TMCSRL3_MOD0 tmcsrl3.bit._MOD0 +#define TMCSRL3_OULT tmcsrl3.bit._OULT +#define TMCSRL3_RELD tmcsrl3.bit._RELD +#define TMCSRL3_INTE tmcsrl3.bit._INTE +#define TMCSRL3_UF tmcsrl3.bit._UF +#define TMCSRL3_CNTE tmcsrl3.bit._CNTE +#define TMCSRL3_TRG tmcsrl3.bit._TRG +__IO_EXTERN TMRLR4STR tmrlr4; /* Reload Timer 4 */ +#define TMRLR4 tmrlr4.word +#define TMRLR4_D15 tmrlr4.bit._D15 +#define TMRLR4_D14 tmrlr4.bit._D14 +#define TMRLR4_D13 tmrlr4.bit._D13 +#define TMRLR4_D12 tmrlr4.bit._D12 +#define TMRLR4_D11 tmrlr4.bit._D11 +#define TMRLR4_D10 tmrlr4.bit._D10 +#define TMRLR4_D9 tmrlr4.bit._D9 +#define TMRLR4_D8 tmrlr4.bit._D8 +#define TMRLR4_D7 tmrlr4.bit._D7 +#define TMRLR4_D6 tmrlr4.bit._D6 +#define TMRLR4_D5 tmrlr4.bit._D5 +#define TMRLR4_D4 tmrlr4.bit._D4 +#define TMRLR4_D3 tmrlr4.bit._D3 +#define TMRLR4_D2 tmrlr4.bit._D2 +#define TMRLR4_D1 tmrlr4.bit._D1 +#define TMRLR4_D0 tmrlr4.bit._D0 +__IO_EXTERN TMR4STR tmr4; +#define TMR4 tmr4.word +#define TMR4_D15 tmr4.bit._D15 +#define TMR4_D14 tmr4.bit._D14 +#define TMR4_D13 tmr4.bit._D13 +#define TMR4_D12 tmr4.bit._D12 +#define TMR4_D11 tmr4.bit._D11 +#define TMR4_D10 tmr4.bit._D10 +#define TMR4_D9 tmr4.bit._D9 +#define TMR4_D8 tmr4.bit._D8 +#define TMR4_D7 tmr4.bit._D7 +#define TMR4_D6 tmr4.bit._D6 +#define TMR4_D5 tmr4.bit._D5 +#define TMR4_D4 tmr4.bit._D4 +#define TMR4_D3 tmr4.bit._D3 +#define TMR4_D2 tmr4.bit._D2 +#define TMR4_D1 tmr4.bit._D1 +#define TMR4_D0 tmr4.bit._D0 +__IO_EXTERN TMCSR4STR tmcsr4; +#define TMCSR4 tmcsr4.word +#define TMCSR4_CSL2 tmcsr4.bit._CSL2 +#define TMCSR4_CSL1 tmcsr4.bit._CSL1 +#define TMCSR4_CSL0 tmcsr4.bit._CSL0 +#define TMCSR4_MOD2 tmcsr4.bit._MOD2 +#define TMCSR4_MOD1 tmcsr4.bit._MOD1 +#define TMCSR4_MOD0 tmcsr4.bit._MOD0 +#define TMCSR4_OULT tmcsr4.bit._OULT +#define TMCSR4_RELD tmcsr4.bit._RELD +#define TMCSR4_INTE tmcsr4.bit._INTE +#define TMCSR4_UF tmcsr4.bit._UF +#define TMCSR4_CNTE tmcsr4.bit._CNTE +#define TMCSR4_TRG tmcsr4.bit._TRG +#define TMCSR4_CSL tmcsr4.bitc._CSL +#define TMCSR4_MOD tmcsr4.bitc._MOD +__IO_EXTERN TMCSRH4STR tmcsrh4; +#define TMCSRH4 tmcsrh4.byte +#define TMCSRH4_CSL2 tmcsrh4.bit._CSL2 +#define TMCSRH4_CSL1 tmcsrh4.bit._CSL1 +#define TMCSRH4_CSL0 tmcsrh4.bit._CSL0 +#define TMCSRH4_MOD2 tmcsrh4.bit._MOD2 +#define TMCSRH4_MOD1 tmcsrh4.bit._MOD1 +#define TMCSRH4_CSL tmcsrh4.bitc._CSL +__IO_EXTERN TMCSRL4STR tmcsrl4; +#define TMCSRL4 tmcsrl4.byte +#define TMCSRL4_MOD0 tmcsrl4.bit._MOD0 +#define TMCSRL4_OULT tmcsrl4.bit._OULT +#define TMCSRL4_RELD tmcsrl4.bit._RELD +#define TMCSRL4_INTE tmcsrl4.bit._INTE +#define TMCSRL4_UF tmcsrl4.bit._UF +#define TMCSRL4_CNTE tmcsrl4.bit._CNTE +#define TMCSRL4_TRG tmcsrl4.bit._TRG +__IO_EXTERN TMRLR5STR tmrlr5; /* Reload Timer 5 */ +#define TMRLR5 tmrlr5.word +#define TMRLR5_D15 tmrlr5.bit._D15 +#define TMRLR5_D14 tmrlr5.bit._D14 +#define TMRLR5_D13 tmrlr5.bit._D13 +#define TMRLR5_D12 tmrlr5.bit._D12 +#define TMRLR5_D11 tmrlr5.bit._D11 +#define TMRLR5_D10 tmrlr5.bit._D10 +#define TMRLR5_D9 tmrlr5.bit._D9 +#define TMRLR5_D8 tmrlr5.bit._D8 +#define TMRLR5_D7 tmrlr5.bit._D7 +#define TMRLR5_D6 tmrlr5.bit._D6 +#define TMRLR5_D5 tmrlr5.bit._D5 +#define TMRLR5_D4 tmrlr5.bit._D4 +#define TMRLR5_D3 tmrlr5.bit._D3 +#define TMRLR5_D2 tmrlr5.bit._D2 +#define TMRLR5_D1 tmrlr5.bit._D1 +#define TMRLR5_D0 tmrlr5.bit._D0 +__IO_EXTERN TMR5STR tmr5; +#define TMR5 tmr5.word +#define TMR5_D15 tmr5.bit._D15 +#define TMR5_D14 tmr5.bit._D14 +#define TMR5_D13 tmr5.bit._D13 +#define TMR5_D12 tmr5.bit._D12 +#define TMR5_D11 tmr5.bit._D11 +#define TMR5_D10 tmr5.bit._D10 +#define TMR5_D9 tmr5.bit._D9 +#define TMR5_D8 tmr5.bit._D8 +#define TMR5_D7 tmr5.bit._D7 +#define TMR5_D6 tmr5.bit._D6 +#define TMR5_D5 tmr5.bit._D5 +#define TMR5_D4 tmr5.bit._D4 +#define TMR5_D3 tmr5.bit._D3 +#define TMR5_D2 tmr5.bit._D2 +#define TMR5_D1 tmr5.bit._D1 +#define TMR5_D0 tmr5.bit._D0 +__IO_EXTERN TMCSR5STR tmcsr5; +#define TMCSR5 tmcsr5.word +#define TMCSR5_CSL2 tmcsr5.bit._CSL2 +#define TMCSR5_CSL1 tmcsr5.bit._CSL1 +#define TMCSR5_CSL0 tmcsr5.bit._CSL0 +#define TMCSR5_MOD2 tmcsr5.bit._MOD2 +#define TMCSR5_MOD1 tmcsr5.bit._MOD1 +#define TMCSR5_MOD0 tmcsr5.bit._MOD0 +#define TMCSR5_OULT tmcsr5.bit._OULT +#define TMCSR5_RELD tmcsr5.bit._RELD +#define TMCSR5_INTE tmcsr5.bit._INTE +#define TMCSR5_UF tmcsr5.bit._UF +#define TMCSR5_CNTE tmcsr5.bit._CNTE +#define TMCSR5_TRG tmcsr5.bit._TRG +#define TMCSR5_CSL tmcsr5.bitc._CSL +#define TMCSR5_MOD tmcsr5.bitc._MOD +__IO_EXTERN TMCSRH5STR tmcsrh5; +#define TMCSRH5 tmcsrh5.byte +#define TMCSRH5_CSL2 tmcsrh5.bit._CSL2 +#define TMCSRH5_CSL1 tmcsrh5.bit._CSL1 +#define TMCSRH5_CSL0 tmcsrh5.bit._CSL0 +#define TMCSRH5_MOD2 tmcsrh5.bit._MOD2 +#define TMCSRH5_MOD1 tmcsrh5.bit._MOD1 +#define TMCSRH5_CSL tmcsrh5.bitc._CSL +__IO_EXTERN TMCSRL5STR tmcsrl5; +#define TMCSRL5 tmcsrl5.byte +#define TMCSRL5_MOD0 tmcsrl5.bit._MOD0 +#define TMCSRL5_OULT tmcsrl5.bit._OULT +#define TMCSRL5_RELD tmcsrl5.bit._RELD +#define TMCSRL5_INTE tmcsrl5.bit._INTE +#define TMCSRL5_UF tmcsrl5.bit._UF +#define TMCSRL5_CNTE tmcsrl5.bit._CNTE +#define TMCSRL5_TRG tmcsrl5.bit._TRG +__IO_EXTERN TMRLR6STR tmrlr6; /* Reload Timer 6 */ +#define TMRLR6 tmrlr6.word +#define TMRLR6_D15 tmrlr6.bit._D15 +#define TMRLR6_D14 tmrlr6.bit._D14 +#define TMRLR6_D13 tmrlr6.bit._D13 +#define TMRLR6_D12 tmrlr6.bit._D12 +#define TMRLR6_D11 tmrlr6.bit._D11 +#define TMRLR6_D10 tmrlr6.bit._D10 +#define TMRLR6_D9 tmrlr6.bit._D9 +#define TMRLR6_D8 tmrlr6.bit._D8 +#define TMRLR6_D7 tmrlr6.bit._D7 +#define TMRLR6_D6 tmrlr6.bit._D6 +#define TMRLR6_D5 tmrlr6.bit._D5 +#define TMRLR6_D4 tmrlr6.bit._D4 +#define TMRLR6_D3 tmrlr6.bit._D3 +#define TMRLR6_D2 tmrlr6.bit._D2 +#define TMRLR6_D1 tmrlr6.bit._D1 +#define TMRLR6_D0 tmrlr6.bit._D0 +__IO_EXTERN TMR6STR tmr6; +#define TMR6 tmr6.word +#define TMR6_D15 tmr6.bit._D15 +#define TMR6_D14 tmr6.bit._D14 +#define TMR6_D13 tmr6.bit._D13 +#define TMR6_D12 tmr6.bit._D12 +#define TMR6_D11 tmr6.bit._D11 +#define TMR6_D10 tmr6.bit._D10 +#define TMR6_D9 tmr6.bit._D9 +#define TMR6_D8 tmr6.bit._D8 +#define TMR6_D7 tmr6.bit._D7 +#define TMR6_D6 tmr6.bit._D6 +#define TMR6_D5 tmr6.bit._D5 +#define TMR6_D4 tmr6.bit._D4 +#define TMR6_D3 tmr6.bit._D3 +#define TMR6_D2 tmr6.bit._D2 +#define TMR6_D1 tmr6.bit._D1 +#define TMR6_D0 tmr6.bit._D0 +__IO_EXTERN TMCSR6STR tmcsr6; +#define TMCSR6 tmcsr6.word +#define TMCSR6_CSL2 tmcsr6.bit._CSL2 +#define TMCSR6_CSL1 tmcsr6.bit._CSL1 +#define TMCSR6_CSL0 tmcsr6.bit._CSL0 +#define TMCSR6_MOD2 tmcsr6.bit._MOD2 +#define TMCSR6_MOD1 tmcsr6.bit._MOD1 +#define TMCSR6_MOD0 tmcsr6.bit._MOD0 +#define TMCSR6_OULT tmcsr6.bit._OULT +#define TMCSR6_RELD tmcsr6.bit._RELD +#define TMCSR6_INTE tmcsr6.bit._INTE +#define TMCSR6_UF tmcsr6.bit._UF +#define TMCSR6_CNTE tmcsr6.bit._CNTE +#define TMCSR6_TRG tmcsr6.bit._TRG +#define TMCSR6_CSL tmcsr6.bitc._CSL +#define TMCSR6_MOD tmcsr6.bitc._MOD +__IO_EXTERN TMCSRH6STR tmcsrh6; +#define TMCSRH6 tmcsrh6.byte +#define TMCSRH6_CSL2 tmcsrh6.bit._CSL2 +#define TMCSRH6_CSL1 tmcsrh6.bit._CSL1 +#define TMCSRH6_CSL0 tmcsrh6.bit._CSL0 +#define TMCSRH6_MOD2 tmcsrh6.bit._MOD2 +#define TMCSRH6_MOD1 tmcsrh6.bit._MOD1 +#define TMCSRH6_CSL tmcsrh6.bitc._CSL +__IO_EXTERN TMCSRL6STR tmcsrl6; +#define TMCSRL6 tmcsrl6.byte +#define TMCSRL6_MOD0 tmcsrl6.bit._MOD0 +#define TMCSRL6_OULT tmcsrl6.bit._OULT +#define TMCSRL6_RELD tmcsrl6.bit._RELD +#define TMCSRL6_INTE tmcsrl6.bit._INTE +#define TMCSRL6_UF tmcsrl6.bit._UF +#define TMCSRL6_CNTE tmcsrl6.bit._CNTE +#define TMCSRL6_TRG tmcsrl6.bit._TRG +__IO_EXTERN TMRLR7STR tmrlr7; /* Reload Timer 7 */ +#define TMRLR7 tmrlr7.word +#define TMRLR7_D15 tmrlr7.bit._D15 +#define TMRLR7_D14 tmrlr7.bit._D14 +#define TMRLR7_D13 tmrlr7.bit._D13 +#define TMRLR7_D12 tmrlr7.bit._D12 +#define TMRLR7_D11 tmrlr7.bit._D11 +#define TMRLR7_D10 tmrlr7.bit._D10 +#define TMRLR7_D9 tmrlr7.bit._D9 +#define TMRLR7_D8 tmrlr7.bit._D8 +#define TMRLR7_D7 tmrlr7.bit._D7 +#define TMRLR7_D6 tmrlr7.bit._D6 +#define TMRLR7_D5 tmrlr7.bit._D5 +#define TMRLR7_D4 tmrlr7.bit._D4 +#define TMRLR7_D3 tmrlr7.bit._D3 +#define TMRLR7_D2 tmrlr7.bit._D2 +#define TMRLR7_D1 tmrlr7.bit._D1 +#define TMRLR7_D0 tmrlr7.bit._D0 +__IO_EXTERN TMR7STR tmr7; +#define TMR7 tmr7.word +#define TMR7_D15 tmr7.bit._D15 +#define TMR7_D14 tmr7.bit._D14 +#define TMR7_D13 tmr7.bit._D13 +#define TMR7_D12 tmr7.bit._D12 +#define TMR7_D11 tmr7.bit._D11 +#define TMR7_D10 tmr7.bit._D10 +#define TMR7_D9 tmr7.bit._D9 +#define TMR7_D8 tmr7.bit._D8 +#define TMR7_D7 tmr7.bit._D7 +#define TMR7_D6 tmr7.bit._D6 +#define TMR7_D5 tmr7.bit._D5 +#define TMR7_D4 tmr7.bit._D4 +#define TMR7_D3 tmr7.bit._D3 +#define TMR7_D2 tmr7.bit._D2 +#define TMR7_D1 tmr7.bit._D1 +#define TMR7_D0 tmr7.bit._D0 +__IO_EXTERN TMCSR7STR tmcsr7; +#define TMCSR7 tmcsr7.word +#define TMCSR7_CSL2 tmcsr7.bit._CSL2 +#define TMCSR7_CSL1 tmcsr7.bit._CSL1 +#define TMCSR7_CSL0 tmcsr7.bit._CSL0 +#define TMCSR7_MOD2 tmcsr7.bit._MOD2 +#define TMCSR7_MOD1 tmcsr7.bit._MOD1 +#define TMCSR7_MOD0 tmcsr7.bit._MOD0 +#define TMCSR7_OULT tmcsr7.bit._OULT +#define TMCSR7_RELD tmcsr7.bit._RELD +#define TMCSR7_INTE tmcsr7.bit._INTE +#define TMCSR7_UF tmcsr7.bit._UF +#define TMCSR7_CNTE tmcsr7.bit._CNTE +#define TMCSR7_TRG tmcsr7.bit._TRG +#define TMCSR7_CSL tmcsr7.bitc._CSL +#define TMCSR7_MOD tmcsr7.bitc._MOD +__IO_EXTERN TMCSRH7STR tmcsrh7; +#define TMCSRH7 tmcsrh7.byte +#define TMCSRH7_CSL2 tmcsrh7.bit._CSL2 +#define TMCSRH7_CSL1 tmcsrh7.bit._CSL1 +#define TMCSRH7_CSL0 tmcsrh7.bit._CSL0 +#define TMCSRH7_MOD2 tmcsrh7.bit._MOD2 +#define TMCSRH7_MOD1 tmcsrh7.bit._MOD1 +#define TMCSRH7_CSL tmcsrh7.bitc._CSL +__IO_EXTERN TMCSRL7STR tmcsrl7; +#define TMCSRL7 tmcsrl7.byte +#define TMCSRL7_MOD0 tmcsrl7.bit._MOD0 +#define TMCSRL7_OULT tmcsrl7.bit._OULT +#define TMCSRL7_RELD tmcsrl7.bit._RELD +#define TMCSRL7_INTE tmcsrl7.bit._INTE +#define TMCSRL7_UF tmcsrl7.bit._UF +#define TMCSRL7_CNTE tmcsrl7.bit._CNTE +#define TMCSRL7_TRG tmcsrl7.bit._TRG +__IO_EXTERN TCDT0STR tcdt0; /* Free Running Timer0 */ +#define TCDT0 tcdt0.word +#define TCDT0_T15 tcdt0.bit._T15 +#define TCDT0_T14 tcdt0.bit._T14 +#define TCDT0_T13 tcdt0.bit._T13 +#define TCDT0_T12 tcdt0.bit._T12 +#define TCDT0_T11 tcdt0.bit._T11 +#define TCDT0_T10 tcdt0.bit._T10 +#define TCDT0_T9 tcdt0.bit._T9 +#define TCDT0_T8 tcdt0.bit._T8 +#define TCDT0_T7 tcdt0.bit._T7 +#define TCDT0_T6 tcdt0.bit._T6 +#define TCDT0_T5 tcdt0.bit._T5 +#define TCDT0_T4 tcdt0.bit._T4 +#define TCDT0_T3 tcdt0.bit._T3 +#define TCDT0_T2 tcdt0.bit._T2 +#define TCDT0_T1 tcdt0.bit._T1 +#define TCDT0_T0 tcdt0.bit._T0 +__IO_EXTERN TCCS0STR tccs0; +#define TCCS0 tccs0.byte +#define TCCS0_ECLK tccs0.bit._ECLK +#define TCCS0_IVF tccs0.bit._IVF +#define TCCS0_IVFE tccs0.bit._IVFE +#define TCCS0_STOP tccs0.bit._STOP +#define TCCS0_MODE tccs0.bit._MODE +#define TCCS0_CLR tccs0.bit._CLR +#define TCCS0_CLK1 tccs0.bit._CLK1 +#define TCCS0_CLK0 tccs0.bit._CLK0 +#define TCCS0_CLK tccs0.bitc._CLK +__IO_EXTERN TCDT1STR tcdt1; /* Free Running Timer1 */ +#define TCDT1 tcdt1.word +#define TCDT1_T15 tcdt1.bit._T15 +#define TCDT1_T14 tcdt1.bit._T14 +#define TCDT1_T13 tcdt1.bit._T13 +#define TCDT1_T12 tcdt1.bit._T12 +#define TCDT1_T11 tcdt1.bit._T11 +#define TCDT1_T10 tcdt1.bit._T10 +#define TCDT1_T9 tcdt1.bit._T9 +#define TCDT1_T8 tcdt1.bit._T8 +#define TCDT1_T7 tcdt1.bit._T7 +#define TCDT1_T6 tcdt1.bit._T6 +#define TCDT1_T5 tcdt1.bit._T5 +#define TCDT1_T4 tcdt1.bit._T4 +#define TCDT1_T3 tcdt1.bit._T3 +#define TCDT1_T2 tcdt1.bit._T2 +#define TCDT1_T1 tcdt1.bit._T1 +#define TCDT1_T0 tcdt1.bit._T0 +__IO_EXTERN TCCS1STR tccs1; +#define TCCS1 tccs1.byte +#define TCCS1_ECLK tccs1.bit._ECLK +#define TCCS1_IVF tccs1.bit._IVF +#define TCCS1_IVFE tccs1.bit._IVFE +#define TCCS1_STOP tccs1.bit._STOP +#define TCCS1_MODE tccs1.bit._MODE +#define TCCS1_CLR tccs1.bit._CLR +#define TCCS1_CLK1 tccs1.bit._CLK1 +#define TCCS1_CLK0 tccs1.bit._CLK0 +#define TCCS1_CLK tccs1.bitc._CLK +__IO_EXTERN TCDT2STR tcdt2; /* Free Running Timer2 */ +#define TCDT2 tcdt2.word +#define TCDT2_T15 tcdt2.bit._T15 +#define TCDT2_T14 tcdt2.bit._T14 +#define TCDT2_T13 tcdt2.bit._T13 +#define TCDT2_T12 tcdt2.bit._T12 +#define TCDT2_T11 tcdt2.bit._T11 +#define TCDT2_T10 tcdt2.bit._T10 +#define TCDT2_T9 tcdt2.bit._T9 +#define TCDT2_T8 tcdt2.bit._T8 +#define TCDT2_T7 tcdt2.bit._T7 +#define TCDT2_T6 tcdt2.bit._T6 +#define TCDT2_T5 tcdt2.bit._T5 +#define TCDT2_T4 tcdt2.bit._T4 +#define TCDT2_T3 tcdt2.bit._T3 +#define TCDT2_T2 tcdt2.bit._T2 +#define TCDT2_T1 tcdt2.bit._T1 +#define TCDT2_T0 tcdt2.bit._T0 +__IO_EXTERN TCCS2STR tccs2; +#define TCCS2 tccs2.byte +#define TCCS2_ECLK tccs2.bit._ECLK +#define TCCS2_IVF tccs2.bit._IVF +#define TCCS2_IVFE tccs2.bit._IVFE +#define TCCS2_STOP tccs2.bit._STOP +#define TCCS2_MODE tccs2.bit._MODE +#define TCCS2_CLR tccs2.bit._CLR +#define TCCS2_CLK1 tccs2.bit._CLK1 +#define TCCS2_CLK0 tccs2.bit._CLK0 +#define TCCS2_CLK tccs2.bitc._CLK +__IO_EXTERN TCDT3STR tcdt3; /* Free Running Timer3 */ +#define TCDT3 tcdt3.word +#define TCDT3_T15 tcdt3.bit._T15 +#define TCDT3_T14 tcdt3.bit._T14 +#define TCDT3_T13 tcdt3.bit._T13 +#define TCDT3_T12 tcdt3.bit._T12 +#define TCDT3_T11 tcdt3.bit._T11 +#define TCDT3_T10 tcdt3.bit._T10 +#define TCDT3_T9 tcdt3.bit._T9 +#define TCDT3_T8 tcdt3.bit._T8 +#define TCDT3_T7 tcdt3.bit._T7 +#define TCDT3_T6 tcdt3.bit._T6 +#define TCDT3_T5 tcdt3.bit._T5 +#define TCDT3_T4 tcdt3.bit._T4 +#define TCDT3_T3 tcdt3.bit._T3 +#define TCDT3_T2 tcdt3.bit._T2 +#define TCDT3_T1 tcdt3.bit._T1 +#define TCDT3_T0 tcdt3.bit._T0 +__IO_EXTERN TCCS3STR tccs3; +#define TCCS3 tccs3.byte +#define TCCS3_ECLK tccs3.bit._ECLK +#define TCCS3_IVF tccs3.bit._IVF +#define TCCS3_IVFE tccs3.bit._IVFE +#define TCCS3_STOP tccs3.bit._STOP +#define TCCS3_MODE tccs3.bit._MODE +#define TCCS3_CLR tccs3.bit._CLR +#define TCCS3_CLK1 tccs3.bit._CLK1 +#define TCCS3_CLK0 tccs3.bit._CLK0 +#define TCCS3_CLK tccs3.bitc._CLK +__IO_EXTERN DMACA0STR dmaca0; /* DMAC */ +#define DMACA0 dmaca0.lword +#define DMACA0_DENB dmaca0.bit._DENB +#define DMACA0_PAUS dmaca0.bit._PAUS +#define DMACA0_STRG dmaca0.bit._STRG +#define DMACA0_IS4 dmaca0.bit._IS4 +#define DMACA0_IS3 dmaca0.bit._IS3 +#define DMACA0_IS2 dmaca0.bit._IS2 +#define DMACA0_IS1 dmaca0.bit._IS1 +#define DMACA0_IS0 dmaca0.bit._IS0 +#define DMACA0_EIS3 dmaca0.bit._EIS3 +#define DMACA0_EIS2 dmaca0.bit._EIS2 +#define DMACA0_EIS1 dmaca0.bit._EIS1 +#define DMACA0_EIS0 dmaca0.bit._EIS0 +#define DMACA0_BLK3 dmaca0.bit._BLK3 +#define DMACA0_BLK2 dmaca0.bit._BLK2 +#define DMACA0_BLK1 dmaca0.bit._BLK1 +#define DMACA0_BLK0 dmaca0.bit._BLK0 +#define DMACA0_DTCF dmaca0.bit._DTCF +#define DMACA0_DTCE dmaca0.bit._DTCE +#define DMACA0_DTCD dmaca0.bit._DTCD +#define DMACA0_DTCC dmaca0.bit._DTCC +#define DMACA0_DTCB dmaca0.bit._DTCB +#define DMACA0_DTCA dmaca0.bit._DTCA +#define DMACA0_DTC9 dmaca0.bit._DTC9 +#define DMACA0_DTC8 dmaca0.bit._DTC8 +#define DMACA0_DTC7 dmaca0.bit._DTC7 +#define DMACA0_DTC6 dmaca0.bit._DTC6 +#define DMACA0_DTC5 dmaca0.bit._DTC5 +#define DMACA0_DTC4 dmaca0.bit._DTC4 +#define DMACA0_DTC3 dmaca0.bit._DTC3 +#define DMACA0_DTC2 dmaca0.bit._DTC2 +#define DMACA0_DTC1 dmaca0.bit._DTC1 +#define DMACA0_DTC0 dmaca0.bit._DTC0 +#define DMACA0_IS dmaca0.bitc._IS +#define DMACA0_EIS dmaca0.bitc._EIS +#define DMACA0_BLK dmaca0.bitc._BLK +#define DMACA0_DTC dmaca0.bitc._DTC +__IO_EXTERN DMACB0STR dmacb0; +#define DMACB0 dmacb0.lword +#define DMACB0_TYPE1 dmacb0.bit._TYPE1 +#define DMACB0_TYPE0 dmacb0.bit._TYPE0 +#define DMACB0_MOD1 dmacb0.bit._MOD1 +#define DMACB0_MOD0 dmacb0.bit._MOD0 +#define DMACB0_WS1 dmacb0.bit._WS1 +#define DMACB0_WS0 dmacb0.bit._WS0 +#define DMACB0_SADM dmacb0.bit._SADM +#define DMACB0_DADM dmacb0.bit._DADM +#define DMACB0_DTCR dmacb0.bit._DTCR +#define DMACB0_SADR dmacb0.bit._SADR +#define DMACB0_DADR dmacb0.bit._DADR +#define DMACB0_ERIE dmacb0.bit._ERIE +#define DMACB0_EDIE dmacb0.bit._EDIE +#define DMACB0_DSS2 dmacb0.bit._DSS2 +#define DMACB0_DSS1 dmacb0.bit._DSS1 +#define DMACB0_DSS0 dmacb0.bit._DSS0 +#define DMACB0_SASZ7 dmacb0.bit._SASZ7 +#define DMACB0_SASZ6 dmacb0.bit._SASZ6 +#define DMACB0_SASZ5 dmacb0.bit._SASZ5 +#define DMACB0_SASZ4 dmacb0.bit._SASZ4 +#define DMACB0_SASZ3 dmacb0.bit._SASZ3 +#define DMACB0_SASZ2 dmacb0.bit._SASZ2 +#define DMACB0_SASZ1 dmacb0.bit._SASZ1 +#define DMACB0_SASZ0 dmacb0.bit._SASZ0 +#define DMACB0_DASZ7 dmacb0.bit._DASZ7 +#define DMACB0_DASZ6 dmacb0.bit._DASZ6 +#define DMACB0_DASZ5 dmacb0.bit._DASZ5 +#define DMACB0_DASZ4 dmacb0.bit._DASZ4 +#define DMACB0_DASZ3 dmacb0.bit._DASZ3 +#define DMACB0_DASZ2 dmacb0.bit._DASZ2 +#define DMACB0_DASZ1 dmacb0.bit._DASZ1 +#define DMACB0_DASZ0 dmacb0.bit._DASZ0 +#define DMACB0_TYPE dmacb0.bitc._TYPE +#define DMACB0_MOD dmacb0.bitc._MOD +#define DMACB0_WS dmacb0.bitc._WS +#define DMACB0_DSS dmacb0.bitc._DSS +#define DMACB0_SASZ dmacb0.bitc._SASZ +#define DMACB0_DASZ dmacb0.bitc._DASZ +__IO_EXTERN DMACA1STR dmaca1; +#define DMACA1 dmaca1.lword +#define DMACA1_DENB dmaca1.bit._DENB +#define DMACA1_PAUS dmaca1.bit._PAUS +#define DMACA1_STRG dmaca1.bit._STRG +#define DMACA1_IS4 dmaca1.bit._IS4 +#define DMACA1_IS3 dmaca1.bit._IS3 +#define DMACA1_IS2 dmaca1.bit._IS2 +#define DMACA1_IS1 dmaca1.bit._IS1 +#define DMACA1_IS0 dmaca1.bit._IS0 +#define DMACA1_EIS3 dmaca1.bit._EIS3 +#define DMACA1_EIS2 dmaca1.bit._EIS2 +#define DMACA1_EIS1 dmaca1.bit._EIS1 +#define DMACA1_EIS0 dmaca1.bit._EIS0 +#define DMACA1_BLK3 dmaca1.bit._BLK3 +#define DMACA1_BLK2 dmaca1.bit._BLK2 +#define DMACA1_BLK1 dmaca1.bit._BLK1 +#define DMACA1_BLK0 dmaca1.bit._BLK0 +#define DMACA1_DTCF dmaca1.bit._DTCF +#define DMACA1_DTCE dmaca1.bit._DTCE +#define DMACA1_DTCD dmaca1.bit._DTCD +#define DMACA1_DTCC dmaca1.bit._DTCC +#define DMACA1_DTCB dmaca1.bit._DTCB +#define DMACA1_DTCA dmaca1.bit._DTCA +#define DMACA1_DTC9 dmaca1.bit._DTC9 +#define DMACA1_DTC8 dmaca1.bit._DTC8 +#define DMACA1_DTC7 dmaca1.bit._DTC7 +#define DMACA1_DTC6 dmaca1.bit._DTC6 +#define DMACA1_DTC5 dmaca1.bit._DTC5 +#define DMACA1_DTC4 dmaca1.bit._DTC4 +#define DMACA1_DTC3 dmaca1.bit._DTC3 +#define DMACA1_DTC2 dmaca1.bit._DTC2 +#define DMACA1_DTC1 dmaca1.bit._DTC1 +#define DMACA1_DTC0 dmaca1.bit._DTC0 +#define DMACA1_IS dmaca1.bitc._IS +#define DMACA1_EIS dmaca1.bitc._EIS +#define DMACA1_BLK dmaca1.bitc._BLK +#define DMACA1_DTC dmaca1.bitc._DTC +__IO_EXTERN DMACB1STR dmacb1; +#define DMACB1 dmacb1.lword +#define DMACB1_TYPE1 dmacb1.bit._TYPE1 +#define DMACB1_TYPE0 dmacb1.bit._TYPE0 +#define DMACB1_MOD1 dmacb1.bit._MOD1 +#define DMACB1_MOD0 dmacb1.bit._MOD0 +#define DMACB1_WS1 dmacb1.bit._WS1 +#define DMACB1_WS0 dmacb1.bit._WS0 +#define DMACB1_SADM dmacb1.bit._SADM +#define DMACB1_DADM dmacb1.bit._DADM +#define DMACB1_DTCR dmacb1.bit._DTCR +#define DMACB1_SADR dmacb1.bit._SADR +#define DMACB1_DADR dmacb1.bit._DADR +#define DMACB1_ERIE dmacb1.bit._ERIE +#define DMACB1_EDIE dmacb1.bit._EDIE +#define DMACB1_DSS2 dmacb1.bit._DSS2 +#define DMACB1_DSS1 dmacb1.bit._DSS1 +#define DMACB1_DSS0 dmacb1.bit._DSS0 +#define DMACB1_SASZ7 dmacb1.bit._SASZ7 +#define DMACB1_SASZ6 dmacb1.bit._SASZ6 +#define DMACB1_SASZ5 dmacb1.bit._SASZ5 +#define DMACB1_SASZ4 dmacb1.bit._SASZ4 +#define DMACB1_SASZ3 dmacb1.bit._SASZ3 +#define DMACB1_SASZ2 dmacb1.bit._SASZ2 +#define DMACB1_SASZ1 dmacb1.bit._SASZ1 +#define DMACB1_SASZ0 dmacb1.bit._SASZ0 +#define DMACB1_DASZ7 dmacb1.bit._DASZ7 +#define DMACB1_DASZ6 dmacb1.bit._DASZ6 +#define DMACB1_DASZ5 dmacb1.bit._DASZ5 +#define DMACB1_DASZ4 dmacb1.bit._DASZ4 +#define DMACB1_DASZ3 dmacb1.bit._DASZ3 +#define DMACB1_DASZ2 dmacb1.bit._DASZ2 +#define DMACB1_DASZ1 dmacb1.bit._DASZ1 +#define DMACB1_DASZ0 dmacb1.bit._DASZ0 +#define DMACB1_TYPE dmacb1.bitc._TYPE +#define DMACB1_MOD dmacb1.bitc._MOD +#define DMACB1_WS dmacb1.bitc._WS +#define DMACB1_DSS dmacb1.bitc._DSS +#define DMACB1_SASZ dmacb1.bitc._SASZ +#define DMACB1_DASZ dmacb1.bitc._DASZ +__IO_EXTERN DMACA2STR dmaca2; +#define DMACA2 dmaca2.lword +#define DMACA2_DENB dmaca2.bit._DENB +#define DMACA2_PAUS dmaca2.bit._PAUS +#define DMACA2_STRG dmaca2.bit._STRG +#define DMACA2_IS4 dmaca2.bit._IS4 +#define DMACA2_IS3 dmaca2.bit._IS3 +#define DMACA2_IS2 dmaca2.bit._IS2 +#define DMACA2_IS1 dmaca2.bit._IS1 +#define DMACA2_IS0 dmaca2.bit._IS0 +#define DMACA2_EIS3 dmaca2.bit._EIS3 +#define DMACA2_EIS2 dmaca2.bit._EIS2 +#define DMACA2_EIS1 dmaca2.bit._EIS1 +#define DMACA2_EIS0 dmaca2.bit._EIS0 +#define DMACA2_BLK3 dmaca2.bit._BLK3 +#define DMACA2_BLK2 dmaca2.bit._BLK2 +#define DMACA2_BLK1 dmaca2.bit._BLK1 +#define DMACA2_BLK0 dmaca2.bit._BLK0 +#define DMACA2_DTCF dmaca2.bit._DTCF +#define DMACA2_DTCE dmaca2.bit._DTCE +#define DMACA2_DTCD dmaca2.bit._DTCD +#define DMACA2_DTCC dmaca2.bit._DTCC +#define DMACA2_DTCB dmaca2.bit._DTCB +#define DMACA2_DTCA dmaca2.bit._DTCA +#define DMACA2_DTC9 dmaca2.bit._DTC9 +#define DMACA2_DTC8 dmaca2.bit._DTC8 +#define DMACA2_DTC7 dmaca2.bit._DTC7 +#define DMACA2_DTC6 dmaca2.bit._DTC6 +#define DMACA2_DTC5 dmaca2.bit._DTC5 +#define DMACA2_DTC4 dmaca2.bit._DTC4 +#define DMACA2_DTC3 dmaca2.bit._DTC3 +#define DMACA2_DTC2 dmaca2.bit._DTC2 +#define DMACA2_DTC1 dmaca2.bit._DTC1 +#define DMACA2_DTC0 dmaca2.bit._DTC0 +#define DMACA2_IS dmaca2.bitc._IS +#define DMACA2_EIS dmaca2.bitc._EIS +#define DMACA2_BLK dmaca2.bitc._BLK +#define DMACA2_DTC dmaca2.bitc._DTC +__IO_EXTERN DMACB2STR dmacb2; +#define DMACB2 dmacb2.lword +#define DMACB2_TYPE1 dmacb2.bit._TYPE1 +#define DMACB2_TYPE0 dmacb2.bit._TYPE0 +#define DMACB2_MOD1 dmacb2.bit._MOD1 +#define DMACB2_MOD0 dmacb2.bit._MOD0 +#define DMACB2_WS1 dmacb2.bit._WS1 +#define DMACB2_WS0 dmacb2.bit._WS0 +#define DMACB2_SADM dmacb2.bit._SADM +#define DMACB2_DADM dmacb2.bit._DADM +#define DMACB2_DTCR dmacb2.bit._DTCR +#define DMACB2_SADR dmacb2.bit._SADR +#define DMACB2_DADR dmacb2.bit._DADR +#define DMACB2_ERIE dmacb2.bit._ERIE +#define DMACB2_EDIE dmacb2.bit._EDIE +#define DMACB2_DSS2 dmacb2.bit._DSS2 +#define DMACB2_DSS1 dmacb2.bit._DSS1 +#define DMACB2_DSS0 dmacb2.bit._DSS0 +#define DMACB2_SASZ7 dmacb2.bit._SASZ7 +#define DMACB2_SASZ6 dmacb2.bit._SASZ6 +#define DMACB2_SASZ5 dmacb2.bit._SASZ5 +#define DMACB2_SASZ4 dmacb2.bit._SASZ4 +#define DMACB2_SASZ3 dmacb2.bit._SASZ3 +#define DMACB2_SASZ2 dmacb2.bit._SASZ2 +#define DMACB2_SASZ1 dmacb2.bit._SASZ1 +#define DMACB2_SASZ0 dmacb2.bit._SASZ0 +#define DMACB2_DASZ7 dmacb2.bit._DASZ7 +#define DMACB2_DASZ6 dmacb2.bit._DASZ6 +#define DMACB2_DASZ5 dmacb2.bit._DASZ5 +#define DMACB2_DASZ4 dmacb2.bit._DASZ4 +#define DMACB2_DASZ3 dmacb2.bit._DASZ3 +#define DMACB2_DASZ2 dmacb2.bit._DASZ2 +#define DMACB2_DASZ1 dmacb2.bit._DASZ1 +#define DMACB2_DASZ0 dmacb2.bit._DASZ0 +#define DMACB2_TYPE dmacb2.bitc._TYPE +#define DMACB2_MOD dmacb2.bitc._MOD +#define DMACB2_WS dmacb2.bitc._WS +#define DMACB2_DSS dmacb2.bitc._DSS +#define DMACB2_SASZ dmacb2.bitc._SASZ +#define DMACB2_DASZ dmacb2.bitc._DASZ +__IO_EXTERN DMACA3STR dmaca3; +#define DMACA3 dmaca3.lword +#define DMACA3_DENB dmaca3.bit._DENB +#define DMACA3_PAUS dmaca3.bit._PAUS +#define DMACA3_STRG dmaca3.bit._STRG +#define DMACA3_IS4 dmaca3.bit._IS4 +#define DMACA3_IS3 dmaca3.bit._IS3 +#define DMACA3_IS2 dmaca3.bit._IS2 +#define DMACA3_IS1 dmaca3.bit._IS1 +#define DMACA3_IS0 dmaca3.bit._IS0 +#define DMACA3_EIS3 dmaca3.bit._EIS3 +#define DMACA3_EIS2 dmaca3.bit._EIS2 +#define DMACA3_EIS1 dmaca3.bit._EIS1 +#define DMACA3_EIS0 dmaca3.bit._EIS0 +#define DMACA3_BLK3 dmaca3.bit._BLK3 +#define DMACA3_BLK2 dmaca3.bit._BLK2 +#define DMACA3_BLK1 dmaca3.bit._BLK1 +#define DMACA3_BLK0 dmaca3.bit._BLK0 +#define DMACA3_DTCF dmaca3.bit._DTCF +#define DMACA3_DTCE dmaca3.bit._DTCE +#define DMACA3_DTCD dmaca3.bit._DTCD +#define DMACA3_DTCC dmaca3.bit._DTCC +#define DMACA3_DTCB dmaca3.bit._DTCB +#define DMACA3_DTCA dmaca3.bit._DTCA +#define DMACA3_DTC9 dmaca3.bit._DTC9 +#define DMACA3_DTC8 dmaca3.bit._DTC8 +#define DMACA3_DTC7 dmaca3.bit._DTC7 +#define DMACA3_DTC6 dmaca3.bit._DTC6 +#define DMACA3_DTC5 dmaca3.bit._DTC5 +#define DMACA3_DTC4 dmaca3.bit._DTC4 +#define DMACA3_DTC3 dmaca3.bit._DTC3 +#define DMACA3_DTC2 dmaca3.bit._DTC2 +#define DMACA3_DTC1 dmaca3.bit._DTC1 +#define DMACA3_DTC0 dmaca3.bit._DTC0 +#define DMACA3_IS dmaca3.bitc._IS +#define DMACA3_EIS dmaca3.bitc._EIS +#define DMACA3_BLK dmaca3.bitc._BLK +#define DMACA3_DTC dmaca3.bitc._DTC +__IO_EXTERN DMACB3STR dmacb3; +#define DMACB3 dmacb3.lword +#define DMACB3_TYPE1 dmacb3.bit._TYPE1 +#define DMACB3_TYPE0 dmacb3.bit._TYPE0 +#define DMACB3_MOD1 dmacb3.bit._MOD1 +#define DMACB3_MOD0 dmacb3.bit._MOD0 +#define DMACB3_WS1 dmacb3.bit._WS1 +#define DMACB3_WS0 dmacb3.bit._WS0 +#define DMACB3_SADM dmacb3.bit._SADM +#define DMACB3_DADM dmacb3.bit._DADM +#define DMACB3_DTCR dmacb3.bit._DTCR +#define DMACB3_SADR dmacb3.bit._SADR +#define DMACB3_DADR dmacb3.bit._DADR +#define DMACB3_ERIE dmacb3.bit._ERIE +#define DMACB3_EDIE dmacb3.bit._EDIE +#define DMACB3_DSS2 dmacb3.bit._DSS2 +#define DMACB3_DSS1 dmacb3.bit._DSS1 +#define DMACB3_DSS0 dmacb3.bit._DSS0 +#define DMACB3_SASZ7 dmacb3.bit._SASZ7 +#define DMACB3_SASZ6 dmacb3.bit._SASZ6 +#define DMACB3_SASZ5 dmacb3.bit._SASZ5 +#define DMACB3_SASZ4 dmacb3.bit._SASZ4 +#define DMACB3_SASZ3 dmacb3.bit._SASZ3 +#define DMACB3_SASZ2 dmacb3.bit._SASZ2 +#define DMACB3_SASZ1 dmacb3.bit._SASZ1 +#define DMACB3_SASZ0 dmacb3.bit._SASZ0 +#define DMACB3_DASZ7 dmacb3.bit._DASZ7 +#define DMACB3_DASZ6 dmacb3.bit._DASZ6 +#define DMACB3_DASZ5 dmacb3.bit._DASZ5 +#define DMACB3_DASZ4 dmacb3.bit._DASZ4 +#define DMACB3_DASZ3 dmacb3.bit._DASZ3 +#define DMACB3_DASZ2 dmacb3.bit._DASZ2 +#define DMACB3_DASZ1 dmacb3.bit._DASZ1 +#define DMACB3_DASZ0 dmacb3.bit._DASZ0 +#define DMACB3_TYPE dmacb3.bitc._TYPE +#define DMACB3_MOD dmacb3.bitc._MOD +#define DMACB3_WS dmacb3.bitc._WS +#define DMACB3_DSS dmacb3.bitc._DSS +#define DMACB3_SASZ dmacb3.bitc._SASZ +#define DMACB3_DASZ dmacb3.bitc._DASZ +__IO_EXTERN DMACA4STR dmaca4; +#define DMACA4 dmaca4.lword +#define DMACA4_DENB dmaca4.bit._DENB +#define DMACA4_PAUS dmaca4.bit._PAUS +#define DMACA4_STRG dmaca4.bit._STRG +#define DMACA4_IS4 dmaca4.bit._IS4 +#define DMACA4_IS3 dmaca4.bit._IS3 +#define DMACA4_IS2 dmaca4.bit._IS2 +#define DMACA4_IS1 dmaca4.bit._IS1 +#define DMACA4_IS0 dmaca4.bit._IS0 +#define DMACA4_EIS3 dmaca4.bit._EIS3 +#define DMACA4_EIS2 dmaca4.bit._EIS2 +#define DMACA4_EIS1 dmaca4.bit._EIS1 +#define DMACA4_EIS0 dmaca4.bit._EIS0 +#define DMACA4_BLK3 dmaca4.bit._BLK3 +#define DMACA4_BLK2 dmaca4.bit._BLK2 +#define DMACA4_BLK1 dmaca4.bit._BLK1 +#define DMACA4_BLK0 dmaca4.bit._BLK0 +#define DMACA4_DTCF dmaca4.bit._DTCF +#define DMACA4_DTCE dmaca4.bit._DTCE +#define DMACA4_DTCD dmaca4.bit._DTCD +#define DMACA4_DTCC dmaca4.bit._DTCC +#define DMACA4_DTCB dmaca4.bit._DTCB +#define DMACA4_DTCA dmaca4.bit._DTCA +#define DMACA4_DTC9 dmaca4.bit._DTC9 +#define DMACA4_DTC8 dmaca4.bit._DTC8 +#define DMACA4_DTC7 dmaca4.bit._DTC7 +#define DMACA4_DTC6 dmaca4.bit._DTC6 +#define DMACA4_DTC5 dmaca4.bit._DTC5 +#define DMACA4_DTC4 dmaca4.bit._DTC4 +#define DMACA4_DTC3 dmaca4.bit._DTC3 +#define DMACA4_DTC2 dmaca4.bit._DTC2 +#define DMACA4_DTC1 dmaca4.bit._DTC1 +#define DMACA4_DTC0 dmaca4.bit._DTC0 +#define DMACA4_IS dmaca4.bitc._IS +#define DMACA4_EIS dmaca4.bitc._EIS +#define DMACA4_BLK dmaca4.bitc._BLK +#define DMACA4_DTC dmaca4.bitc._DTC +__IO_EXTERN DMACB4STR dmacb4; +#define DMACB4 dmacb4.lword +#define DMACB4_TYPE1 dmacb4.bit._TYPE1 +#define DMACB4_TYPE0 dmacb4.bit._TYPE0 +#define DMACB4_MOD1 dmacb4.bit._MOD1 +#define DMACB4_MOD0 dmacb4.bit._MOD0 +#define DMACB4_WS1 dmacb4.bit._WS1 +#define DMACB4_WS0 dmacb4.bit._WS0 +#define DMACB4_SADM dmacb4.bit._SADM +#define DMACB4_DADM dmacb4.bit._DADM +#define DMACB4_DTCR dmacb4.bit._DTCR +#define DMACB4_SADR dmacb4.bit._SADR +#define DMACB4_DADR dmacb4.bit._DADR +#define DMACB4_ERIE dmacb4.bit._ERIE +#define DMACB4_EDIE dmacb4.bit._EDIE +#define DMACB4_DSS2 dmacb4.bit._DSS2 +#define DMACB4_DSS1 dmacb4.bit._DSS1 +#define DMACB4_DSS0 dmacb4.bit._DSS0 +#define DMACB4_SASZ7 dmacb4.bit._SASZ7 +#define DMACB4_SASZ6 dmacb4.bit._SASZ6 +#define DMACB4_SASZ5 dmacb4.bit._SASZ5 +#define DMACB4_SASZ4 dmacb4.bit._SASZ4 +#define DMACB4_SASZ3 dmacb4.bit._SASZ3 +#define DMACB4_SASZ2 dmacb4.bit._SASZ2 +#define DMACB4_SASZ1 dmacb4.bit._SASZ1 +#define DMACB4_SASZ0 dmacb4.bit._SASZ0 +#define DMACB4_DASZ7 dmacb4.bit._DASZ7 +#define DMACB4_DASZ6 dmacb4.bit._DASZ6 +#define DMACB4_DASZ5 dmacb4.bit._DASZ5 +#define DMACB4_DASZ4 dmacb4.bit._DASZ4 +#define DMACB4_DASZ3 dmacb4.bit._DASZ3 +#define DMACB4_DASZ2 dmacb4.bit._DASZ2 +#define DMACB4_DASZ1 dmacb4.bit._DASZ1 +#define DMACB4_DASZ0 dmacb4.bit._DASZ0 +#define DMACB4_TYPE dmacb4.bitc._TYPE +#define DMACB4_MOD dmacb4.bitc._MOD +#define DMACB4_WS dmacb4.bitc._WS +#define DMACB4_DSS dmacb4.bitc._DSS +#define DMACB4_SASZ dmacb4.bitc._SASZ +#define DMACB4_DASZ dmacb4.bitc._DASZ +__IO_EXTERN DMACRSTR dmacr; +#define DMACR dmacr.byte +#define DMACR_DMAE dmacr.bit._DMAE +#define DMACR_PM01 dmacr.bit._PM01 +#define DMACR_DMAH3 dmacr.bit._DMAH3 +#define DMACR_DMAH2 dmacr.bit._DMAH2 +#define DMACR_DMAH1 dmacr.bit._DMAH1 +#define DMACR_DMAH0 dmacr.bit._DMAH0 +#define DMACR_DMAH dmacr.bitc._DMAH +__IO_EXTERN ICS45STR ics45; /* Input Capture 4-7 */ +#define ICS45 ics45.byte +#define ICS45_ICP5 ics45.bit._ICP5 +#define ICS45_ICP4 ics45.bit._ICP4 +#define ICS45_ICE5 ics45.bit._ICE5 +#define ICS45_ICE4 ics45.bit._ICE4 +#define ICS45_EG51 ics45.bit._EG51 +#define ICS45_EG50 ics45.bit._EG50 +#define ICS45_EG41 ics45.bit._EG41 +#define ICS45_EG40 ics45.bit._EG40 +#define ICS45_EG5 ics45.bitc._EG5 +#define ICS45_EG4 ics45.bitc._EG4 +__IO_EXTERN ICS67STR ics67; +#define ICS67 ics67.byte +#define ICS67_ICP7 ics67.bit._ICP7 +#define ICS67_ICP6 ics67.bit._ICP6 +#define ICS67_ICE7 ics67.bit._ICE7 +#define ICS67_ICE6 ics67.bit._ICE6 +#define ICS67_EG71 ics67.bit._EG71 +#define ICS67_EG70 ics67.bit._EG70 +#define ICS67_EG61 ics67.bit._EG61 +#define ICS67_EG60 ics67.bit._EG60 +#define ICS67_EG7 ics67.bitc._EG7 +#define ICS67_EG6 ics67.bitc._EG6 +__IO_EXTERN IPCP4STR ipcp4; +#define IPCP4 ipcp4.word +#define IPCP4_CP15 ipcp4.bit._CP15 +#define IPCP4_CP14 ipcp4.bit._CP14 +#define IPCP4_CP13 ipcp4.bit._CP13 +#define IPCP4_CP12 ipcp4.bit._CP12 +#define IPCP4_CP11 ipcp4.bit._CP11 +#define IPCP4_CP10 ipcp4.bit._CP10 +#define IPCP4_CP9 ipcp4.bit._CP9 +#define IPCP4_CP8 ipcp4.bit._CP8 +#define IPCP4_CP7 ipcp4.bit._CP7 +#define IPCP4_CP6 ipcp4.bit._CP6 +#define IPCP4_CP5 ipcp4.bit._CP5 +#define IPCP4_CP4 ipcp4.bit._CP4 +#define IPCP4_CP3 ipcp4.bit._CP3 +#define IPCP4_CP2 ipcp4.bit._CP2 +#define IPCP4_CP1 ipcp4.bit._CP1 +#define IPCP4_CP0 ipcp4.bit._CP0 +__IO_EXTERN IPCP5STR ipcp5; +#define IPCP5 ipcp5.word +#define IPCP5_CP15 ipcp5.bit._CP15 +#define IPCP5_CP14 ipcp5.bit._CP14 +#define IPCP5_CP13 ipcp5.bit._CP13 +#define IPCP5_CP12 ipcp5.bit._CP12 +#define IPCP5_CP11 ipcp5.bit._CP11 +#define IPCP5_CP10 ipcp5.bit._CP10 +#define IPCP5_CP9 ipcp5.bit._CP9 +#define IPCP5_CP8 ipcp5.bit._CP8 +#define IPCP5_CP7 ipcp5.bit._CP7 +#define IPCP5_CP6 ipcp5.bit._CP6 +#define IPCP5_CP5 ipcp5.bit._CP5 +#define IPCP5_CP4 ipcp5.bit._CP4 +#define IPCP5_CP3 ipcp5.bit._CP3 +#define IPCP5_CP2 ipcp5.bit._CP2 +#define IPCP5_CP1 ipcp5.bit._CP1 +#define IPCP5_CP0 ipcp5.bit._CP0 +__IO_EXTERN IPCP6STR ipcp6; +#define IPCP6 ipcp6.word +#define IPCP6_CP15 ipcp6.bit._CP15 +#define IPCP6_CP14 ipcp6.bit._CP14 +#define IPCP6_CP13 ipcp6.bit._CP13 +#define IPCP6_CP12 ipcp6.bit._CP12 +#define IPCP6_CP11 ipcp6.bit._CP11 +#define IPCP6_CP10 ipcp6.bit._CP10 +#define IPCP6_CP9 ipcp6.bit._CP9 +#define IPCP6_CP8 ipcp6.bit._CP8 +#define IPCP6_CP7 ipcp6.bit._CP7 +#define IPCP6_CP6 ipcp6.bit._CP6 +#define IPCP6_CP5 ipcp6.bit._CP5 +#define IPCP6_CP4 ipcp6.bit._CP4 +#define IPCP6_CP3 ipcp6.bit._CP3 +#define IPCP6_CP2 ipcp6.bit._CP2 +#define IPCP6_CP1 ipcp6.bit._CP1 +#define IPCP6_CP0 ipcp6.bit._CP0 +__IO_EXTERN IPCP7STR ipcp7; +#define IPCP7 ipcp7.word +#define IPCP7_CP15 ipcp7.bit._CP15 +#define IPCP7_CP14 ipcp7.bit._CP14 +#define IPCP7_CP13 ipcp7.bit._CP13 +#define IPCP7_CP12 ipcp7.bit._CP12 +#define IPCP7_CP11 ipcp7.bit._CP11 +#define IPCP7_CP10 ipcp7.bit._CP10 +#define IPCP7_CP9 ipcp7.bit._CP9 +#define IPCP7_CP8 ipcp7.bit._CP8 +#define IPCP7_CP7 ipcp7.bit._CP7 +#define IPCP7_CP6 ipcp7.bit._CP6 +#define IPCP7_CP5 ipcp7.bit._CP5 +#define IPCP7_CP4 ipcp7.bit._CP4 +#define IPCP7_CP3 ipcp7.bit._CP3 +#define IPCP7_CP2 ipcp7.bit._CP2 +#define IPCP7_CP1 ipcp7.bit._CP1 +#define IPCP7_CP0 ipcp7.bit._CP0 +__IO_EXTERN OCS45STR ocs45; /* Output Compare 4-7 */ +#define OCS45 ocs45.word +#define OCS45_CMOD ocs45.bit._CMOD +#define OCS45_OTD5 ocs45.bit._OTD5 +#define OCS45_OTD4 ocs45.bit._OTD4 +#define OCS45_ICP5 ocs45.bit._ICP5 +#define OCS45_ICP4 ocs45.bit._ICP4 +#define OCS45_ICE5 ocs45.bit._ICE5 +#define OCS45_ICE4 ocs45.bit._ICE4 +#define OCS45_CST5 ocs45.bit._CST5 +#define OCS45_CST4 ocs45.bit._CST4 +__IO_EXTERN OCS67STR ocs67; +#define OCS67 ocs67.word +#define OCS67_CMOD ocs67.bit._CMOD +#define OCS67_OTD7 ocs67.bit._OTD7 +#define OCS67_OTD6 ocs67.bit._OTD6 +#define OCS67_ICP7 ocs67.bit._ICP7 +#define OCS67_ICP6 ocs67.bit._ICP6 +#define OCS67_ICE7 ocs67.bit._ICE7 +#define OCS67_ICE6 ocs67.bit._ICE6 +#define OCS67_CST7 ocs67.bit._CST7 +#define OCS67_CST6 ocs67.bit._CST6 +__IO_EXTERN OCCP4STR occp4; +#define OCCP4 occp4.word +#define OCCP4_C15 occp4.bit._C15 +#define OCCP4_C14 occp4.bit._C14 +#define OCCP4_C13 occp4.bit._C13 +#define OCCP4_C12 occp4.bit._C12 +#define OCCP4_C11 occp4.bit._C11 +#define OCCP4_C10 occp4.bit._C10 +#define OCCP4_C9 occp4.bit._C9 +#define OCCP4_C8 occp4.bit._C8 +#define OCCP4_C7 occp4.bit._C7 +#define OCCP4_C6 occp4.bit._C6 +#define OCCP4_C5 occp4.bit._C5 +#define OCCP4_C4 occp4.bit._C4 +#define OCCP4_C3 occp4.bit._C3 +#define OCCP4_C2 occp4.bit._C2 +#define OCCP4_C1 occp4.bit._C1 +#define OCCP4_C0 occp4.bit._C0 +__IO_EXTERN OCCP5STR occp5; +#define OCCP5 occp5.word +#define OCCP5_C15 occp5.bit._C15 +#define OCCP5_C14 occp5.bit._C14 +#define OCCP5_C13 occp5.bit._C13 +#define OCCP5_C12 occp5.bit._C12 +#define OCCP5_C11 occp5.bit._C11 +#define OCCP5_C10 occp5.bit._C10 +#define OCCP5_C9 occp5.bit._C9 +#define OCCP5_C8 occp5.bit._C8 +#define OCCP5_C7 occp5.bit._C7 +#define OCCP5_C6 occp5.bit._C6 +#define OCCP5_C5 occp5.bit._C5 +#define OCCP5_C4 occp5.bit._C4 +#define OCCP5_C3 occp5.bit._C3 +#define OCCP5_C2 occp5.bit._C2 +#define OCCP5_C1 occp5.bit._C1 +#define OCCP5_C0 occp5.bit._C0 +__IO_EXTERN OCCP6STR occp6; +#define OCCP6 occp6.word +#define OCCP6_C15 occp6.bit._C15 +#define OCCP6_C14 occp6.bit._C14 +#define OCCP6_C13 occp6.bit._C13 +#define OCCP6_C12 occp6.bit._C12 +#define OCCP6_C11 occp6.bit._C11 +#define OCCP6_C10 occp6.bit._C10 +#define OCCP6_C9 occp6.bit._C9 +#define OCCP6_C8 occp6.bit._C8 +#define OCCP6_C7 occp6.bit._C7 +#define OCCP6_C6 occp6.bit._C6 +#define OCCP6_C5 occp6.bit._C5 +#define OCCP6_C4 occp6.bit._C4 +#define OCCP6_C3 occp6.bit._C3 +#define OCCP6_C2 occp6.bit._C2 +#define OCCP6_C1 occp6.bit._C1 +#define OCCP6_C0 occp6.bit._C0 +__IO_EXTERN OCCP7STR occp7; +#define OCCP7 occp7.word +#define OCCP7_C15 occp7.bit._C15 +#define OCCP7_C14 occp7.bit._C14 +#define OCCP7_C13 occp7.bit._C13 +#define OCCP7_C12 occp7.bit._C12 +#define OCCP7_C11 occp7.bit._C11 +#define OCCP7_C10 occp7.bit._C10 +#define OCCP7_C9 occp7.bit._C9 +#define OCCP7_C8 occp7.bit._C8 +#define OCCP7_C7 occp7.bit._C7 +#define OCCP7_C6 occp7.bit._C6 +#define OCCP7_C5 occp7.bit._C5 +#define OCCP7_C4 occp7.bit._C4 +#define OCCP7_C3 occp7.bit._C3 +#define OCCP7_C2 occp7.bit._C2 +#define OCCP7_C1 occp7.bit._C1 +#define OCCP7_C0 occp7.bit._C0 +__IO_EXTERN TCDT4STR tcdt4; /* Free Running Timer4 */ +#define TCDT4 tcdt4.word +#define TCDT4_T15 tcdt4.bit._T15 +#define TCDT4_T14 tcdt4.bit._T14 +#define TCDT4_T13 tcdt4.bit._T13 +#define TCDT4_T12 tcdt4.bit._T12 +#define TCDT4_T11 tcdt4.bit._T11 +#define TCDT4_T10 tcdt4.bit._T10 +#define TCDT4_T9 tcdt4.bit._T9 +#define TCDT4_T8 tcdt4.bit._T8 +#define TCDT4_T7 tcdt4.bit._T7 +#define TCDT4_T6 tcdt4.bit._T6 +#define TCDT4_T5 tcdt4.bit._T5 +#define TCDT4_T4 tcdt4.bit._T4 +#define TCDT4_T3 tcdt4.bit._T3 +#define TCDT4_T2 tcdt4.bit._T2 +#define TCDT4_T1 tcdt4.bit._T1 +#define TCDT4_T0 tcdt4.bit._T0 +__IO_EXTERN TCCS4STR tccs4; +#define TCCS4 tccs4.byte +#define TCCS4_ECLK tccs4.bit._ECLK +#define TCCS4_IVF tccs4.bit._IVF +#define TCCS4_IVFE tccs4.bit._IVFE +#define TCCS4_STOP tccs4.bit._STOP +#define TCCS4_MODE tccs4.bit._MODE +#define TCCS4_CLR tccs4.bit._CLR +#define TCCS4_CLK1 tccs4.bit._CLK1 +#define TCCS4_CLK0 tccs4.bit._CLK0 +#define TCCS4_CLK tccs4.bitc._CLK +__IO_EXTERN TCDT5STR tcdt5; /* Free Running Timer5 */ +#define TCDT5 tcdt5.word +#define TCDT5_T15 tcdt5.bit._T15 +#define TCDT5_T14 tcdt5.bit._T14 +#define TCDT5_T13 tcdt5.bit._T13 +#define TCDT5_T12 tcdt5.bit._T12 +#define TCDT5_T11 tcdt5.bit._T11 +#define TCDT5_T10 tcdt5.bit._T10 +#define TCDT5_T9 tcdt5.bit._T9 +#define TCDT5_T8 tcdt5.bit._T8 +#define TCDT5_T7 tcdt5.bit._T7 +#define TCDT5_T6 tcdt5.bit._T6 +#define TCDT5_T5 tcdt5.bit._T5 +#define TCDT5_T4 tcdt5.bit._T4 +#define TCDT5_T3 tcdt5.bit._T3 +#define TCDT5_T2 tcdt5.bit._T2 +#define TCDT5_T1 tcdt5.bit._T1 +#define TCDT5_T0 tcdt5.bit._T0 +__IO_EXTERN TCCS5STR tccs5; +#define TCCS5 tccs5.byte +#define TCCS5_ECLK tccs5.bit._ECLK +#define TCCS5_IVF tccs5.bit._IVF +#define TCCS5_IVFE tccs5.bit._IVFE +#define TCCS5_STOP tccs5.bit._STOP +#define TCCS5_MODE tccs5.bit._MODE +#define TCCS5_CLR tccs5.bit._CLR +#define TCCS5_CLK1 tccs5.bit._CLK1 +#define TCCS5_CLK0 tccs5.bit._CLK0 +#define TCCS5_CLK tccs5.bitc._CLK +__IO_EXTERN TCDT6STR tcdt6; /* Free Running Timer6 */ +#define TCDT6 tcdt6.word +#define TCDT6_T15 tcdt6.bit._T15 +#define TCDT6_T14 tcdt6.bit._T14 +#define TCDT6_T13 tcdt6.bit._T13 +#define TCDT6_T12 tcdt6.bit._T12 +#define TCDT6_T11 tcdt6.bit._T11 +#define TCDT6_T10 tcdt6.bit._T10 +#define TCDT6_T9 tcdt6.bit._T9 +#define TCDT6_T8 tcdt6.bit._T8 +#define TCDT6_T7 tcdt6.bit._T7 +#define TCDT6_T6 tcdt6.bit._T6 +#define TCDT6_T5 tcdt6.bit._T5 +#define TCDT6_T4 tcdt6.bit._T4 +#define TCDT6_T3 tcdt6.bit._T3 +#define TCDT6_T2 tcdt6.bit._T2 +#define TCDT6_T1 tcdt6.bit._T1 +#define TCDT6_T0 tcdt6.bit._T0 +__IO_EXTERN TCCS6STR tccs6; +#define TCCS6 tccs6.byte +#define TCCS6_ECLK tccs6.bit._ECLK +#define TCCS6_IVF tccs6.bit._IVF +#define TCCS6_IVFE tccs6.bit._IVFE +#define TCCS6_STOP tccs6.bit._STOP +#define TCCS6_MODE tccs6.bit._MODE +#define TCCS6_CLR tccs6.bit._CLR +#define TCCS6_CLK1 tccs6.bit._CLK1 +#define TCCS6_CLK0 tccs6.bit._CLK0 +#define TCCS6_CLK tccs6.bitc._CLK +__IO_EXTERN TCDT7STR tcdt7; /* Free Running Timer7 */ +#define TCDT7 tcdt7.word +#define TCDT7_T15 tcdt7.bit._T15 +#define TCDT7_T14 tcdt7.bit._T14 +#define TCDT7_T13 tcdt7.bit._T13 +#define TCDT7_T12 tcdt7.bit._T12 +#define TCDT7_T11 tcdt7.bit._T11 +#define TCDT7_T10 tcdt7.bit._T10 +#define TCDT7_T9 tcdt7.bit._T9 +#define TCDT7_T8 tcdt7.bit._T8 +#define TCDT7_T7 tcdt7.bit._T7 +#define TCDT7_T6 tcdt7.bit._T6 +#define TCDT7_T5 tcdt7.bit._T5 +#define TCDT7_T4 tcdt7.bit._T4 +#define TCDT7_T3 tcdt7.bit._T3 +#define TCDT7_T2 tcdt7.bit._T2 +#define TCDT7_T1 tcdt7.bit._T1 +#define TCDT7_T0 tcdt7.bit._T0 +__IO_EXTERN TCCS7STR tccs7; +#define TCCS7 tccs7.byte +#define TCCS7_ECLK tccs7.bit._ECLK +#define TCCS7_IVF tccs7.bit._IVF +#define TCCS7_IVFE tccs7.bit._IVFE +#define TCCS7_STOP tccs7.bit._STOP +#define TCCS7_MODE tccs7.bit._MODE +#define TCCS7_CLR tccs7.bit._CLR +#define TCCS7_CLK1 tccs7.bit._CLK1 +#define TCCS7_CLK0 tccs7.bit._CLK0 +#define TCCS7_CLK tccs7.bitc._CLK +__IO_EXTERN ROMSSTR roms; /* ROM Select Register */ +#define ROMS roms.word +#define ROMS_D15 roms.bit._D15 +#define ROMS_D14 roms.bit._D14 +#define ROMS_D13 roms.bit._D13 +#define ROMS_D12 roms.bit._D12 +#define ROMS_D11 roms.bit._D11 +#define ROMS_D10 roms.bit._D10 +#define ROMS_D9 roms.bit._D9 +#define ROMS_D8 roms.bit._D8 +#define ROMS_D7 roms.bit._D7 +#define ROMS_D6 roms.bit._D6 +#define ROMS_D5 roms.bit._D5 +#define ROMS_D4 roms.bit._D4 +#define ROMS_D3 roms.bit._D3 +#define ROMS_D2 roms.bit._D2 +#define ROMS_D1 roms.bit._D1 +#define ROMS_D0 roms.bit._D0 +__IO_EXTERN IO_LWORD bsd0; /* Bit Search Module */ +#define BSD0 bsd0 +__IO_EXTERN IO_LWORD bsd1; +#define BSD1 bsd1 +__IO_EXTERN IO_LWORD bsdc; +#define BSDC bsdc +__IO_EXTERN IO_LWORD bsrr; +#define BSRR bsrr +__IO_EXTERN ICR00STR icr00; /* Interrupt Control Unit */ +#define ICR00 icr00.byte +#define ICR00_ICR4 icr00.bit._ICR4 +#define ICR00_ICR3 icr00.bit._ICR3 +#define ICR00_ICR2 icr00.bit._ICR2 +#define ICR00_ICR1 icr00.bit._ICR1 +#define ICR00_ICR0 icr00.bit._ICR0 +__IO_EXTERN ICR01STR icr01; +#define ICR01 icr01.byte +#define ICR01_ICR4 icr01.bit._ICR4 +#define ICR01_ICR3 icr01.bit._ICR3 +#define ICR01_ICR2 icr01.bit._ICR2 +#define ICR01_ICR1 icr01.bit._ICR1 +#define ICR01_ICR0 icr01.bit._ICR0 +__IO_EXTERN ICR02STR icr02; +#define ICR02 icr02.byte +#define ICR02_ICR4 icr02.bit._ICR4 +#define ICR02_ICR3 icr02.bit._ICR3 +#define ICR02_ICR2 icr02.bit._ICR2 +#define ICR02_ICR1 icr02.bit._ICR1 +#define ICR02_ICR0 icr02.bit._ICR0 +__IO_EXTERN ICR03STR icr03; +#define ICR03 icr03.byte +#define ICR03_ICR4 icr03.bit._ICR4 +#define ICR03_ICR3 icr03.bit._ICR3 +#define ICR03_ICR2 icr03.bit._ICR2 +#define ICR03_ICR1 icr03.bit._ICR1 +#define ICR03_ICR0 icr03.bit._ICR0 +__IO_EXTERN ICR04STR icr04; +#define ICR04 icr04.byte +#define ICR04_ICR4 icr04.bit._ICR4 +#define ICR04_ICR3 icr04.bit._ICR3 +#define ICR04_ICR2 icr04.bit._ICR2 +#define ICR04_ICR1 icr04.bit._ICR1 +#define ICR04_ICR0 icr04.bit._ICR0 +__IO_EXTERN ICR05STR icr05; +#define ICR05 icr05.byte +#define ICR05_ICR4 icr05.bit._ICR4 +#define ICR05_ICR3 icr05.bit._ICR3 +#define ICR05_ICR2 icr05.bit._ICR2 +#define ICR05_ICR1 icr05.bit._ICR1 +#define ICR05_ICR0 icr05.bit._ICR0 +__IO_EXTERN ICR06STR icr06; +#define ICR06 icr06.byte +#define ICR06_ICR4 icr06.bit._ICR4 +#define ICR06_ICR3 icr06.bit._ICR3 +#define ICR06_ICR2 icr06.bit._ICR2 +#define ICR06_ICR1 icr06.bit._ICR1 +#define ICR06_ICR0 icr06.bit._ICR0 +__IO_EXTERN ICR07STR icr07; +#define ICR07 icr07.byte +#define ICR07_ICR4 icr07.bit._ICR4 +#define ICR07_ICR3 icr07.bit._ICR3 +#define ICR07_ICR2 icr07.bit._ICR2 +#define ICR07_ICR1 icr07.bit._ICR1 +#define ICR07_ICR0 icr07.bit._ICR0 +__IO_EXTERN ICR08STR icr08; +#define ICR08 icr08.byte +#define ICR08_ICR4 icr08.bit._ICR4 +#define ICR08_ICR3 icr08.bit._ICR3 +#define ICR08_ICR2 icr08.bit._ICR2 +#define ICR08_ICR1 icr08.bit._ICR1 +#define ICR08_ICR0 icr08.bit._ICR0 +__IO_EXTERN ICR09STR icr09; +#define ICR09 icr09.byte +#define ICR09_ICR4 icr09.bit._ICR4 +#define ICR09_ICR3 icr09.bit._ICR3 +#define ICR09_ICR2 icr09.bit._ICR2 +#define ICR09_ICR1 icr09.bit._ICR1 +#define ICR09_ICR0 icr09.bit._ICR0 +__IO_EXTERN ICR10STR icr10; +#define ICR10 icr10.byte +#define ICR10_ICR4 icr10.bit._ICR4 +#define ICR10_ICR3 icr10.bit._ICR3 +#define ICR10_ICR2 icr10.bit._ICR2 +#define ICR10_ICR1 icr10.bit._ICR1 +#define ICR10_ICR0 icr10.bit._ICR0 +__IO_EXTERN ICR11STR icr11; +#define ICR11 icr11.byte +#define ICR11_ICR4 icr11.bit._ICR4 +#define ICR11_ICR3 icr11.bit._ICR3 +#define ICR11_ICR2 icr11.bit._ICR2 +#define ICR11_ICR1 icr11.bit._ICR1 +#define ICR11_ICR0 icr11.bit._ICR0 +__IO_EXTERN ICR12STR icr12; +#define ICR12 icr12.byte +#define ICR12_ICR4 icr12.bit._ICR4 +#define ICR12_ICR3 icr12.bit._ICR3 +#define ICR12_ICR2 icr12.bit._ICR2 +#define ICR12_ICR1 icr12.bit._ICR1 +#define ICR12_ICR0 icr12.bit._ICR0 +__IO_EXTERN ICR13STR icr13; +#define ICR13 icr13.byte +#define ICR13_ICR4 icr13.bit._ICR4 +#define ICR13_ICR3 icr13.bit._ICR3 +#define ICR13_ICR2 icr13.bit._ICR2 +#define ICR13_ICR1 icr13.bit._ICR1 +#define ICR13_ICR0 icr13.bit._ICR0 +__IO_EXTERN ICR14STR icr14; +#define ICR14 icr14.byte +#define ICR14_ICR4 icr14.bit._ICR4 +#define ICR14_ICR3 icr14.bit._ICR3 +#define ICR14_ICR2 icr14.bit._ICR2 +#define ICR14_ICR1 icr14.bit._ICR1 +#define ICR14_ICR0 icr14.bit._ICR0 +__IO_EXTERN ICR15STR icr15; +#define ICR15 icr15.byte +#define ICR15_ICR4 icr15.bit._ICR4 +#define ICR15_ICR3 icr15.bit._ICR3 +#define ICR15_ICR2 icr15.bit._ICR2 +#define ICR15_ICR1 icr15.bit._ICR1 +#define ICR15_ICR0 icr15.bit._ICR0 +__IO_EXTERN ICR16STR icr16; +#define ICR16 icr16.byte +#define ICR16_ICR4 icr16.bit._ICR4 +#define ICR16_ICR3 icr16.bit._ICR3 +#define ICR16_ICR2 icr16.bit._ICR2 +#define ICR16_ICR1 icr16.bit._ICR1 +#define ICR16_ICR0 icr16.bit._ICR0 +__IO_EXTERN ICR17STR icr17; +#define ICR17 icr17.byte +#define ICR17_ICR4 icr17.bit._ICR4 +#define ICR17_ICR3 icr17.bit._ICR3 +#define ICR17_ICR2 icr17.bit._ICR2 +#define ICR17_ICR1 icr17.bit._ICR1 +#define ICR17_ICR0 icr17.bit._ICR0 +__IO_EXTERN ICR18STR icr18; +#define ICR18 icr18.byte +#define ICR18_ICR4 icr18.bit._ICR4 +#define ICR18_ICR3 icr18.bit._ICR3 +#define ICR18_ICR2 icr18.bit._ICR2 +#define ICR18_ICR1 icr18.bit._ICR1 +#define ICR18_ICR0 icr18.bit._ICR0 +__IO_EXTERN ICR19STR icr19; +#define ICR19 icr19.byte +#define ICR19_ICR4 icr19.bit._ICR4 +#define ICR19_ICR3 icr19.bit._ICR3 +#define ICR19_ICR2 icr19.bit._ICR2 +#define ICR19_ICR1 icr19.bit._ICR1 +#define ICR19_ICR0 icr19.bit._ICR0 +__IO_EXTERN ICR20STR icr20; +#define ICR20 icr20.byte +#define ICR20_ICR4 icr20.bit._ICR4 +#define ICR20_ICR3 icr20.bit._ICR3 +#define ICR20_ICR2 icr20.bit._ICR2 +#define ICR20_ICR1 icr20.bit._ICR1 +#define ICR20_ICR0 icr20.bit._ICR0 +__IO_EXTERN ICR21STR icr21; +#define ICR21 icr21.byte +#define ICR21_ICR4 icr21.bit._ICR4 +#define ICR21_ICR3 icr21.bit._ICR3 +#define ICR21_ICR2 icr21.bit._ICR2 +#define ICR21_ICR1 icr21.bit._ICR1 +#define ICR21_ICR0 icr21.bit._ICR0 +__IO_EXTERN ICR22STR icr22; +#define ICR22 icr22.byte +#define ICR22_ICR4 icr22.bit._ICR4 +#define ICR22_ICR3 icr22.bit._ICR3 +#define ICR22_ICR2 icr22.bit._ICR2 +#define ICR22_ICR1 icr22.bit._ICR1 +#define ICR22_ICR0 icr22.bit._ICR0 +__IO_EXTERN ICR23STR icr23; +#define ICR23 icr23.byte +#define ICR23_ICR4 icr23.bit._ICR4 +#define ICR23_ICR3 icr23.bit._ICR3 +#define ICR23_ICR2 icr23.bit._ICR2 +#define ICR23_ICR1 icr23.bit._ICR1 +#define ICR23_ICR0 icr23.bit._ICR0 +__IO_EXTERN ICR24STR icr24; +#define ICR24 icr24.byte +#define ICR24_ICR4 icr24.bit._ICR4 +#define ICR24_ICR3 icr24.bit._ICR3 +#define ICR24_ICR2 icr24.bit._ICR2 +#define ICR24_ICR1 icr24.bit._ICR1 +#define ICR24_ICR0 icr24.bit._ICR0 +__IO_EXTERN ICR25STR icr25; +#define ICR25 icr25.byte +#define ICR25_ICR4 icr25.bit._ICR4 +#define ICR25_ICR3 icr25.bit._ICR3 +#define ICR25_ICR2 icr25.bit._ICR2 +#define ICR25_ICR1 icr25.bit._ICR1 +#define ICR25_ICR0 icr25.bit._ICR0 +__IO_EXTERN ICR26STR icr26; +#define ICR26 icr26.byte +#define ICR26_ICR4 icr26.bit._ICR4 +#define ICR26_ICR3 icr26.bit._ICR3 +#define ICR26_ICR2 icr26.bit._ICR2 +#define ICR26_ICR1 icr26.bit._ICR1 +#define ICR26_ICR0 icr26.bit._ICR0 +__IO_EXTERN ICR27STR icr27; +#define ICR27 icr27.byte +#define ICR27_ICR4 icr27.bit._ICR4 +#define ICR27_ICR3 icr27.bit._ICR3 +#define ICR27_ICR2 icr27.bit._ICR2 +#define ICR27_ICR1 icr27.bit._ICR1 +#define ICR27_ICR0 icr27.bit._ICR0 +__IO_EXTERN ICR28STR icr28; +#define ICR28 icr28.byte +#define ICR28_ICR4 icr28.bit._ICR4 +#define ICR28_ICR3 icr28.bit._ICR3 +#define ICR28_ICR2 icr28.bit._ICR2 +#define ICR28_ICR1 icr28.bit._ICR1 +#define ICR28_ICR0 icr28.bit._ICR0 +__IO_EXTERN ICR29STR icr29; +#define ICR29 icr29.byte +#define ICR29_ICR4 icr29.bit._ICR4 +#define ICR29_ICR3 icr29.bit._ICR3 +#define ICR29_ICR2 icr29.bit._ICR2 +#define ICR29_ICR1 icr29.bit._ICR1 +#define ICR29_ICR0 icr29.bit._ICR0 +__IO_EXTERN ICR30STR icr30; +#define ICR30 icr30.byte +#define ICR30_ICR4 icr30.bit._ICR4 +#define ICR30_ICR3 icr30.bit._ICR3 +#define ICR30_ICR2 icr30.bit._ICR2 +#define ICR30_ICR1 icr30.bit._ICR1 +#define ICR30_ICR0 icr30.bit._ICR0 +__IO_EXTERN ICR31STR icr31; +#define ICR31 icr31.byte +#define ICR31_ICR4 icr31.bit._ICR4 +#define ICR31_ICR3 icr31.bit._ICR3 +#define ICR31_ICR2 icr31.bit._ICR2 +#define ICR31_ICR1 icr31.bit._ICR1 +#define ICR31_ICR0 icr31.bit._ICR0 +__IO_EXTERN ICR32STR icr32; +#define ICR32 icr32.byte +#define ICR32_ICR4 icr32.bit._ICR4 +#define ICR32_ICR3 icr32.bit._ICR3 +#define ICR32_ICR2 icr32.bit._ICR2 +#define ICR32_ICR1 icr32.bit._ICR1 +#define ICR32_ICR0 icr32.bit._ICR0 +__IO_EXTERN ICR33STR icr33; +#define ICR33 icr33.byte +#define ICR33_ICR4 icr33.bit._ICR4 +#define ICR33_ICR3 icr33.bit._ICR3 +#define ICR33_ICR2 icr33.bit._ICR2 +#define ICR33_ICR1 icr33.bit._ICR1 +#define ICR33_ICR0 icr33.bit._ICR0 +__IO_EXTERN ICR34STR icr34; +#define ICR34 icr34.byte +#define ICR34_ICR4 icr34.bit._ICR4 +#define ICR34_ICR3 icr34.bit._ICR3 +#define ICR34_ICR2 icr34.bit._ICR2 +#define ICR34_ICR1 icr34.bit._ICR1 +#define ICR34_ICR0 icr34.bit._ICR0 +__IO_EXTERN ICR35STR icr35; +#define ICR35 icr35.byte +#define ICR35_ICR4 icr35.bit._ICR4 +#define ICR35_ICR3 icr35.bit._ICR3 +#define ICR35_ICR2 icr35.bit._ICR2 +#define ICR35_ICR1 icr35.bit._ICR1 +#define ICR35_ICR0 icr35.bit._ICR0 +__IO_EXTERN ICR36STR icr36; +#define ICR36 icr36.byte +#define ICR36_ICR4 icr36.bit._ICR4 +#define ICR36_ICR3 icr36.bit._ICR3 +#define ICR36_ICR2 icr36.bit._ICR2 +#define ICR36_ICR1 icr36.bit._ICR1 +#define ICR36_ICR0 icr36.bit._ICR0 +__IO_EXTERN ICR37STR icr37; +#define ICR37 icr37.byte +#define ICR37_ICR4 icr37.bit._ICR4 +#define ICR37_ICR3 icr37.bit._ICR3 +#define ICR37_ICR2 icr37.bit._ICR2 +#define ICR37_ICR1 icr37.bit._ICR1 +#define ICR37_ICR0 icr37.bit._ICR0 +__IO_EXTERN ICR38STR icr38; +#define ICR38 icr38.byte +#define ICR38_ICR4 icr38.bit._ICR4 +#define ICR38_ICR3 icr38.bit._ICR3 +#define ICR38_ICR2 icr38.bit._ICR2 +#define ICR38_ICR1 icr38.bit._ICR1 +#define ICR38_ICR0 icr38.bit._ICR0 +__IO_EXTERN ICR39STR icr39; +#define ICR39 icr39.byte +#define ICR39_ICR4 icr39.bit._ICR4 +#define ICR39_ICR3 icr39.bit._ICR3 +#define ICR39_ICR2 icr39.bit._ICR2 +#define ICR39_ICR1 icr39.bit._ICR1 +#define ICR39_ICR0 icr39.bit._ICR0 +__IO_EXTERN ICR40STR icr40; +#define ICR40 icr40.byte +#define ICR40_ICR4 icr40.bit._ICR4 +#define ICR40_ICR3 icr40.bit._ICR3 +#define ICR40_ICR2 icr40.bit._ICR2 +#define ICR40_ICR1 icr40.bit._ICR1 +#define ICR40_ICR0 icr40.bit._ICR0 +__IO_EXTERN ICR41STR icr41; +#define ICR41 icr41.byte +#define ICR41_ICR4 icr41.bit._ICR4 +#define ICR41_ICR3 icr41.bit._ICR3 +#define ICR41_ICR2 icr41.bit._ICR2 +#define ICR41_ICR1 icr41.bit._ICR1 +#define ICR41_ICR0 icr41.bit._ICR0 +__IO_EXTERN ICR42STR icr42; +#define ICR42 icr42.byte +#define ICR42_ICR4 icr42.bit._ICR4 +#define ICR42_ICR3 icr42.bit._ICR3 +#define ICR42_ICR2 icr42.bit._ICR2 +#define ICR42_ICR1 icr42.bit._ICR1 +#define ICR42_ICR0 icr42.bit._ICR0 +__IO_EXTERN ICR43STR icr43; +#define ICR43 icr43.byte +#define ICR43_ICR4 icr43.bit._ICR4 +#define ICR43_ICR3 icr43.bit._ICR3 +#define ICR43_ICR2 icr43.bit._ICR2 +#define ICR43_ICR1 icr43.bit._ICR1 +#define ICR43_ICR0 icr43.bit._ICR0 +__IO_EXTERN ICR44STR icr44; +#define ICR44 icr44.byte +#define ICR44_ICR4 icr44.bit._ICR4 +#define ICR44_ICR3 icr44.bit._ICR3 +#define ICR44_ICR2 icr44.bit._ICR2 +#define ICR44_ICR1 icr44.bit._ICR1 +#define ICR44_ICR0 icr44.bit._ICR0 +__IO_EXTERN ICR45STR icr45; +#define ICR45 icr45.byte +#define ICR45_ICR4 icr45.bit._ICR4 +#define ICR45_ICR3 icr45.bit._ICR3 +#define ICR45_ICR2 icr45.bit._ICR2 +#define ICR45_ICR1 icr45.bit._ICR1 +#define ICR45_ICR0 icr45.bit._ICR0 +__IO_EXTERN ICR46STR icr46; +#define ICR46 icr46.byte +#define ICR46_ICR4 icr46.bit._ICR4 +#define ICR46_ICR3 icr46.bit._ICR3 +#define ICR46_ICR2 icr46.bit._ICR2 +#define ICR46_ICR1 icr46.bit._ICR1 +#define ICR46_ICR0 icr46.bit._ICR0 +__IO_EXTERN ICR47STR icr47; +#define ICR47 icr47.byte +#define ICR47_ICR4 icr47.bit._ICR4 +#define ICR47_ICR3 icr47.bit._ICR3 +#define ICR47_ICR2 icr47.bit._ICR2 +#define ICR47_ICR1 icr47.bit._ICR1 +#define ICR47_ICR0 icr47.bit._ICR0 +__IO_EXTERN ICR48STR icr48; +#define ICR48 icr48.byte +#define ICR48_ICR4 icr48.bit._ICR4 +#define ICR48_ICR3 icr48.bit._ICR3 +#define ICR48_ICR2 icr48.bit._ICR2 +#define ICR48_ICR1 icr48.bit._ICR1 +#define ICR48_ICR0 icr48.bit._ICR0 +__IO_EXTERN ICR49STR icr49; +#define ICR49 icr49.byte +#define ICR49_ICR4 icr49.bit._ICR4 +#define ICR49_ICR3 icr49.bit._ICR3 +#define ICR49_ICR2 icr49.bit._ICR2 +#define ICR49_ICR1 icr49.bit._ICR1 +#define ICR49_ICR0 icr49.bit._ICR0 +__IO_EXTERN ICR50STR icr50; +#define ICR50 icr50.byte +#define ICR50_ICR4 icr50.bit._ICR4 +#define ICR50_ICR3 icr50.bit._ICR3 +#define ICR50_ICR2 icr50.bit._ICR2 +#define ICR50_ICR1 icr50.bit._ICR1 +#define ICR50_ICR0 icr50.bit._ICR0 +__IO_EXTERN ICR51STR icr51; +#define ICR51 icr51.byte +#define ICR51_ICR4 icr51.bit._ICR4 +#define ICR51_ICR3 icr51.bit._ICR3 +#define ICR51_ICR2 icr51.bit._ICR2 +#define ICR51_ICR1 icr51.bit._ICR1 +#define ICR51_ICR0 icr51.bit._ICR0 +__IO_EXTERN ICR52STR icr52; +#define ICR52 icr52.byte +#define ICR52_ICR4 icr52.bit._ICR4 +#define ICR52_ICR3 icr52.bit._ICR3 +#define ICR52_ICR2 icr52.bit._ICR2 +#define ICR52_ICR1 icr52.bit._ICR1 +#define ICR52_ICR0 icr52.bit._ICR0 +__IO_EXTERN ICR53STR icr53; +#define ICR53 icr53.byte +#define ICR53_ICR4 icr53.bit._ICR4 +#define ICR53_ICR3 icr53.bit._ICR3 +#define ICR53_ICR2 icr53.bit._ICR2 +#define ICR53_ICR1 icr53.bit._ICR1 +#define ICR53_ICR0 icr53.bit._ICR0 +__IO_EXTERN ICR54STR icr54; +#define ICR54 icr54.byte +#define ICR54_ICR4 icr54.bit._ICR4 +#define ICR54_ICR3 icr54.bit._ICR3 +#define ICR54_ICR2 icr54.bit._ICR2 +#define ICR54_ICR1 icr54.bit._ICR1 +#define ICR54_ICR0 icr54.bit._ICR0 +__IO_EXTERN ICR55STR icr55; +#define ICR55 icr55.byte +#define ICR55_ICR4 icr55.bit._ICR4 +#define ICR55_ICR3 icr55.bit._ICR3 +#define ICR55_ICR2 icr55.bit._ICR2 +#define ICR55_ICR1 icr55.bit._ICR1 +#define ICR55_ICR0 icr55.bit._ICR0 +__IO_EXTERN ICR56STR icr56; +#define ICR56 icr56.byte +#define ICR56_ICR4 icr56.bit._ICR4 +#define ICR56_ICR3 icr56.bit._ICR3 +#define ICR56_ICR2 icr56.bit._ICR2 +#define ICR56_ICR1 icr56.bit._ICR1 +#define ICR56_ICR0 icr56.bit._ICR0 +__IO_EXTERN ICR57STR icr57; +#define ICR57 icr57.byte +#define ICR57_ICR4 icr57.bit._ICR4 +#define ICR57_ICR3 icr57.bit._ICR3 +#define ICR57_ICR2 icr57.bit._ICR2 +#define ICR57_ICR1 icr57.bit._ICR1 +#define ICR57_ICR0 icr57.bit._ICR0 +__IO_EXTERN ICR58STR icr58; +#define ICR58 icr58.byte +#define ICR58_ICR4 icr58.bit._ICR4 +#define ICR58_ICR3 icr58.bit._ICR3 +#define ICR58_ICR2 icr58.bit._ICR2 +#define ICR58_ICR1 icr58.bit._ICR1 +#define ICR58_ICR0 icr58.bit._ICR0 +__IO_EXTERN ICR59STR icr59; +#define ICR59 icr59.byte +#define ICR59_ICR4 icr59.bit._ICR4 +#define ICR59_ICR3 icr59.bit._ICR3 +#define ICR59_ICR2 icr59.bit._ICR2 +#define ICR59_ICR1 icr59.bit._ICR1 +#define ICR59_ICR0 icr59.bit._ICR0 +__IO_EXTERN ICR60STR icr60; +#define ICR60 icr60.byte +#define ICR60_ICR4 icr60.bit._ICR4 +#define ICR60_ICR3 icr60.bit._ICR3 +#define ICR60_ICR2 icr60.bit._ICR2 +#define ICR60_ICR1 icr60.bit._ICR1 +#define ICR60_ICR0 icr60.bit._ICR0 +__IO_EXTERN ICR61STR icr61; +#define ICR61 icr61.byte +#define ICR61_ICR4 icr61.bit._ICR4 +#define ICR61_ICR3 icr61.bit._ICR3 +#define ICR61_ICR2 icr61.bit._ICR2 +#define ICR61_ICR1 icr61.bit._ICR1 +#define ICR61_ICR0 icr61.bit._ICR0 +__IO_EXTERN ICR62STR icr62; +#define ICR62 icr62.byte +#define ICR62_ICR4 icr62.bit._ICR4 +#define ICR62_ICR3 icr62.bit._ICR3 +#define ICR62_ICR2 icr62.bit._ICR2 +#define ICR62_ICR1 icr62.bit._ICR1 +#define ICR62_ICR0 icr62.bit._ICR0 +__IO_EXTERN ICR63STR icr63; +#define ICR63 icr63.byte +#define ICR63_ICR4 icr63.bit._ICR4 +#define ICR63_ICR3 icr63.bit._ICR3 +#define ICR63_ICR2 icr63.bit._ICR2 +#define ICR63_ICR1 icr63.bit._ICR1 +#define ICR63_ICR0 icr63.bit._ICR0 +__IO_EXTERN RSRRSTR rsrr; /* Clock Control Unit */ +#define RSRR rsrr.byte +#define RSRR_INIT rsrr.bit._INIT +#define RSRR_HSTB rsrr.bit._HSTB +#define RSRR_WDOG rsrr.bit._WDOG +#define RSRR_ERST rsrr.bit._ERST +#define RSRR_SRST rsrr.bit._SRST +#define RSRR_LINIT rsrr.bit._LINIT +#define RSRR_WT1 rsrr.bit._WT1 +#define RSRR_WT0 rsrr.bit._WT0 +#define RSRR_WT rsrr.bitc._WT +__IO_EXTERN STCRSTR stcr; +#define STCR stcr.byte +#define STCR_STOP stcr.bit._STOP +#define STCR_SLEEP stcr.bit._SLEEP +#define STCR_HIZ stcr.bit._HIZ +#define STCR_SRST stcr.bit._SRST +#define STCR_OS1 stcr.bit._OS1 +#define STCR_OS0 stcr.bit._OS0 +#define STCR_OSCD2 stcr.bit._OSCD2 +#define STCR_OSCD1 stcr.bit._OSCD1 +#define STCR_OS stcr.bitc._OS +#define STCR_OSCD stcr.bitc._OSCD +__IO_EXTERN TBCRSTR tbcr; +#define TBCR tbcr.byte +#define TBCR_TBIF tbcr.bit._TBIF +#define TBCR_TBIE tbcr.bit._TBIE +#define TBCR_TBC2 tbcr.bit._TBC2 +#define TBCR_TBC1 tbcr.bit._TBC1 +#define TBCR_TBC0 tbcr.bit._TBC0 +#define TBCR_SYNCR tbcr.bit._SYNCR +#define TBCR_SYNCS tbcr.bit._SYNCS +#define TBCR_TBC tbcr.bitc._TBC +__IO_EXTERN CTBRSTR ctbr; +#define CTBR ctbr.byte +#define CTBR_D7 ctbr.bit._D7 +#define CTBR_D6 ctbr.bit._D6 +#define CTBR_D5 ctbr.bit._D5 +#define CTBR_D4 ctbr.bit._D4 +#define CTBR_D3 ctbr.bit._D3 +#define CTBR_D2 ctbr.bit._D2 +#define CTBR_D1 ctbr.bit._D1 +#define CTBR_D0 ctbr.bit._D0 +__IO_EXTERN CLKRSTR clkr; +#define CLKR clkr.byte +#define CLKR_SCKEN clkr.bit._SCKEN +#define CLKR_PLL1EN clkr.bit._PLL1EN +#define CLKR_CLKS1 clkr.bit._CLKS1 +#define CLKR_CLKS0 clkr.bit._CLKS0 +#define CLKR_CLKS clkr.bitc._CLKS +__IO_EXTERN WPRSTR wpr; +#define WPR wpr.byte +#define WPR_D7 wpr.bit._D7 +#define WPR_D6 wpr.bit._D6 +#define WPR_D5 wpr.bit._D5 +#define WPR_D4 wpr.bit._D4 +#define WPR_D3 wpr.bit._D3 +#define WPR_D2 wpr.bit._D2 +#define WPR_D1 wpr.bit._D1 +#define WPR_D0 wpr.bit._D0 +__IO_EXTERN DIVR0STR divr0; +#define DIVR0 divr0.byte +#define DIVR0_B3 divr0.bit._B3 +#define DIVR0_B2 divr0.bit._B2 +#define DIVR0_B1 divr0.bit._B1 +#define DIVR0_B0 divr0.bit._B0 +#define DIVR0_P3 divr0.bit._P3 +#define DIVR0_P2 divr0.bit._P2 +#define DIVR0_P1 divr0.bit._P1 +#define DIVR0_P0 divr0.bit._P0 +#define DIVR0_B divr0.bitc._B +#define DIVR0_P divr0.bitc._P +__IO_EXTERN DIVR1STR divr1; +#define DIVR1 divr1.byte +#define DIVR1_T3 divr1.bit._T3 +#define DIVR1_T2 divr1.bit._T2 +#define DIVR1_T1 divr1.bit._T1 +#define DIVR1_T0 divr1.bit._T0 +#define DIVR1_T divr1.bitc._T +__IO_EXTERN PLLDIVMSTR plldivm; /* PLL - Clock Gear Unit: */ +#define PLLDIVM plldivm.byte +#define PLLDIVM_DVM3 plldivm.bit._DVM3 +#define PLLDIVM_DVM2 plldivm.bit._DVM2 +#define PLLDIVM_DVM1 plldivm.bit._DVM1 +#define PLLDIVM_DVM0 plldivm.bit._DVM0 +#define PLLDIVM_DVM plldivm.bitc._DVM +__IO_EXTERN PLLDIVNSTR plldivn; +#define PLLDIVN plldivn.byte +#define PLLDIVN_DVN5 plldivn.bit._DVN5 +#define PLLDIVN_DVN4 plldivn.bit._DVN4 +#define PLLDIVN_DVN3 plldivn.bit._DVN3 +#define PLLDIVN_DVN2 plldivn.bit._DVN2 +#define PLLDIVN_DVN1 plldivn.bit._DVN1 +#define PLLDIVN_DVN0 plldivn.bit._DVN0 +#define PLLDIVN_DVN plldivn.bitc._DVN +__IO_EXTERN PLLDIVGSTR plldivg; +#define PLLDIVG plldivg.byte +#define PLLDIVG_DVG3 plldivg.bit._DVG3 +#define PLLDIVG_DVG2 plldivg.bit._DVG2 +#define PLLDIVG_DVG1 plldivg.bit._DVG1 +#define PLLDIVG_DVG0 plldivg.bit._DVG0 +#define PLLDIVG_DVG plldivg.bitc._DVG +__IO_EXTERN PLLMULGSTR pllmulg; +#define PLLMULG pllmulg.byte +#define PLLMULG_MLG7 pllmulg.bit._MLG7 +#define PLLMULG_MLG6 pllmulg.bit._MLG6 +#define PLLMULG_MLG5 pllmulg.bit._MLG5 +#define PLLMULG_MLG4 pllmulg.bit._MLG4 +#define PLLMULG_MLG3 pllmulg.bit._MLG3 +#define PLLMULG_MLG2 pllmulg.bit._MLG2 +#define PLLMULG_MLG1 pllmulg.bit._MLG1 +#define PLLMULG_MLG0 pllmulg.bit._MLG0 +#define PLLMULG_MLG pllmulg.bitc._MLG +__IO_EXTERN PLLCTRLSTR pllctrl; +#define PLLCTRL pllctrl.byte +#define PLLCTRL_IEDN pllctrl.bit._IEDN +#define PLLCTRL_GRDN pllctrl.bit._GRDN +#define PLLCTRL_IEUP pllctrl.bit._IEUP +#define PLLCTRL_GRUP pllctrl.bit._GRUP +__IO_EXTERN OSCC1STR oscc1; /* Main/Sub Oscillator Control */ +#define OSCC1 oscc1.byte +#define OSCC1_FCI oscc1.bit._FCI +#define OSCC1_RFBEN oscc1.bit._RFBEN +#define OSCC1_OSCR oscc1.bit._OSCR +__IO_EXTERN OSCS1STR oscs1; +#define OSCS1 oscs1.byte +#define OSCS1_OSCS7 oscs1.bit._OSCS7 +#define OSCS1_OSCS6 oscs1.bit._OSCS6 +#define OSCS1_OSCS5 oscs1.bit._OSCS5 +#define OSCS1_OSCS4 oscs1.bit._OSCS4 +#define OSCS1_OSCS3 oscs1.bit._OSCS3 +#define OSCS1_OSCS2 oscs1.bit._OSCS2 +#define OSCS1_OSCS1 oscs1.bit._OSCS1 +#define OSCS1_OSCS0 oscs1.bit._OSCS0 +__IO_EXTERN OSCC2STR oscc2; +#define OSCC2 oscc2.byte +#define OSCC2_FCI oscc2.bit._FCI +#define OSCC2_RFBEN oscc2.bit._RFBEN +#define OSCC2_OSCR oscc2.bit._OSCR +__IO_EXTERN OSCS2STR oscs2; +#define OSCS2 oscs2.byte +#define OSCS2_OSCS7 oscs2.bit._OSCS7 +#define OSCS2_OSCS6 oscs2.bit._OSCS6 +#define OSCS2_OSCS5 oscs2.bit._OSCS5 +#define OSCS2_OSCS4 oscs2.bit._OSCS4 +#define OSCS2_OSCS3 oscs2.bit._OSCS3 +#define OSCS2_OSCS2 oscs2.bit._OSCS2 +#define OSCS2_OSCS1 oscs2.bit._OSCS1 +#define OSCS2_OSCS0 oscs2.bit._OSCS0 +__IO_EXTERN PORTENSTR porten; /* Port Input Enable Control */ +#define PORTEN porten.byte +#define PORTEN_CPORTEN porten.bit._CPORTEN +#define PORTEN_GPORTEN porten.bit._GPORTEN +__IO_EXTERN WTCERSTR wtcer; /* Real Time Clock (Watch Timer) */ +#define WTCER wtcer.byte +#define WTCER_INTE4 wtcer.bit._INTE4 +#define WTCER_INT4 wtcer.bit._INT4 +__IO_EXTERN WTCRSTR wtcr; +#define WTCR wtcr.word +#define WTCR_INTE3 wtcr.bit._INTE3 +#define WTCR_INT3 wtcr.bit._INT3 +#define WTCR_INTE2 wtcr.bit._INTE2 +#define WTCR_INT2 wtcr.bit._INT2 +#define WTCR_INTE1 wtcr.bit._INTE1 +#define WTCR_INT1 wtcr.bit._INT1 +#define WTCR_INTE0 wtcr.bit._INTE0 +#define WTCR_INT0 wtcr.bit._INT0 +#define WTCR_RUN wtcr.bit._RUN +#define WTCR_UPDT wtcr.bit._UPDT +#define WTCR_ST wtcr.bit._ST +__IO_EXTERN WTBRSTR wtbr; +#define WTBR wtbr.lword +#define WTBR_D20 wtbr.bit._D20 +#define WTBR_D19 wtbr.bit._D19 +#define WTBR_D18 wtbr.bit._D18 +#define WTBR_D17 wtbr.bit._D17 +#define WTBR_D16 wtbr.bit._D16 +#define WTBR_D15 wtbr.bit._D15 +#define WTBR_D14 wtbr.bit._D14 +#define WTBR_D13 wtbr.bit._D13 +#define WTBR_D12 wtbr.bit._D12 +#define WTBR_D11 wtbr.bit._D11 +#define WTBR_D10 wtbr.bit._D10 +#define WTBR_D9 wtbr.bit._D9 +#define WTBR_D8 wtbr.bit._D8 +#define WTBR_D7 wtbr.bit._D7 +#define WTBR_D6 wtbr.bit._D6 +#define WTBR_D5 wtbr.bit._D5 +#define WTBR_D4 wtbr.bit._D4 +#define WTBR_D3 wtbr.bit._D3 +#define WTBR_D2 wtbr.bit._D2 +#define WTBR_D1 wtbr.bit._D1 +#define WTBR_D0 wtbr.bit._D0 +__IO_EXTERN WTHRSTR wthr; +#define WTHR wthr.byte +#define WTHR_H4 wthr.bit._H4 +#define WTHR_H3 wthr.bit._H3 +#define WTHR_H2 wthr.bit._H2 +#define WTHR_H1 wthr.bit._H1 +#define WTHR_H0 wthr.bit._H0 +__IO_EXTERN WTMRSTR wtmr; +#define WTMR wtmr.byte +#define WTMR_M5 wtmr.bit._M5 +#define WTMR_M4 wtmr.bit._M4 +#define WTMR_M3 wtmr.bit._M3 +#define WTMR_M2 wtmr.bit._M2 +#define WTMR_M1 wtmr.bit._M1 +#define WTMR_M0 wtmr.bit._M0 +__IO_EXTERN WTSRSTR wtsr; +#define WTSR wtsr.byte +#define WTSR_S5 wtsr.bit._S5 +#define WTSR_S4 wtsr.bit._S4 +#define WTSR_S3 wtsr.bit._S3 +#define WTSR_S2 wtsr.bit._S2 +#define WTSR_S1 wtsr.bit._S1 +#define WTSR_S0 wtsr.bit._S0 +__IO_EXTERN IO_BYTE csvtr; /* Clock-Supervisor / Selecor / Monitor */ +#define CSVTR csvtr +__IO_EXTERN CSVCRSTR csvcr; +#define CSVCR csvcr.byte +#define CSVCR_SCKS csvcr.bit._SCKS +#define CSVCR_MM csvcr.bit._MM +#define CSVCR_SM csvcr.bit._SM +#define CSVCR_RCE csvcr.bit._RCE +#define CSVCR_MSVE csvcr.bit._MSVE +#define CSVCR_SSVE csvcr.bit._SSVE +#define CSVCR_SRST csvcr.bit._SRST +#define CSVCR_OUTE csvcr.bit._OUTE +__IO_EXTERN CSCFGSTR cscfg; +#define CSCFG cscfg.byte +#define CSCFG_EDSUEN cscfg.bit._EDSUEN +#define CSCFG_PLLLOCK cscfg.bit._PLLLOCK +#define CSCFG_RCSEL cscfg.bit._RCSEL +#define CSCFG_MONCKI cscfg.bit._MONCKI +#define CSCFG_CSC3 cscfg.bit._CSC3 +#define CSCFG_CSC2 cscfg.bit._CSC2 +#define CSCFG_CSC1 cscfg.bit._CSC1 +#define CSCFG_CSC0 cscfg.bit._CSC0 +#define CSCFG_CSC cscfg.bitc._CSC +__IO_EXTERN CMCFGSTR cmcfg; +#define CMCFG cmcfg.byte +#define CMCFG_CMPRE3 cmcfg.bit._CMPRE3 +#define CMCFG_CMPRE2 cmcfg.bit._CMPRE2 +#define CMCFG_CMPRE1 cmcfg.bit._CMPRE1 +#define CMCFG_CMPRE0 cmcfg.bit._CMPRE0 +#define CMCFG_CMSEL3 cmcfg.bit._CMSEL3 +#define CMCFG_CMSEL2 cmcfg.bit._CMSEL2 +#define CMCFG_CMSEL1 cmcfg.bit._CMSEL1 +#define CMCFG_CMSEL0 cmcfg.bit._CMSEL0 +#define CMCFG_CMPRE cmcfg.bitc._CMPRE +#define CMCFG_CMSEL cmcfg.bitc._CMSEL +__IO_EXTERN CUCRSTR cucr; /* Calibration Unit of Sub Oszillation */ +#define CUCR cucr.word +#define CUCR_STRT cucr.bit._STRT +#define CUCR_INT cucr.bit._INT +#define CUCR_INTEN cucr.bit._INTEN +__IO_EXTERN CUTDSTR cutd; +#define CUTD cutd.word +#define CUTD_TDD15 cutd.bit._TDD15 +#define CUTD_TDD14 cutd.bit._TDD14 +#define CUTD_TDD13 cutd.bit._TDD13 +#define CUTD_TDD12 cutd.bit._TDD12 +#define CUTD_TDD11 cutd.bit._TDD11 +#define CUTD_TDD10 cutd.bit._TDD10 +#define CUTD_TDD9 cutd.bit._TDD9 +#define CUTD_TDD8 cutd.bit._TDD8 +#define CUTD_TDD7 cutd.bit._TDD7 +#define CUTD_TDD6 cutd.bit._TDD6 +#define CUTD_TDD5 cutd.bit._TDD5 +#define CUTD_TDD4 cutd.bit._TDD4 +#define CUTD_TDD3 cutd.bit._TDD3 +#define CUTD_TDD2 cutd.bit._TDD2 +#define CUTD_TDD1 cutd.bit._TDD1 +#define CUTD_TDD0 cutd.bit._TDD0 +__IO_EXTERN CUTR1STR cutr1; +#define CUTR1 cutr1.word +#define CUTR1_TDR23 cutr1.bit._TDR23 +#define CUTR1_TDR22 cutr1.bit._TDR22 +#define CUTR1_TDR21 cutr1.bit._TDR21 +#define CUTR1_TDR20 cutr1.bit._TDR20 +#define CUTR1_TDR19 cutr1.bit._TDR19 +#define CUTR1_TDR18 cutr1.bit._TDR18 +#define CUTR1_TDR17 cutr1.bit._TDR17 +#define CUTR1_TDR16 cutr1.bit._TDR16 +__IO_EXTERN CUTR2STR cutr2; +#define CUTR2 cutr2.word +#define CUTR2_TDR15 cutr2.bit._TDR15 +#define CUTR2_TDR14 cutr2.bit._TDR14 +#define CUTR2_TDR13 cutr2.bit._TDR13 +#define CUTR2_TDR12 cutr2.bit._TDR12 +#define CUTR2_TDR11 cutr2.bit._TDR11 +#define CUTR2_TDR10 cutr2.bit._TDR10 +#define CUTR2_TDR9 cutr2.bit._TDR9 +#define CUTR2_TDR8 cutr2.bit._TDR8 +#define CUTR2_TDR7 cutr2.bit._TDR7 +#define CUTR2_TDR6 cutr2.bit._TDR6 +#define CUTR2_TDR5 cutr2.bit._TDR5 +#define CUTR2_TDR4 cutr2.bit._TDR4 +#define CUTR2_TDR3 cutr2.bit._TDR3 +#define CUTR2_TDR2 cutr2.bit._TDR2 +#define CUTR2_TDR1 cutr2.bit._TDR1 +#define CUTR2_TDR0 cutr2.bit._TDR0 +__IO_EXTERN CMPRSTR cmpr; /* Clock Modulator */ +#define CMPR cmpr.word +#define CMPR_MP13 cmpr.bit._MP13 +#define CMPR_MP12 cmpr.bit._MP12 +#define CMPR_MP11 cmpr.bit._MP11 +#define CMPR_MP10 cmpr.bit._MP10 +#define CMPR_MP9 cmpr.bit._MP9 +#define CMPR_MP8 cmpr.bit._MP8 +#define CMPR_MP7 cmpr.bit._MP7 +#define CMPR_MP6 cmpr.bit._MP6 +#define CMPR_MP5 cmpr.bit._MP5 +#define CMPR_MP4 cmpr.bit._MP4 +#define CMPR_MP3 cmpr.bit._MP3 +#define CMPR_MP2 cmpr.bit._MP2 +#define CMPR_MP1 cmpr.bit._MP1 +#define CMPR_MP0 cmpr.bit._MP0 +__IO_EXTERN CMCRSTR cmcr; +#define CMCR cmcr.byte +#define CMCR_FMODRUN cmcr.bit._FMODRUN +#define CMCR_FMOD cmcr.bit._FMOD +#define CMCR_PDX cmcr.bit._PDX +__IO_EXTERN IO_WORD cmt1; +#define CMT1 cmt1 +__IO_EXTERN IO_WORD cmt2; +#define CMT2 cmt2 +__IO_EXTERN CANPRESTR canpre; /* CAN clock control */ +#define CANPRE canpre.byte +#define CANPRE_CPCKS1 canpre.bit._CPCKS1 +#define CANPRE_CPCKS0 canpre.bit._CPCKS0 +#define CANPRE_DVC3 canpre.bit._DVC3 +#define CANPRE_DVC2 canpre.bit._DVC2 +#define CANPRE_DVC1 canpre.bit._DVC1 +#define CANPRE_DVC0 canpre.bit._DVC0 +#define CANPRE_CPCKS canpre.bitc._CPCKS +#define CANPRE_DVC canpre.bitc._DVC +__IO_EXTERN CANCKDSTR canckd; +#define CANCKD canckd.byte +#define CANCKD_CANCKD5 canckd.bit._CANCKD5 +#define CANCKD_CANCKD4 canckd.bit._CANCKD4 +#define CANCKD_CANCKD3 canckd.bit._CANCKD3 +#define CANCKD_CANCKD2 canckd.bit._CANCKD2 +#define CANCKD_CANCKD1 canckd.bit._CANCKD1 +#define CANCKD_CANCKD0 canckd.bit._CANCKD0 +__IO_EXTERN LVSELSTR lvsel; /* LV Detection / Hardware-Watchdog */ +#define LVSEL lvsel.byte +#define LVSEL_LVESEL3 lvsel.bit._LVESEL3 +#define LVSEL_LVESEL2 lvsel.bit._LVESEL2 +#define LVSEL_LVESEL1 lvsel.bit._LVESEL1 +#define LVSEL_LVESEL0 lvsel.bit._LVESEL0 +#define LVSEL_LVISEL3 lvsel.bit._LVISEL3 +#define LVSEL_LVISEL2 lvsel.bit._LVISEL2 +#define LVSEL_LVISEL1 lvsel.bit._LVISEL1 +#define LVSEL_LVISEL0 lvsel.bit._LVISEL0 +#define LVSEL_LVESEL lvsel.bitc._LVESEL +#define LVSEL_LVISEL lvsel.bitc._LVISEL +__IO_EXTERN LVDETSTR lvdet; +#define LVDET lvdet.byte +#define LVDET_LVSEL lvdet.bit._LVSEL +#define LVDET_LVEPD lvdet.bit._LVEPD +#define LVDET_LVIPD lvdet.bit._LVIPD +#define LVDET_LVREN lvdet.bit._LVREN +#define LVDET_LVIEN lvdet.bit._LVIEN +#define LVDET_LVIRQ lvdet.bit._LVIRQ +__IO_EXTERN HWWDESTR hwwde; +#define HWWDE hwwde.byte +#define HWWDE_ED1 hwwde.bit._ED1 +#define HWWDE_ED0 hwwde.bit._ED0 +#define HWWDE_ED hwwde.bitc._ED +__IO_EXTERN HWWDSTR hwwd; +#define HWWD hwwd.byte +#define HWWD_CL hwwd.bit._CL +#define HWWD_CPUF hwwd.bit._CPUF +__IO_EXTERN OSCRHSTR oscrh; /* Main-/Sub-Oscillatio Stabilization Timer */ +#define OSCRH oscrh.byte +#define OSCRH_WIF oscrh.bit._WIF +#define OSCRH_WIE oscrh.bit._WIE +#define OSCRH_WEN oscrh.bit._WEN +#define OSCRH_WS1 oscrh.bit._WS1 +#define OSCRH_WS0 oscrh.bit._WS0 +#define OSCRH_WCL oscrh.bit._WCL +#define OSCRH_WS oscrh.bitc._WS +__IO_EXTERN IO_BYTE oscrl; +#define OSCRL oscrl +__IO_EXTERN WPCRHSTR wpcrh; +#define WPCRH wpcrh.byte +#define WPCRH_WIF wpcrh.bit._WIF +#define WPCRH_WIE wpcrh.bit._WIE +#define WPCRH_WEN wpcrh.bit._WEN +#define WPCRH_WS1 wpcrh.bit._WS1 +#define WPCRH_WS0 wpcrh.bit._WS0 +#define WPCRH_WCL wpcrh.bit._WCL +#define WPCRH_WS wpcrh.bitc._WS +__IO_EXTERN IO_BYTE wpcrl; +#define WPCRL wpcrl +__IO_EXTERN OSCCRSTR osccr; /* Main-/Sub-Oscillatio Standby Control */ +#define OSCCR osccr.byte +#define OSCCR_OSCDS1 osccr.bit._OSCDS1 +__IO_EXTERN REGSELSTR regsel; +#define REGSEL regsel.byte +#define REGSEL_FLASHSEL regsel.bit._FLASHSEL +#define REGSEL_MAINSEL regsel.bit._MAINSEL +#define REGSEL_SUBSEL3 regsel.bit._SUBSEL3 +#define REGSEL_SUBSEL2 regsel.bit._SUBSEL2 +#define REGSEL_SUBSEL1 regsel.bit._SUBSEL1 +#define REGSEL_SUBSEL0 regsel.bit._SUBSEL0 +#define REGSEL_SUBSEL regsel.bitc._SUBSEL +__IO_EXTERN REGCTRSTR regctr; +#define REGCTR regctr.byte +#define REGCTR_MSTBO regctr.bit._MSTBO +#define REGCTR_MAINKPEN regctr.bit._MAINKPEN +#define REGCTR_MAINDSBL regctr.bit._MAINDSBL +__IO_EXTERN MODRSTR modr; /* Mode Register */ +#define MODR modr.byte +#define MODR_ROMA modr.bit._ROMA +#define MODR_WTH1 modr.bit._WTH1 +#define MODR_WTH0 modr.bit._WTH0 +#define MODR_WTH modr.bitc._WTH +__IO_EXTERN PDRD14STR pdrd14; /* R-bus Port Data Direct Read Register */ +#define PDRD14 pdrd14.byte +#define PDRD14_D7 pdrd14.bit._D7 +#define PDRD14_D6 pdrd14.bit._D6 +#define PDRD14_D5 pdrd14.bit._D5 +#define PDRD14_D4 pdrd14.bit._D4 +#define PDRD14_D3 pdrd14.bit._D3 +#define PDRD14_D2 pdrd14.bit._D2 +#define PDRD14_D1 pdrd14.bit._D1 +#define PDRD14_D0 pdrd14.bit._D0 +__IO_EXTERN PDRD15STR pdrd15; +#define PDRD15 pdrd15.byte +#define PDRD15_D7 pdrd15.bit._D7 +#define PDRD15_D6 pdrd15.bit._D6 +#define PDRD15_D5 pdrd15.bit._D5 +#define PDRD15_D4 pdrd15.bit._D4 +#define PDRD15_D3 pdrd15.bit._D3 +#define PDRD15_D2 pdrd15.bit._D2 +#define PDRD15_D1 pdrd15.bit._D1 +#define PDRD15_D0 pdrd15.bit._D0 +__IO_EXTERN PDRD16STR pdrd16; +#define PDRD16 pdrd16.byte +#define PDRD16_D7 pdrd16.bit._D7 +#define PDRD16_D6 pdrd16.bit._D6 +#define PDRD16_D5 pdrd16.bit._D5 +#define PDRD16_D4 pdrd16.bit._D4 +#define PDRD16_D3 pdrd16.bit._D3 +#define PDRD16_D2 pdrd16.bit._D2 +#define PDRD16_D1 pdrd16.bit._D1 +#define PDRD16_D0 pdrd16.bit._D0 +__IO_EXTERN PDRD17STR pdrd17; +#define PDRD17 pdrd17.byte +#define PDRD17_D7 pdrd17.bit._D7 +#define PDRD17_D6 pdrd17.bit._D6 +#define PDRD17_D5 pdrd17.bit._D5 +#define PDRD17_D4 pdrd17.bit._D4 +#define PDRD17_D3 pdrd17.bit._D3 +#define PDRD17_D2 pdrd17.bit._D2 +#define PDRD17_D1 pdrd17.bit._D1 +#define PDRD17_D0 pdrd17.bit._D0 +__IO_EXTERN PDRD18STR pdrd18; +#define PDRD18 pdrd18.byte +#define PDRD18_D6 pdrd18.bit._D6 +#define PDRD18_D2 pdrd18.bit._D2 +__IO_EXTERN PDRD19STR pdrd19; +#define PDRD19 pdrd19.byte +#define PDRD19_D6 pdrd19.bit._D6 +#define PDRD19_D2 pdrd19.bit._D2 +#define PDRD19_D1 pdrd19.bit._D1 +#define PDRD19_D0 pdrd19.bit._D0 +__IO_EXTERN PDRD20STR pdrd20; +#define PDRD20 pdrd20.byte +#define PDRD20_D7 pdrd20.bit._D7 +#define PDRD20_D6 pdrd20.bit._D6 +#define PDRD20_D5 pdrd20.bit._D5 +#define PDRD20_D4 pdrd20.bit._D4 +#define PDRD20_D3 pdrd20.bit._D3 +#define PDRD20_D2 pdrd20.bit._D2 +#define PDRD20_D1 pdrd20.bit._D1 +#define PDRD20_D0 pdrd20.bit._D0 +__IO_EXTERN PDRD21STR pdrd21; +#define PDRD21 pdrd21.byte +#define PDRD21_D7 pdrd21.bit._D7 +#define PDRD21_D6 pdrd21.bit._D6 +#define PDRD21_D5 pdrd21.bit._D5 +#define PDRD21_D4 pdrd21.bit._D4 +#define PDRD21_D3 pdrd21.bit._D3 +#define PDRD21_D2 pdrd21.bit._D2 +#define PDRD21_D1 pdrd21.bit._D1 +#define PDRD21_D0 pdrd21.bit._D0 +__IO_EXTERN PDRD22STR pdrd22; +#define PDRD22 pdrd22.byte +#define PDRD22_D5 pdrd22.bit._D5 +#define PDRD22_D4 pdrd22.bit._D4 +#define PDRD22_D1 pdrd22.bit._D1 +#define PDRD22_D0 pdrd22.bit._D0 +__IO_EXTERN PDRD24STR pdrd24; +#define PDRD24 pdrd24.byte +#define PDRD24_D7 pdrd24.bit._D7 +#define PDRD24_D6 pdrd24.bit._D6 +#define PDRD24_D5 pdrd24.bit._D5 +#define PDRD24_D4 pdrd24.bit._D4 +#define PDRD24_D3 pdrd24.bit._D3 +#define PDRD24_D2 pdrd24.bit._D2 +#define PDRD24_D1 pdrd24.bit._D1 +#define PDRD24_D0 pdrd24.bit._D0 +__IO_EXTERN PDRD26STR pdrd26; +#define PDRD26 pdrd26.byte +#define PDRD26_D1 pdrd26.bit._D1 +#define PDRD26_D0 pdrd26.bit._D0 +__IO_EXTERN PDRD27STR pdrd27; +#define PDRD27 pdrd27.byte +#define PDRD27_D7 pdrd27.bit._D7 +#define PDRD27_D6 pdrd27.bit._D6 +#define PDRD27_D5 pdrd27.bit._D5 +#define PDRD27_D4 pdrd27.bit._D4 +#define PDRD27_D3 pdrd27.bit._D3 +#define PDRD27_D2 pdrd27.bit._D2 +#define PDRD27_D1 pdrd27.bit._D1 +#define PDRD27_D0 pdrd27.bit._D0 +__IO_EXTERN PDRD28STR pdrd28; +#define PDRD28 pdrd28.byte +#define PDRD28_D7 pdrd28.bit._D7 +#define PDRD28_D6 pdrd28.bit._D6 +#define PDRD28_D5 pdrd28.bit._D5 +#define PDRD28_D4 pdrd28.bit._D4 +#define PDRD28_D3 pdrd28.bit._D3 +#define PDRD28_D2 pdrd28.bit._D2 +#define PDRD28_D1 pdrd28.bit._D1 +#define PDRD28_D0 pdrd28.bit._D0 +__IO_EXTERN PDRD29STR pdrd29; +#define PDRD29 pdrd29.byte +#define PDRD29_D7 pdrd29.bit._D7 +#define PDRD29_D6 pdrd29.bit._D6 +#define PDRD29_D5 pdrd29.bit._D5 +#define PDRD29_D4 pdrd29.bit._D4 +#define PDRD29_D3 pdrd29.bit._D3 +#define PDRD29_D2 pdrd29.bit._D2 +#define PDRD29_D1 pdrd29.bit._D1 +#define PDRD29_D0 pdrd29.bit._D0 +__IO_EXTERN DDR14STR ddr14; /* R-bus Port Direction Register */ +#define DDR14 ddr14.byte +#define DDR14_D7 ddr14.bit._D7 +#define DDR14_D6 ddr14.bit._D6 +#define DDR14_D5 ddr14.bit._D5 +#define DDR14_D4 ddr14.bit._D4 +#define DDR14_D3 ddr14.bit._D3 +#define DDR14_D2 ddr14.bit._D2 +#define DDR14_D1 ddr14.bit._D1 +#define DDR14_D0 ddr14.bit._D0 +__IO_EXTERN DDR15STR ddr15; +#define DDR15 ddr15.byte +#define DDR15_D7 ddr15.bit._D7 +#define DDR15_D6 ddr15.bit._D6 +#define DDR15_D5 ddr15.bit._D5 +#define DDR15_D4 ddr15.bit._D4 +#define DDR15_D3 ddr15.bit._D3 +#define DDR15_D2 ddr15.bit._D2 +#define DDR15_D1 ddr15.bit._D1 +#define DDR15_D0 ddr15.bit._D0 +__IO_EXTERN DDR16STR ddr16; +#define DDR16 ddr16.byte +#define DDR16_D7 ddr16.bit._D7 +#define DDR16_D6 ddr16.bit._D6 +#define DDR16_D5 ddr16.bit._D5 +#define DDR16_D4 ddr16.bit._D4 +#define DDR16_D3 ddr16.bit._D3 +#define DDR16_D2 ddr16.bit._D2 +#define DDR16_D1 ddr16.bit._D1 +#define DDR16_D0 ddr16.bit._D0 +__IO_EXTERN DDR17STR ddr17; +#define DDR17 ddr17.byte +#define DDR17_D7 ddr17.bit._D7 +#define DDR17_D6 ddr17.bit._D6 +#define DDR17_D5 ddr17.bit._D5 +#define DDR17_D4 ddr17.bit._D4 +#define DDR17_D3 ddr17.bit._D3 +#define DDR17_D2 ddr17.bit._D2 +#define DDR17_D1 ddr17.bit._D1 +#define DDR17_D0 ddr17.bit._D0 +__IO_EXTERN DDR18STR ddr18; +#define DDR18 ddr18.byte +#define DDR18_D6 ddr18.bit._D6 +#define DDR18_D2 ddr18.bit._D2 +__IO_EXTERN DDR19STR ddr19; +#define DDR19 ddr19.byte +#define DDR19_D6 ddr19.bit._D6 +#define DDR19_D2 ddr19.bit._D2 +#define DDR19_D1 ddr19.bit._D1 +#define DDR19_D0 ddr19.bit._D0 +__IO_EXTERN DDR20STR ddr20; +#define DDR20 ddr20.byte +#define DDR20_D7 ddr20.bit._D7 +#define DDR20_D6 ddr20.bit._D6 +#define DDR20_D5 ddr20.bit._D5 +#define DDR20_D4 ddr20.bit._D4 +#define DDR20_D3 ddr20.bit._D3 +#define DDR20_D2 ddr20.bit._D2 +#define DDR20_D1 ddr20.bit._D1 +#define DDR20_D0 ddr20.bit._D0 +__IO_EXTERN DDR21STR ddr21; +#define DDR21 ddr21.byte +#define DDR21_D7 ddr21.bit._D7 +#define DDR21_D6 ddr21.bit._D6 +#define DDR21_D5 ddr21.bit._D5 +#define DDR21_D4 ddr21.bit._D4 +#define DDR21_D3 ddr21.bit._D3 +#define DDR21_D2 ddr21.bit._D2 +#define DDR21_D1 ddr21.bit._D1 +#define DDR21_D0 ddr21.bit._D0 +__IO_EXTERN DDR22STR ddr22; +#define DDR22 ddr22.byte +#define DDR22_D5 ddr22.bit._D5 +#define DDR22_D4 ddr22.bit._D4 +#define DDR22_D1 ddr22.bit._D1 +#define DDR22_D0 ddr22.bit._D0 +__IO_EXTERN DDR24STR ddr24; +#define DDR24 ddr24.byte +#define DDR24_D7 ddr24.bit._D7 +#define DDR24_D6 ddr24.bit._D6 +#define DDR24_D5 ddr24.bit._D5 +#define DDR24_D4 ddr24.bit._D4 +#define DDR24_D3 ddr24.bit._D3 +#define DDR24_D2 ddr24.bit._D2 +#define DDR24_D1 ddr24.bit._D1 +#define DDR24_D0 ddr24.bit._D0 +__IO_EXTERN DDR26STR ddr26; +#define DDR26 ddr26.byte +#define DDR26_D1 ddr26.bit._D1 +#define DDR26_D0 ddr26.bit._D0 +__IO_EXTERN DDR27STR ddr27; +#define DDR27 ddr27.byte +#define DDR27_D7 ddr27.bit._D7 +#define DDR27_D6 ddr27.bit._D6 +#define DDR27_D5 ddr27.bit._D5 +#define DDR27_D4 ddr27.bit._D4 +#define DDR27_D3 ddr27.bit._D3 +#define DDR27_D2 ddr27.bit._D2 +#define DDR27_D1 ddr27.bit._D1 +#define DDR27_D0 ddr27.bit._D0 +__IO_EXTERN DDR28STR ddr28; +#define DDR28 ddr28.byte +#define DDR28_D7 ddr28.bit._D7 +#define DDR28_D6 ddr28.bit._D6 +#define DDR28_D5 ddr28.bit._D5 +#define DDR28_D4 ddr28.bit._D4 +#define DDR28_D3 ddr28.bit._D3 +#define DDR28_D2 ddr28.bit._D2 +#define DDR28_D1 ddr28.bit._D1 +#define DDR28_D0 ddr28.bit._D0 +__IO_EXTERN DDR29STR ddr29; +#define DDR29 ddr29.byte +#define DDR29_D7 ddr29.bit._D7 +#define DDR29_D6 ddr29.bit._D6 +#define DDR29_D5 ddr29.bit._D5 +#define DDR29_D4 ddr29.bit._D4 +#define DDR29_D3 ddr29.bit._D3 +#define DDR29_D2 ddr29.bit._D2 +#define DDR29_D1 ddr29.bit._D1 +#define DDR29_D0 ddr29.bit._D0 +__IO_EXTERN PFR14STR pfr14; /* R-bus Port Function Register */ +#define PFR14 pfr14.byte +#define PFR14_D7 pfr14.bit._D7 +#define PFR14_D6 pfr14.bit._D6 +#define PFR14_D5 pfr14.bit._D5 +#define PFR14_D4 pfr14.bit._D4 +#define PFR14_D3 pfr14.bit._D3 +#define PFR14_D2 pfr14.bit._D2 +#define PFR14_D1 pfr14.bit._D1 +#define PFR14_D0 pfr14.bit._D0 +__IO_EXTERN PFR15STR pfr15; +#define PFR15 pfr15.byte +#define PFR15_D7 pfr15.bit._D7 +#define PFR15_D6 pfr15.bit._D6 +#define PFR15_D5 pfr15.bit._D5 +#define PFR15_D4 pfr15.bit._D4 +#define PFR15_D3 pfr15.bit._D3 +#define PFR15_D2 pfr15.bit._D2 +#define PFR15_D1 pfr15.bit._D1 +#define PFR15_D0 pfr15.bit._D0 +__IO_EXTERN PFR16STR pfr16; +#define PFR16 pfr16.byte +#define PFR16_D7 pfr16.bit._D7 +#define PFR16_D6 pfr16.bit._D6 +#define PFR16_D5 pfr16.bit._D5 +#define PFR16_D4 pfr16.bit._D4 +#define PFR16_D3 pfr16.bit._D3 +#define PFR16_D2 pfr16.bit._D2 +#define PFR16_D1 pfr16.bit._D1 +#define PFR16_D0 pfr16.bit._D0 +__IO_EXTERN PFR17STR pfr17; +#define PFR17 pfr17.byte +#define PFR17_D7 pfr17.bit._D7 +#define PFR17_D6 pfr17.bit._D6 +#define PFR17_D5 pfr17.bit._D5 +#define PFR17_D4 pfr17.bit._D4 +#define PFR17_D3 pfr17.bit._D3 +#define PFR17_D2 pfr17.bit._D2 +#define PFR17_D1 pfr17.bit._D1 +#define PFR17_D0 pfr17.bit._D0 +__IO_EXTERN PFR18STR pfr18; +#define PFR18 pfr18.byte +#define PFR18_D6 pfr18.bit._D6 +#define PFR18_D2 pfr18.bit._D2 +__IO_EXTERN PFR19STR pfr19; +#define PFR19 pfr19.byte +#define PFR19_D6 pfr19.bit._D6 +#define PFR19_D2 pfr19.bit._D2 +#define PFR19_D1 pfr19.bit._D1 +#define PFR19_D0 pfr19.bit._D0 +__IO_EXTERN PFR20STR pfr20; +#define PFR20 pfr20.byte +#define PFR20_D7 pfr20.bit._D7 +#define PFR20_D6 pfr20.bit._D6 +#define PFR20_D5 pfr20.bit._D5 +#define PFR20_D4 pfr20.bit._D4 +#define PFR20_D3 pfr20.bit._D3 +#define PFR20_D2 pfr20.bit._D2 +#define PFR20_D1 pfr20.bit._D1 +#define PFR20_D0 pfr20.bit._D0 +__IO_EXTERN PFR21STR pfr21; +#define PFR21 pfr21.byte +#define PFR21_D7 pfr21.bit._D7 +#define PFR21_D6 pfr21.bit._D6 +#define PFR21_D5 pfr21.bit._D5 +#define PFR21_D4 pfr21.bit._D4 +#define PFR21_D3 pfr21.bit._D3 +#define PFR21_D2 pfr21.bit._D2 +#define PFR21_D1 pfr21.bit._D1 +#define PFR21_D0 pfr21.bit._D0 +__IO_EXTERN PFR22STR pfr22; +#define PFR22 pfr22.byte +#define PFR22_D5 pfr22.bit._D5 +#define PFR22_D4 pfr22.bit._D4 +#define PFR22_D1 pfr22.bit._D1 +#define PFR22_D0 pfr22.bit._D0 +__IO_EXTERN PFR24STR pfr24; +#define PFR24 pfr24.byte +#define PFR24_D7 pfr24.bit._D7 +#define PFR24_D6 pfr24.bit._D6 +#define PFR24_D5 pfr24.bit._D5 +#define PFR24_D4 pfr24.bit._D4 +#define PFR24_D3 pfr24.bit._D3 +#define PFR24_D2 pfr24.bit._D2 +#define PFR24_D1 pfr24.bit._D1 +#define PFR24_D0 pfr24.bit._D0 +__IO_EXTERN PFR26STR pfr26; +#define PFR26 pfr26.byte +#define PFR26_D1 pfr26.bit._D1 +#define PFR26_D0 pfr26.bit._D0 +__IO_EXTERN PFR27STR pfr27; +#define PFR27 pfr27.byte +#define PFR27_D7 pfr27.bit._D7 +#define PFR27_D6 pfr27.bit._D6 +#define PFR27_D5 pfr27.bit._D5 +#define PFR27_D4 pfr27.bit._D4 +#define PFR27_D3 pfr27.bit._D3 +#define PFR27_D2 pfr27.bit._D2 +#define PFR27_D1 pfr27.bit._D1 +#define PFR27_D0 pfr27.bit._D0 +__IO_EXTERN PFR28STR pfr28; +#define PFR28 pfr28.byte +#define PFR28_D7 pfr28.bit._D7 +#define PFR28_D6 pfr28.bit._D6 +#define PFR28_D5 pfr28.bit._D5 +#define PFR28_D4 pfr28.bit._D4 +#define PFR28_D3 pfr28.bit._D3 +#define PFR28_D2 pfr28.bit._D2 +#define PFR28_D1 pfr28.bit._D1 +#define PFR28_D0 pfr28.bit._D0 +__IO_EXTERN PFR29STR pfr29; +#define PFR29 pfr29.byte +#define PFR29_D7 pfr29.bit._D7 +#define PFR29_D6 pfr29.bit._D6 +#define PFR29_D5 pfr29.bit._D5 +#define PFR29_D4 pfr29.bit._D4 +#define PFR29_D3 pfr29.bit._D3 +#define PFR29_D2 pfr29.bit._D2 +#define PFR29_D1 pfr29.bit._D1 +#define PFR29_D0 pfr29.bit._D0 +__IO_EXTERN EPFR14STR epfr14; /* R-bus Port Extra Function Register */ +#define EPFR14 epfr14.byte +#define EPFR14_D7 epfr14.bit._D7 +#define EPFR14_D6 epfr14.bit._D6 +#define EPFR14_D5 epfr14.bit._D5 +#define EPFR14_D4 epfr14.bit._D4 +#define EPFR14_D3 epfr14.bit._D3 +#define EPFR14_D2 epfr14.bit._D2 +#define EPFR14_D1 epfr14.bit._D1 +#define EPFR14_D0 epfr14.bit._D0 +__IO_EXTERN EPFR15STR epfr15; +#define EPFR15 epfr15.byte +#define EPFR15_D7 epfr15.bit._D7 +#define EPFR15_D6 epfr15.bit._D6 +#define EPFR15_D5 epfr15.bit._D5 +#define EPFR15_D4 epfr15.bit._D4 +#define EPFR15_D3 epfr15.bit._D3 +#define EPFR15_D2 epfr15.bit._D2 +#define EPFR15_D1 epfr15.bit._D1 +#define EPFR15_D0 epfr15.bit._D0 +__IO_EXTERN EPFR16STR epfr16; +#define EPFR16 epfr16.byte +#define EPFR16_D7 epfr16.bit._D7 +__IO_EXTERN IO_BYTE epfr17; +#define EPFR17 epfr17 +__IO_EXTERN EPFR18STR epfr18; +#define EPFR18 epfr18.byte +#define EPFR18_D6 epfr18.bit._D6 +#define EPFR18_D2 epfr18.bit._D2 +__IO_EXTERN EPFR19STR epfr19; +#define EPFR19 epfr19.byte +#define EPFR19_D6 epfr19.bit._D6 +#define EPFR19_D2 epfr19.bit._D2 +__IO_EXTERN EPFR20STR epfr20; +#define EPFR20 epfr20.byte +#define EPFR20_D6 epfr20.bit._D6 +#define EPFR20_D2 epfr20.bit._D2 +__IO_EXTERN EPFR21STR epfr21; +#define EPFR21 epfr21.byte +#define EPFR21_D6 epfr21.bit._D6 +#define EPFR21_D2 epfr21.bit._D2 +__IO_EXTERN IO_BYTE epfr22; +#define EPFR22 epfr22 +__IO_EXTERN IO_BYTE epfr24; +#define EPFR24 epfr24 +__IO_EXTERN EPFR26STR epfr26; +#define EPFR26 epfr26.byte +#define EPFR26_D1 epfr26.bit._D1 +#define EPFR26_D0 epfr26.bit._D0 +__IO_EXTERN EPFR27STR epfr27; +#define EPFR27 epfr27.byte +#define EPFR27_D7 epfr27.bit._D7 +#define EPFR27_D6 epfr27.bit._D6 +#define EPFR27_D5 epfr27.bit._D5 +#define EPFR27_D4 epfr27.bit._D4 +#define EPFR27_D3 epfr27.bit._D3 +#define EPFR27_D2 epfr27.bit._D2 +#define EPFR27_D1 epfr27.bit._D1 +#define EPFR27_D0 epfr27.bit._D0 +__IO_EXTERN IO_BYTE epfr29; +#define EPFR29 epfr29 +__IO_EXTERN PODR14STR podr14; /* R-bus Port Output Drive Select Register */ +#define PODR14 podr14.byte +#define PODR14_D7 podr14.bit._D7 +#define PODR14_D6 podr14.bit._D6 +#define PODR14_D5 podr14.bit._D5 +#define PODR14_D4 podr14.bit._D4 +#define PODR14_D3 podr14.bit._D3 +#define PODR14_D2 podr14.bit._D2 +#define PODR14_D1 podr14.bit._D1 +#define PODR14_D0 podr14.bit._D0 +__IO_EXTERN PODR15STR podr15; +#define PODR15 podr15.byte +#define PODR15_D7 podr15.bit._D7 +#define PODR15_D6 podr15.bit._D6 +#define PODR15_D5 podr15.bit._D5 +#define PODR15_D4 podr15.bit._D4 +#define PODR15_D3 podr15.bit._D3 +#define PODR15_D2 podr15.bit._D2 +#define PODR15_D1 podr15.bit._D1 +#define PODR15_D0 podr15.bit._D0 +__IO_EXTERN PODR16STR podr16; +#define PODR16 podr16.byte +#define PODR16_D7 podr16.bit._D7 +#define PODR16_D6 podr16.bit._D6 +#define PODR16_D5 podr16.bit._D5 +#define PODR16_D4 podr16.bit._D4 +#define PODR16_D3 podr16.bit._D3 +#define PODR16_D2 podr16.bit._D2 +#define PODR16_D1 podr16.bit._D1 +#define PODR16_D0 podr16.bit._D0 +__IO_EXTERN PODR17STR podr17; +#define PODR17 podr17.byte +#define PODR17_D7 podr17.bit._D7 +#define PODR17_D6 podr17.bit._D6 +#define PODR17_D5 podr17.bit._D5 +#define PODR17_D4 podr17.bit._D4 +#define PODR17_D3 podr17.bit._D3 +#define PODR17_D2 podr17.bit._D2 +#define PODR17_D1 podr17.bit._D1 +#define PODR17_D0 podr17.bit._D0 +__IO_EXTERN PODR18STR podr18; +#define PODR18 podr18.byte +#define PODR18_D6 podr18.bit._D6 +#define PODR18_D2 podr18.bit._D2 +__IO_EXTERN PODR19STR podr19; +#define PODR19 podr19.byte +#define PODR19_D6 podr19.bit._D6 +#define PODR19_D2 podr19.bit._D2 +#define PODR19_D1 podr19.bit._D1 +#define PODR19_D0 podr19.bit._D0 +__IO_EXTERN PODR20STR podr20; +#define PODR20 podr20.byte +#define PODR20_D7 podr20.bit._D7 +#define PODR20_D6 podr20.bit._D6 +#define PODR20_D5 podr20.bit._D5 +#define PODR20_D4 podr20.bit._D4 +#define PODR20_D3 podr20.bit._D3 +#define PODR20_D2 podr20.bit._D2 +#define PODR20_D1 podr20.bit._D1 +#define PODR20_D0 podr20.bit._D0 +__IO_EXTERN PODR21STR podr21; +#define PODR21 podr21.byte +#define PODR21_D7 podr21.bit._D7 +#define PODR21_D6 podr21.bit._D6 +#define PODR21_D5 podr21.bit._D5 +#define PODR21_D4 podr21.bit._D4 +#define PODR21_D3 podr21.bit._D3 +#define PODR21_D2 podr21.bit._D2 +#define PODR21_D1 podr21.bit._D1 +#define PODR21_D0 podr21.bit._D0 +__IO_EXTERN PODR22STR podr22; +#define PODR22 podr22.byte +#define PODR22_D5 podr22.bit._D5 +#define PODR22_D4 podr22.bit._D4 +#define PODR22_D1 podr22.bit._D1 +#define PODR22_D0 podr22.bit._D0 +__IO_EXTERN PODR24STR podr24; +#define PODR24 podr24.byte +#define PODR24_D7 podr24.bit._D7 +#define PODR24_D6 podr24.bit._D6 +#define PODR24_D5 podr24.bit._D5 +#define PODR24_D4 podr24.bit._D4 +#define PODR24_D3 podr24.bit._D3 +#define PODR24_D2 podr24.bit._D2 +#define PODR24_D1 podr24.bit._D1 +#define PODR24_D0 podr24.bit._D0 +__IO_EXTERN PODR26STR podr26; +#define PODR26 podr26.byte +#define PODR26_D1 podr26.bit._D1 +#define PODR26_D0 podr26.bit._D0 +__IO_EXTERN PODR27STR podr27; +#define PODR27 podr27.byte +#define PODR27_D7 podr27.bit._D7 +#define PODR27_D6 podr27.bit._D6 +#define PODR27_D5 podr27.bit._D5 +#define PODR27_D4 podr27.bit._D4 +#define PODR27_D3 podr27.bit._D3 +#define PODR27_D2 podr27.bit._D2 +#define PODR27_D1 podr27.bit._D1 +#define PODR27_D0 podr27.bit._D0 +__IO_EXTERN PODR28STR podr28; +#define PODR28 podr28.byte +#define PODR28_D7 podr28.bit._D7 +#define PODR28_D6 podr28.bit._D6 +#define PODR28_D5 podr28.bit._D5 +#define PODR28_D4 podr28.bit._D4 +#define PODR28_D3 podr28.bit._D3 +#define PODR28_D2 podr28.bit._D2 +#define PODR28_D1 podr28.bit._D1 +#define PODR28_D0 podr28.bit._D0 +__IO_EXTERN PODR29STR podr29; +#define PODR29 podr29.byte +#define PODR29_D7 podr29.bit._D7 +#define PODR29_D6 podr29.bit._D6 +#define PODR29_D5 podr29.bit._D5 +#define PODR29_D4 podr29.bit._D4 +#define PODR29_D3 podr29.bit._D3 +#define PODR29_D2 podr29.bit._D2 +#define PODR29_D1 podr29.bit._D1 +#define PODR29_D0 podr29.bit._D0 +__IO_EXTERN PILR14STR pilr14; /* R-bus Port Input Level Select Register */ +#define PILR14 pilr14.byte +#define PILR14_D7 pilr14.bit._D7 +#define PILR14_D6 pilr14.bit._D6 +#define PILR14_D5 pilr14.bit._D5 +#define PILR14_D4 pilr14.bit._D4 +#define PILR14_D3 pilr14.bit._D3 +#define PILR14_D2 pilr14.bit._D2 +#define PILR14_D1 pilr14.bit._D1 +#define PILR14_D0 pilr14.bit._D0 +__IO_EXTERN PILR15STR pilr15; +#define PILR15 pilr15.byte +#define PILR15_D7 pilr15.bit._D7 +#define PILR15_D6 pilr15.bit._D6 +#define PILR15_D5 pilr15.bit._D5 +#define PILR15_D4 pilr15.bit._D4 +#define PILR15_D3 pilr15.bit._D3 +#define PILR15_D2 pilr15.bit._D2 +#define PILR15_D1 pilr15.bit._D1 +#define PILR15_D0 pilr15.bit._D0 +__IO_EXTERN PILR16STR pilr16; +#define PILR16 pilr16.byte +#define PILR16_D7 pilr16.bit._D7 +#define PILR16_D6 pilr16.bit._D6 +#define PILR16_D5 pilr16.bit._D5 +#define PILR16_D4 pilr16.bit._D4 +#define PILR16_D3 pilr16.bit._D3 +#define PILR16_D2 pilr16.bit._D2 +#define PILR16_D1 pilr16.bit._D1 +#define PILR16_D0 pilr16.bit._D0 +__IO_EXTERN PILR17STR pilr17; +#define PILR17 pilr17.byte +#define PILR17_D7 pilr17.bit._D7 +#define PILR17_D6 pilr17.bit._D6 +#define PILR17_D5 pilr17.bit._D5 +#define PILR17_D4 pilr17.bit._D4 +#define PILR17_D3 pilr17.bit._D3 +#define PILR17_D2 pilr17.bit._D2 +#define PILR17_D1 pilr17.bit._D1 +#define PILR17_D0 pilr17.bit._D0 +__IO_EXTERN PILR18STR pilr18; +#define PILR18 pilr18.byte +#define PILR18_D6 pilr18.bit._D6 +#define PILR18_D2 pilr18.bit._D2 +__IO_EXTERN PILR19STR pilr19; +#define PILR19 pilr19.byte +#define PILR19_D6 pilr19.bit._D6 +#define PILR19_D2 pilr19.bit._D2 +#define PILR19_D1 pilr19.bit._D1 +#define PILR19_D0 pilr19.bit._D0 +__IO_EXTERN PILR20STR pilr20; +#define PILR20 pilr20.byte +#define PILR20_D7 pilr20.bit._D7 +#define PILR20_D6 pilr20.bit._D6 +#define PILR20_D5 pilr20.bit._D5 +#define PILR20_D4 pilr20.bit._D4 +#define PILR20_D3 pilr20.bit._D3 +#define PILR20_D2 pilr20.bit._D2 +#define PILR20_D1 pilr20.bit._D1 +#define PILR20_D0 pilr20.bit._D0 +__IO_EXTERN PILR21STR pilr21; +#define PILR21 pilr21.byte +#define PILR21_D7 pilr21.bit._D7 +#define PILR21_D6 pilr21.bit._D6 +#define PILR21_D5 pilr21.bit._D5 +#define PILR21_D4 pilr21.bit._D4 +#define PILR21_D3 pilr21.bit._D3 +#define PILR21_D2 pilr21.bit._D2 +#define PILR21_D1 pilr21.bit._D1 +#define PILR21_D0 pilr21.bit._D0 +__IO_EXTERN PILR22STR pilr22; +#define PILR22 pilr22.byte +#define PILR22_D5 pilr22.bit._D5 +#define PILR22_D4 pilr22.bit._D4 +#define PILR22_D1 pilr22.bit._D1 +#define PILR22_D0 pilr22.bit._D0 +__IO_EXTERN PILR24STR pilr24; +#define PILR24 pilr24.byte +#define PILR24_D7 pilr24.bit._D7 +#define PILR24_D6 pilr24.bit._D6 +#define PILR24_D5 pilr24.bit._D5 +#define PILR24_D4 pilr24.bit._D4 +#define PILR24_D3 pilr24.bit._D3 +#define PILR24_D2 pilr24.bit._D2 +#define PILR24_D1 pilr24.bit._D1 +#define PILR24_D0 pilr24.bit._D0 +__IO_EXTERN PILR26STR pilr26; +#define PILR26 pilr26.byte +#define PILR26_D1 pilr26.bit._D1 +#define PILR26_D0 pilr26.bit._D0 +__IO_EXTERN PILR27STR pilr27; +#define PILR27 pilr27.byte +#define PILR27_D7 pilr27.bit._D7 +#define PILR27_D6 pilr27.bit._D6 +#define PILR27_D5 pilr27.bit._D5 +#define PILR27_D4 pilr27.bit._D4 +#define PILR27_D3 pilr27.bit._D3 +#define PILR27_D2 pilr27.bit._D2 +#define PILR27_D1 pilr27.bit._D1 +#define PILR27_D0 pilr27.bit._D0 +__IO_EXTERN PILR28STR pilr28; +#define PILR28 pilr28.byte +#define PILR28_D7 pilr28.bit._D7 +#define PILR28_D6 pilr28.bit._D6 +#define PILR28_D5 pilr28.bit._D5 +#define PILR28_D4 pilr28.bit._D4 +#define PILR28_D3 pilr28.bit._D3 +#define PILR28_D2 pilr28.bit._D2 +#define PILR28_D1 pilr28.bit._D1 +#define PILR28_D0 pilr28.bit._D0 +__IO_EXTERN PILR29STR pilr29; +#define PILR29 pilr29.byte +#define PILR29_D7 pilr29.bit._D7 +#define PILR29_D6 pilr29.bit._D6 +#define PILR29_D5 pilr29.bit._D5 +#define PILR29_D4 pilr29.bit._D4 +#define PILR29_D3 pilr29.bit._D3 +#define PILR29_D2 pilr29.bit._D2 +#define PILR29_D1 pilr29.bit._D1 +#define PILR29_D0 pilr29.bit._D0 +__IO_EXTERN EPILR14STR epilr14; /* R-bus Port Extra Input Level Select Register */ +#define EPILR14 epilr14.byte +#define EPILR14_D7 epilr14.bit._D7 +#define EPILR14_D6 epilr14.bit._D6 +#define EPILR14_D5 epilr14.bit._D5 +#define EPILR14_D4 epilr14.bit._D4 +#define EPILR14_D3 epilr14.bit._D3 +#define EPILR14_D2 epilr14.bit._D2 +#define EPILR14_D1 epilr14.bit._D1 +#define EPILR14_D0 epilr14.bit._D0 +__IO_EXTERN EPILR15STR epilr15; +#define EPILR15 epilr15.byte +#define EPILR15_D7 epilr15.bit._D7 +#define EPILR15_D6 epilr15.bit._D6 +#define EPILR15_D5 epilr15.bit._D5 +#define EPILR15_D4 epilr15.bit._D4 +#define EPILR15_D3 epilr15.bit._D3 +#define EPILR15_D2 epilr15.bit._D2 +#define EPILR15_D1 epilr15.bit._D1 +#define EPILR15_D0 epilr15.bit._D0 +__IO_EXTERN EPILR16STR epilr16; +#define EPILR16 epilr16.byte +#define EPILR16_D7 epilr16.bit._D7 +#define EPILR16_D6 epilr16.bit._D6 +#define EPILR16_D5 epilr16.bit._D5 +#define EPILR16_D4 epilr16.bit._D4 +#define EPILR16_D3 epilr16.bit._D3 +#define EPILR16_D2 epilr16.bit._D2 +#define EPILR16_D1 epilr16.bit._D1 +#define EPILR16_D0 epilr16.bit._D0 +__IO_EXTERN EPILR17STR epilr17; +#define EPILR17 epilr17.byte +#define EPILR17_D7 epilr17.bit._D7 +#define EPILR17_D6 epilr17.bit._D6 +#define EPILR17_D5 epilr17.bit._D5 +#define EPILR17_D4 epilr17.bit._D4 +#define EPILR17_D3 epilr17.bit._D3 +#define EPILR17_D2 epilr17.bit._D2 +#define EPILR17_D1 epilr17.bit._D1 +#define EPILR17_D0 epilr17.bit._D0 +__IO_EXTERN EPILR18STR epilr18; +#define EPILR18 epilr18.byte +#define EPILR18_D6 epilr18.bit._D6 +#define EPILR18_D2 epilr18.bit._D2 +__IO_EXTERN EPILR19STR epilr19; +#define EPILR19 epilr19.byte +#define EPILR19_D6 epilr19.bit._D6 +#define EPILR19_D2 epilr19.bit._D2 +#define EPILR19_D1 epilr19.bit._D1 +#define EPILR19_D0 epilr19.bit._D0 +__IO_EXTERN EPILR20STR epilr20; +#define EPILR20 epilr20.byte +#define EPILR20_D7 epilr20.bit._D7 +#define EPILR20_D6 epilr20.bit._D6 +#define EPILR20_D5 epilr20.bit._D5 +#define EPILR20_D4 epilr20.bit._D4 +#define EPILR20_D3 epilr20.bit._D3 +#define EPILR20_D2 epilr20.bit._D2 +#define EPILR20_D1 epilr20.bit._D1 +#define EPILR20_D0 epilr20.bit._D0 +__IO_EXTERN EPILR21STR epilr21; +#define EPILR21 epilr21.byte +#define EPILR21_D7 epilr21.bit._D7 +#define EPILR21_D6 epilr21.bit._D6 +#define EPILR21_D5 epilr21.bit._D5 +#define EPILR21_D4 epilr21.bit._D4 +#define EPILR21_D3 epilr21.bit._D3 +#define EPILR21_D2 epilr21.bit._D2 +#define EPILR21_D1 epilr21.bit._D1 +#define EPILR21_D0 epilr21.bit._D0 +__IO_EXTERN EPILR22STR epilr22; +#define EPILR22 epilr22.byte +#define EPILR22_D5 epilr22.bit._D5 +#define EPILR22_D4 epilr22.bit._D4 +#define EPILR22_D1 epilr22.bit._D1 +#define EPILR22_D0 epilr22.bit._D0 +__IO_EXTERN EPILR24STR epilr24; +#define EPILR24 epilr24.byte +#define EPILR24_D7 epilr24.bit._D7 +#define EPILR24_D6 epilr24.bit._D6 +#define EPILR24_D5 epilr24.bit._D5 +#define EPILR24_D4 epilr24.bit._D4 +#define EPILR24_D3 epilr24.bit._D3 +#define EPILR24_D2 epilr24.bit._D2 +#define EPILR24_D1 epilr24.bit._D1 +#define EPILR24_D0 epilr24.bit._D0 +__IO_EXTERN EPILR26STR epilr26; +#define EPILR26 epilr26.byte +#define EPILR26_D1 epilr26.bit._D1 +#define EPILR26_D0 epilr26.bit._D0 +__IO_EXTERN EPILR27STR epilr27; +#define EPILR27 epilr27.byte +#define EPILR27_D7 epilr27.bit._D7 +#define EPILR27_D6 epilr27.bit._D6 +#define EPILR27_D5 epilr27.bit._D5 +#define EPILR27_D4 epilr27.bit._D4 +#define EPILR27_D3 epilr27.bit._D3 +#define EPILR27_D2 epilr27.bit._D2 +#define EPILR27_D1 epilr27.bit._D1 +#define EPILR27_D0 epilr27.bit._D0 +__IO_EXTERN EPILR28STR epilr28; +#define EPILR28 epilr28.byte +#define EPILR28_D7 epilr28.bit._D7 +#define EPILR28_D6 epilr28.bit._D6 +#define EPILR28_D5 epilr28.bit._D5 +#define EPILR28_D4 epilr28.bit._D4 +#define EPILR28_D3 epilr28.bit._D3 +#define EPILR28_D2 epilr28.bit._D2 +#define EPILR28_D1 epilr28.bit._D1 +#define EPILR28_D0 epilr28.bit._D0 +__IO_EXTERN EPILR29STR epilr29; +#define EPILR29 epilr29.byte +#define EPILR29_D7 epilr29.bit._D7 +#define EPILR29_D6 epilr29.bit._D6 +#define EPILR29_D5 epilr29.bit._D5 +#define EPILR29_D4 epilr29.bit._D4 +#define EPILR29_D3 epilr29.bit._D3 +#define EPILR29_D2 epilr29.bit._D2 +#define EPILR29_D1 epilr29.bit._D1 +#define EPILR29_D0 epilr29.bit._D0 +__IO_EXTERN PPER14STR pper14; /* R-bus Port Pull-Up/Down Enable Register */ +#define PPER14 pper14.byte +#define PPER14_D7 pper14.bit._D7 +#define PPER14_D6 pper14.bit._D6 +#define PPER14_D5 pper14.bit._D5 +#define PPER14_D4 pper14.bit._D4 +#define PPER14_D3 pper14.bit._D3 +#define PPER14_D2 pper14.bit._D2 +#define PPER14_D1 pper14.bit._D1 +#define PPER14_D0 pper14.bit._D0 +__IO_EXTERN PPER15STR pper15; +#define PPER15 pper15.byte +#define PPER15_D7 pper15.bit._D7 +#define PPER15_D6 pper15.bit._D6 +#define PPER15_D5 pper15.bit._D5 +#define PPER15_D4 pper15.bit._D4 +#define PPER15_D3 pper15.bit._D3 +#define PPER15_D2 pper15.bit._D2 +#define PPER15_D1 pper15.bit._D1 +#define PPER15_D0 pper15.bit._D0 +__IO_EXTERN PPER16STR pper16; +#define PPER16 pper16.byte +#define PPER16_D7 pper16.bit._D7 +#define PPER16_D6 pper16.bit._D6 +#define PPER16_D5 pper16.bit._D5 +#define PPER16_D4 pper16.bit._D4 +#define PPER16_D3 pper16.bit._D3 +#define PPER16_D2 pper16.bit._D2 +#define PPER16_D1 pper16.bit._D1 +#define PPER16_D0 pper16.bit._D0 +__IO_EXTERN PPER17STR pper17; +#define PPER17 pper17.byte +#define PPER17_D7 pper17.bit._D7 +#define PPER17_D6 pper17.bit._D6 +#define PPER17_D5 pper17.bit._D5 +#define PPER17_D4 pper17.bit._D4 +#define PPER17_D3 pper17.bit._D3 +#define PPER17_D2 pper17.bit._D2 +#define PPER17_D1 pper17.bit._D1 +#define PPER17_D0 pper17.bit._D0 +__IO_EXTERN PPER18STR pper18; +#define PPER18 pper18.byte +#define PPER18_D6 pper18.bit._D6 +#define PPER18_D2 pper18.bit._D2 +__IO_EXTERN PPER19STR pper19; +#define PPER19 pper19.byte +#define PPER19_D6 pper19.bit._D6 +#define PPER19_D2 pper19.bit._D2 +#define PPER19_D1 pper19.bit._D1 +#define PPER19_D0 pper19.bit._D0 +__IO_EXTERN PPER20STR pper20; +#define PPER20 pper20.byte +#define PPER20_D7 pper20.bit._D7 +#define PPER20_D6 pper20.bit._D6 +#define PPER20_D5 pper20.bit._D5 +#define PPER20_D4 pper20.bit._D4 +#define PPER20_D3 pper20.bit._D3 +#define PPER20_D2 pper20.bit._D2 +#define PPER20_D1 pper20.bit._D1 +#define PPER20_D0 pper20.bit._D0 +__IO_EXTERN PPER21STR pper21; +#define PPER21 pper21.byte +#define PPER21_D7 pper21.bit._D7 +#define PPER21_D6 pper21.bit._D6 +#define PPER21_D5 pper21.bit._D5 +#define PPER21_D4 pper21.bit._D4 +#define PPER21_D3 pper21.bit._D3 +#define PPER21_D2 pper21.bit._D2 +#define PPER21_D1 pper21.bit._D1 +#define PPER21_D0 pper21.bit._D0 +__IO_EXTERN PPER22STR pper22; +#define PPER22 pper22.byte +#define PPER22_D5 pper22.bit._D5 +#define PPER22_D4 pper22.bit._D4 +#define PPER22_D1 pper22.bit._D1 +#define PPER22_D0 pper22.bit._D0 +__IO_EXTERN PPER24STR pper24; +#define PPER24 pper24.byte +#define PPER24_D7 pper24.bit._D7 +#define PPER24_D6 pper24.bit._D6 +#define PPER24_D5 pper24.bit._D5 +#define PPER24_D4 pper24.bit._D4 +#define PPER24_D3 pper24.bit._D3 +#define PPER24_D2 pper24.bit._D2 +#define PPER24_D1 pper24.bit._D1 +#define PPER24_D0 pper24.bit._D0 +__IO_EXTERN PPER26STR pper26; +#define PPER26 pper26.byte +#define PPER26_D1 pper26.bit._D1 +#define PPER26_D0 pper26.bit._D0 +__IO_EXTERN PPER27STR pper27; +#define PPER27 pper27.byte +#define PPER27_D7 pper27.bit._D7 +#define PPER27_D6 pper27.bit._D6 +#define PPER27_D5 pper27.bit._D5 +#define PPER27_D4 pper27.bit._D4 +#define PPER27_D3 pper27.bit._D3 +#define PPER27_D2 pper27.bit._D2 +#define PPER27_D1 pper27.bit._D1 +#define PPER27_D0 pper27.bit._D0 +__IO_EXTERN PPER28STR pper28; +#define PPER28 pper28.byte +#define PPER28_D7 pper28.bit._D7 +#define PPER28_D6 pper28.bit._D6 +#define PPER28_D5 pper28.bit._D5 +#define PPER28_D4 pper28.bit._D4 +#define PPER28_D3 pper28.bit._D3 +#define PPER28_D2 pper28.bit._D2 +#define PPER28_D1 pper28.bit._D1 +#define PPER28_D0 pper28.bit._D0 +__IO_EXTERN PPER29STR pper29; +#define PPER29 pper29.byte +#define PPER29_D7 pper29.bit._D7 +#define PPER29_D6 pper29.bit._D6 +#define PPER29_D5 pper29.bit._D5 +#define PPER29_D4 pper29.bit._D4 +#define PPER29_D3 pper29.bit._D3 +#define PPER29_D2 pper29.bit._D2 +#define PPER29_D1 pper29.bit._D1 +#define PPER29_D0 pper29.bit._D0 +__IO_EXTERN PPCR14STR ppcr14; /* R-bus Port Pull-Up/Down Control Register */ +#define PPCR14 ppcr14.byte +#define PPCR14_D7 ppcr14.bit._D7 +#define PPCR14_D6 ppcr14.bit._D6 +#define PPCR14_D5 ppcr14.bit._D5 +#define PPCR14_D4 ppcr14.bit._D4 +#define PPCR14_D3 ppcr14.bit._D3 +#define PPCR14_D2 ppcr14.bit._D2 +#define PPCR14_D1 ppcr14.bit._D1 +#define PPCR14_D0 ppcr14.bit._D0 +__IO_EXTERN PPCR15STR ppcr15; +#define PPCR15 ppcr15.byte +#define PPCR15_D7 ppcr15.bit._D7 +#define PPCR15_D6 ppcr15.bit._D6 +#define PPCR15_D5 ppcr15.bit._D5 +#define PPCR15_D4 ppcr15.bit._D4 +#define PPCR15_D3 ppcr15.bit._D3 +#define PPCR15_D2 ppcr15.bit._D2 +#define PPCR15_D1 ppcr15.bit._D1 +#define PPCR15_D0 ppcr15.bit._D0 +__IO_EXTERN PPCR16STR ppcr16; +#define PPCR16 ppcr16.byte +#define PPCR16_D7 ppcr16.bit._D7 +#define PPCR16_D6 ppcr16.bit._D6 +#define PPCR16_D5 ppcr16.bit._D5 +#define PPCR16_D4 ppcr16.bit._D4 +#define PPCR16_D3 ppcr16.bit._D3 +#define PPCR16_D2 ppcr16.bit._D2 +#define PPCR16_D1 ppcr16.bit._D1 +#define PPCR16_D0 ppcr16.bit._D0 +__IO_EXTERN PPCR17STR ppcr17; +#define PPCR17 ppcr17.byte +#define PPCR17_D7 ppcr17.bit._D7 +#define PPCR17_D6 ppcr17.bit._D6 +#define PPCR17_D5 ppcr17.bit._D5 +#define PPCR17_D4 ppcr17.bit._D4 +#define PPCR17_D3 ppcr17.bit._D3 +#define PPCR17_D2 ppcr17.bit._D2 +#define PPCR17_D1 ppcr17.bit._D1 +#define PPCR17_D0 ppcr17.bit._D0 +__IO_EXTERN PPCR18STR ppcr18; +#define PPCR18 ppcr18.byte +#define PPCR18_D6 ppcr18.bit._D6 +#define PPCR18_D2 ppcr18.bit._D2 +__IO_EXTERN PPCR19STR ppcr19; +#define PPCR19 ppcr19.byte +#define PPCR19_D6 ppcr19.bit._D6 +#define PPCR19_D2 ppcr19.bit._D2 +#define PPCR19_D1 ppcr19.bit._D1 +#define PPCR19_D0 ppcr19.bit._D0 +__IO_EXTERN PPCR20STR ppcr20; +#define PPCR20 ppcr20.byte +#define PPCR20_D7 ppcr20.bit._D7 +#define PPCR20_D6 ppcr20.bit._D6 +#define PPCR20_D5 ppcr20.bit._D5 +#define PPCR20_D4 ppcr20.bit._D4 +#define PPCR20_D3 ppcr20.bit._D3 +#define PPCR20_D2 ppcr20.bit._D2 +#define PPCR20_D1 ppcr20.bit._D1 +#define PPCR20_D0 ppcr20.bit._D0 +__IO_EXTERN PPCR21STR ppcr21; +#define PPCR21 ppcr21.byte +#define PPCR21_D7 ppcr21.bit._D7 +#define PPCR21_D6 ppcr21.bit._D6 +#define PPCR21_D5 ppcr21.bit._D5 +#define PPCR21_D4 ppcr21.bit._D4 +#define PPCR21_D3 ppcr21.bit._D3 +#define PPCR21_D2 ppcr21.bit._D2 +#define PPCR21_D1 ppcr21.bit._D1 +#define PPCR21_D0 ppcr21.bit._D0 +__IO_EXTERN PPCR22STR ppcr22; +#define PPCR22 ppcr22.byte +#define PPCR22_D5 ppcr22.bit._D5 +#define PPCR22_D4 ppcr22.bit._D4 +#define PPCR22_D1 ppcr22.bit._D1 +#define PPCR22_D0 ppcr22.bit._D0 +__IO_EXTERN PPCR24STR ppcr24; +#define PPCR24 ppcr24.byte +#define PPCR24_D7 ppcr24.bit._D7 +#define PPCR24_D6 ppcr24.bit._D6 +#define PPCR24_D5 ppcr24.bit._D5 +#define PPCR24_D4 ppcr24.bit._D4 +#define PPCR24_D3 ppcr24.bit._D3 +#define PPCR24_D2 ppcr24.bit._D2 +#define PPCR24_D1 ppcr24.bit._D1 +#define PPCR24_D0 ppcr24.bit._D0 +__IO_EXTERN PPCR26STR ppcr26; +#define PPCR26 ppcr26.byte +#define PPCR26_D1 ppcr26.bit._D1 +#define PPCR26_D0 ppcr26.bit._D0 +__IO_EXTERN PPCR27STR ppcr27; +#define PPCR27 ppcr27.byte +#define PPCR27_D7 ppcr27.bit._D7 +#define PPCR27_D6 ppcr27.bit._D6 +#define PPCR27_D5 ppcr27.bit._D5 +#define PPCR27_D4 ppcr27.bit._D4 +#define PPCR27_D3 ppcr27.bit._D3 +#define PPCR27_D2 ppcr27.bit._D2 +#define PPCR27_D1 ppcr27.bit._D1 +#define PPCR27_D0 ppcr27.bit._D0 +__IO_EXTERN PPCR28STR ppcr28; +#define PPCR28 ppcr28.byte +#define PPCR28_D7 ppcr28.bit._D7 +#define PPCR28_D6 ppcr28.bit._D6 +#define PPCR28_D5 ppcr28.bit._D5 +#define PPCR28_D4 ppcr28.bit._D4 +#define PPCR28_D3 ppcr28.bit._D3 +#define PPCR28_D2 ppcr28.bit._D2 +#define PPCR28_D1 ppcr28.bit._D1 +#define PPCR28_D0 ppcr28.bit._D0 +__IO_EXTERN PPCR29STR ppcr29; +#define PPCR29 ppcr29.byte +#define PPCR29_D7 ppcr29.bit._D7 +#define PPCR29_D6 ppcr29.bit._D6 +#define PPCR29_D5 ppcr29.bit._D5 +#define PPCR29_D4 ppcr29.bit._D4 +#define PPCR29_D3 ppcr29.bit._D3 +#define PPCR29_D2 ppcr29.bit._D2 +#define PPCR29_D1 ppcr29.bit._D1 +#define PPCR29_D0 ppcr29.bit._D0 +__IO_EXTERN IO_LWORD dmasa0; /* DMAC */ +#define DMASA0 dmasa0 +__IO_EXTERN IO_LWORD dmada0; +#define DMADA0 dmada0 +__IO_EXTERN IO_LWORD dmasa1; +#define DMASA1 dmasa1 +__IO_EXTERN IO_LWORD dmada1; +#define DMADA1 dmada1 +__IO_EXTERN IO_LWORD dmasa2; +#define DMASA2 dmasa2 +__IO_EXTERN IO_LWORD dmada2; +#define DMADA2 dmada2 +__IO_EXTERN IO_LWORD dmasa3; +#define DMASA3 dmasa3 +__IO_EXTERN IO_LWORD dmada3; +#define DMADA3 dmada3 +__IO_EXTERN IO_LWORD dmasa4; +#define DMASA4 dmasa4 +__IO_EXTERN IO_LWORD dmada4; +#define DMADA4 dmada4 +__IO_EXTERN FMCSSTR fmcs; /* Flash Memory/I-Cache Control Register */ +#define FMCS fmcs.byte +#define FMCS_ASYNC fmcs.bit._ASYNC +#define FMCS_FIXE fmcs.bit._FIXE +#define FMCS_BIRE fmcs.bit._BIRE +#define FMCS_RDYEG fmcs.bit._RDYEG +#define FMCS_RDY fmcs.bit._RDY +#define FMCS_RDYI fmcs.bit._RDYI +#define FMCS_RW16 fmcs.bit._RW16 +#define FMCS_LPM fmcs.bit._LPM +__IO_EXTERN FMCRSTR fmcr; +#define FMCR fmcr.byte +#define FMCR_LOCK fmcr.bit._LOCK +#define FMCR_PHASE fmcr.bit._PHASE +#define FMCR_PF2I fmcr.bit._PF2I +#define FMCR_RD64 fmcr.bit._RD64 +__IO_EXTERN FCHCRSTR fchcr; +#define FCHCR fchcr.word +#define FCHCR_REN fchcr.bit._REN +#define FCHCR_TAGE fchcr.bit._TAGE +#define FCHCR_FLUSH fchcr.bit._FLUSH +#define FCHCR_DBEN fchcr.bit._DBEN +#define FCHCR_PFEN fchcr.bit._PFEN +#define FCHCR_PFMC fchcr.bit._PFMC +#define FCHCR_LOCK fchcr.bit._LOCK +#define FCHCR_ENAB fchcr.bit._ENAB +#define FCHCR_SIZE1 fchcr.bit._SIZE1 +#define FCHCR_SIZE0 fchcr.bit._SIZE0 +#define FCHCR_SIZE fchcr.bitc._SIZE +__IO_EXTERN FMWTSTR fmwt; +#define FMWT fmwt.word +#define FMWT_WTP1 fmwt.bit._WTP1 +#define FMWT_WTP0 fmwt.bit._WTP0 +#define FMWT_WEXH1 fmwt.bit._WEXH1 +#define FMWT_WEXH0 fmwt.bit._WEXH0 +#define FMWT_WTC3 fmwt.bit._WTC3 +#define FMWT_WTC2 fmwt.bit._WTC2 +#define FMWT_WTC1 fmwt.bit._WTC1 +#define FMWT_WTC0 fmwt.bit._WTC0 +#define FMWT_FRAM fmwt.bit._FRAM +#define FMWT_ATD2 fmwt.bit._ATD2 +#define FMWT_ATD1 fmwt.bit._ATD1 +#define FMWT_ATD0 fmwt.bit._ATD0 +#define FMWT_EQ3 fmwt.bit._EQ3 +#define FMWT_EQ2 fmwt.bit._EQ2 +#define FMWT_EQ1 fmwt.bit._EQ1 +#define FMWT_EQ0 fmwt.bit._EQ0 +#define FMWT_WTP fmwt.bitc._WTP +#define FMWT_WEXH fmwt.bitc._WEXH +#define FMWT_WTC fmwt.bitc._WTC +#define FMWT_ATD fmwt.bitc._ATD +#define FMWT_EQ fmwt.bitc._EQ +__IO_EXTERN FMWT2STR fmwt2; +#define FMWT2 fmwt2.byte +#define FMWT2_ALEH2 fmwt2.bit._ALEH2 +#define FMWT2_ALEH1 fmwt2.bit._ALEH1 +#define FMWT2_ALEH0 fmwt2.bit._ALEH0 +#define FMWT2_ALEH fmwt2.bitc._ALEH +__IO_EXTERN FMPSSTR fmps; +#define FMPS fmps.byte +#define FMPS_PS2 fmps.bit._PS2 +#define FMPS_PS1 fmps.bit._PS1 +#define FMPS_PS0 fmps.bit._PS0 +#define FMPS_PS fmps.bitc._PS +__IO_EXTERN IO_LWORD fmac; +#define FMAC fmac +__IO_EXTERN IO_LWORD fcha0; /* I_Cache Nonchachable area settings Register */ +#define FCHA0 fcha0 +__IO_EXTERN IO_LWORD fcha1; +#define FCHA1 fcha1 +__IO_EXTERN FSCR0STR fscr0; /* Flash Security Control Register */ +#define FSCR0 fscr0.lword +#define FSCR0_CRC31 fscr0.bit._CRC31 +#define FSCR0_CRC30 fscr0.bit._CRC30 +#define FSCR0_CRC29 fscr0.bit._CRC29 +#define FSCR0_CRC28 fscr0.bit._CRC28 +#define FSCR0_CRC27 fscr0.bit._CRC27 +#define FSCR0_CRC26 fscr0.bit._CRC26 +#define FSCR0_CRC25 fscr0.bit._CRC25 +#define FSCR0_CRC24 fscr0.bit._CRC24 +#define FSCR0_CRC23 fscr0.bit._CRC23 +#define FSCR0_CRC22 fscr0.bit._CRC22 +#define FSCR0_CRC21 fscr0.bit._CRC21 +#define FSCR0_CRC20 fscr0.bit._CRC20 +#define FSCR0_CRC19 fscr0.bit._CRC19 +#define FSCR0_CRC18 fscr0.bit._CRC18 +#define FSCR0_CRC17 fscr0.bit._CRC17 +#define FSCR0_CRC16 fscr0.bit._CRC16 +#define FSCR0_CRC15 fscr0.bit._CRC15 +#define FSCR0_CRC14 fscr0.bit._CRC14 +#define FSCR0_CRC13 fscr0.bit._CRC13 +#define FSCR0_CRC12 fscr0.bit._CRC12 +#define FSCR0_CRC11 fscr0.bit._CRC11 +#define FSCR0_CRC10 fscr0.bit._CRC10 +#define FSCR0_CRC9 fscr0.bit._CRC9 +#define FSCR0_CRC8 fscr0.bit._CRC8 +#define FSCR0_CRC7 fscr0.bit._CRC7 +#define FSCR0_CRC6 fscr0.bit._CRC6 +#define FSCR0_CRC5 fscr0.bit._CRC5 +#define FSCR0_CRC4 fscr0.bit._CRC4 +#define FSCR0_CRC3 fscr0.bit._CRC3 +#define FSCR0_CRC2 fscr0.bit._CRC2 +#define FSCR0_CRC1 fscr0.bit._CRC1 +#define FSCR0_CRC0 fscr0.bit._CRC0 +__IO_EXTERN FSCR1STR fscr1; +#define FSCR1 fscr1.lword +#define FSCR1_RDY fscr1.bit._RDY +#define FSCR1_CSZ3 fscr1.bit._CSZ3 +#define FSCR1_CSZ2 fscr1.bit._CSZ2 +#define FSCR1_CSZ1 fscr1.bit._CSZ1 +#define FSCR1_CSZ0 fscr1.bit._CSZ0 +#define FSCR1_CSA15 fscr1.bit._CSA15 +#define FSCR1_CSA14 fscr1.bit._CSA14 +#define FSCR1_CSA13 fscr1.bit._CSA13 +#define FSCR1_CSA12 fscr1.bit._CSA12 +#define FSCR1_CSA11 fscr1.bit._CSA11 +#define FSCR1_CSA10 fscr1.bit._CSA10 +#define FSCR1_CSA9 fscr1.bit._CSA9 +#define FSCR1_CSA8 fscr1.bit._CSA8 +#define FSCR1_CSA7 fscr1.bit._CSA7 +#define FSCR1_CSA6 fscr1.bit._CSA6 +#define FSCR1_CSA5 fscr1.bit._CSA5 +#define FSCR1_CSA4 fscr1.bit._CSA4 +#define FSCR1_CSA3 fscr1.bit._CSA3 +#define FSCR1_CSA2 fscr1.bit._CSA2 +#define FSCR1_CSA1 fscr1.bit._CSA1 +#define FSCR1_CSA0 fscr1.bit._CSA0 +#define FSCR1_CSZ fscr1.bitc._CSZ +__IO_EXTERN CTRLR4STR ctrlr4; /* CAN 4 Control Register */ +#define CTRLR4 ctrlr4.word +#define CTRLR4_Test ctrlr4.bit._Test +#define CTRLR4_CCE ctrlr4.bit._CCE +#define CTRLR4_DAR ctrlr4.bit._DAR +#define CTRLR4_EIE ctrlr4.bit._EIE +#define CTRLR4_SIE ctrlr4.bit._SIE +#define CTRLR4_IE ctrlr4.bit._IE +#define CTRLR4_Init ctrlr4.bit._Init +__IO_EXTERN STATR4STR statr4; +#define STATR4 statr4.word +#define STATR4_BOff statr4.bit._BOff +#define STATR4_EWarn statr4.bit._EWarn +#define STATR4_EPass statr4.bit._EPass +#define STATR4_RxOK statr4.bit._RxOK +#define STATR4_TxOK statr4.bit._TxOK +#define STATR4_LEC2 statr4.bit._LEC2 +#define STATR4_LEC1 statr4.bit._LEC1 +#define STATR4_LEC0 statr4.bit._LEC0 +#define STATR4_LEC statr4.bitc._LEC +__IO_EXTERN ERRCNT4STR errcnt4; +#define ERRCNT4 errcnt4.word +#define ERRCNT4_RP errcnt4.bit._RP +#define ERRCNT4_REC6 errcnt4.bit._REC6 +#define ERRCNT4_REC5 errcnt4.bit._REC5 +#define ERRCNT4_REC4 errcnt4.bit._REC4 +#define ERRCNT4_REC3 errcnt4.bit._REC3 +#define ERRCNT4_REC2 errcnt4.bit._REC2 +#define ERRCNT4_REC1 errcnt4.bit._REC1 +#define ERRCNT4_REC0 errcnt4.bit._REC0 +#define ERRCNT4_TEC7 errcnt4.bit._TEC7 +#define ERRCNT4_TEC6 errcnt4.bit._TEC6 +#define ERRCNT4_TEC5 errcnt4.bit._TEC5 +#define ERRCNT4_TEC4 errcnt4.bit._TEC4 +#define ERRCNT4_TEC3 errcnt4.bit._TEC3 +#define ERRCNT4_TEC2 errcnt4.bit._TEC2 +#define ERRCNT4_TEC1 errcnt4.bit._TEC1 +#define ERRCNT4_TEC0 errcnt4.bit._TEC0 +#define ERRCNT4_REC errcnt4.bitc._REC +#define ERRCNT4_TEC errcnt4.bitc._TEC +__IO_EXTERN BTR4STR btr4; +#define BTR4 btr4.word +#define BTR4_Tseg22 btr4.bit._Tseg22 +#define BTR4_Tseg21 btr4.bit._Tseg21 +#define BTR4_Tseg20 btr4.bit._Tseg20 +#define BTR4_Tseg13 btr4.bit._Tseg13 +#define BTR4_Tseg12 btr4.bit._Tseg12 +#define BTR4_Tseg11 btr4.bit._Tseg11 +#define BTR4_Tseg10 btr4.bit._Tseg10 +#define BTR4_SJW1 btr4.bit._SJW1 +#define BTR4_SJW0 btr4.bit._SJW0 +#define BTR4_BRP5 btr4.bit._BRP5 +#define BTR4_BRP4 btr4.bit._BRP4 +#define BTR4_BRP3 btr4.bit._BRP3 +#define BTR4_BRP2 btr4.bit._BRP2 +#define BTR4_BRP1 btr4.bit._BRP1 +#define BTR4_BRP0 btr4.bit._BRP0 +#define BTR4_Tseg2 btr4.bitc._Tseg2 +#define BTR4_Tseg1 btr4.bitc._Tseg1 +#define BTR4_SJW btr4.bitc._SJW +#define BTR4_BRP btr4.bitc._BRP +__IO_EXTERN IO_WORD intr4; +#define INTR4 intr4 +__IO_EXTERN TESTR4STR testr4; +#define TESTR4 testr4.word +#define TESTR4_Rx testr4.bit._Rx +#define TESTR4_Tx1 testr4.bit._Tx1 +#define TESTR4_Tx0 testr4.bit._Tx0 +#define TESTR4_LBack testr4.bit._LBack +#define TESTR4_Silent testr4.bit._Silent +#define TESTR4_Basic testr4.bit._Basic +#define TESTR4_Tx testr4.bitc._Tx +__IO_EXTERN BRPER4STR brper4; +#define BRPER4 brper4.word +#define BRPER4_BRPE3 brper4.bit._BRPE3 +#define BRPER4_BRPE2 brper4.bit._BRPE2 +#define BRPER4_BRPE1 brper4.bit._BRPE1 +#define BRPER4_BRPE0 brper4.bit._BRPE0 +#define BRPER4_BRPE brper4.bitc._BRPE +__IO_EXTERN BRPE4STR brpe4; +#define BRPE4 brpe4.word +__IO_EXTERN IF1CREQ4STR if1creq4; /* CAN 4 IF 1 */ +#define IF1CREQ4 if1creq4.word +#define IF1CREQ4_Busy if1creq4.bit._Busy +#define IF1CREQ4_MN5 if1creq4.bit._MN5 +#define IF1CREQ4_MN4 if1creq4.bit._MN4 +#define IF1CREQ4_MN3 if1creq4.bit._MN3 +#define IF1CREQ4_MN2 if1creq4.bit._MN2 +#define IF1CREQ4_MN1 if1creq4.bit._MN1 +#define IF1CREQ4_MN0 if1creq4.bit._MN0 +#define IF1CREQ4_MN if1creq4.bitc._MN +__IO_EXTERN IF1CMSK4STR if1cmsk4; +#define IF1CMSK4 if1cmsk4.word +#define IF1CMSK4_WR if1cmsk4.bit._WR +#define IF1CMSK4_Mask if1cmsk4.bit._Mask +#define IF1CMSK4_Arb if1cmsk4.bit._Arb +#define IF1CMSK4_Control if1cmsk4.bit._Control +#define IF1CMSK4_CIP if1cmsk4.bit._CIP +#define IF1CMSK4_TxReq if1cmsk4.bit._TxReq +#define IF1CMSK4_DataA if1cmsk4.bit._DataA +#define IF1CMSK4_DataB if1cmsk4.bit._DataB +__IO_EXTERN IO_LWORD if1msk124; +#define IF1MSK124 if1msk124 +__IO_EXTERN IF1MSK24STR if1msk24; +#define IF1MSK24 if1msk24.word +#define IF1MSK24_MXtd if1msk24.bit._MXtd +#define IF1MSK24_MDir if1msk24.bit._MDir +__IO_EXTERN IO_WORD if1msk14; +#define IF1MSK14 if1msk14 +__IO_EXTERN IO_LWORD if1arb124; +#define IF1ARB124 if1arb124 +__IO_EXTERN IF1ARB24STR if1arb24; +#define IF1ARB24 if1arb24.word +#define IF1ARB24_MsgVal if1arb24.bit._MsgVal +#define IF1ARB24_Xtd if1arb24.bit._Xtd +#define IF1ARB24_DIR if1arb24.bit._DIR +__IO_EXTERN IO_WORD if1arb14; +#define IF1ARB14 if1arb14 +__IO_EXTERN IF1MCTR4STR if1mctr4; +#define IF1MCTR4 if1mctr4.word +#define IF1MCTR4_NewDat if1mctr4.bit._NewDat +#define IF1MCTR4_MsgLst if1mctr4.bit._MsgLst +#define IF1MCTR4_IntPnd if1mctr4.bit._IntPnd +#define IF1MCTR4_UMask if1mctr4.bit._UMask +#define IF1MCTR4_TxIE if1mctr4.bit._TxIE +#define IF1MCTR4_RxIE if1mctr4.bit._RxIE +#define IF1MCTR4_RmtEn if1mctr4.bit._RmtEn +#define IF1MCTR4_TxRqst if1mctr4.bit._TxRqst +#define IF1MCTR4_EoB if1mctr4.bit._EoB +#define IF1MCTR4_DLC3 if1mctr4.bit._DLC3 +#define IF1MCTR4_DLC2 if1mctr4.bit._DLC2 +#define IF1MCTR4_DLC1 if1mctr4.bit._DLC1 +#define IF1MCTR4_DLC0 if1mctr4.bit._DLC0 +#define IF1MCTR4_DLC if1mctr4.bitc._DLC +__IO_EXTERN IO_LWORD if1dta124; +#define IF1DTA124 if1dta124 +__IO_EXTERN IO_WORD if1dta14; +#define IF1DTA14 if1dta14 +__IO_EXTERN IO_WORD if1dta24; +#define IF1DTA24 if1dta24 +__IO_EXTERN IO_LWORD if1dtb124; +#define IF1DTB124 if1dtb124 +__IO_EXTERN IO_WORD if1dtb14; +#define IF1DTB14 if1dtb14 +__IO_EXTERN IO_WORD if1dtb24; +#define IF1DTB24 if1dtb24 +__IO_EXTERN IO_LWORD if1dta_swp124; +#define IF1DTA_SWP124 if1dta_swp124 +__IO_EXTERN IO_WORD if1dta_swp24; +#define IF1DTA_SWP24 if1dta_swp24 +__IO_EXTERN IO_WORD if1dta_swp14; +#define IF1DTA_SWP14 if1dta_swp14 +__IO_EXTERN IO_LWORD if1dtb_swp124; +#define IF1DTB_SWP124 if1dtb_swp124 +__IO_EXTERN IO_WORD if1dtb_swp24; +#define IF1DTB_SWP24 if1dtb_swp24 +__IO_EXTERN IO_WORD if1dtb_swp14; +#define IF1DTB_SWP14 if1dtb_swp14 +__IO_EXTERN IF2CREQ4STR if2creq4; /* CAN 4 IF 2 */ +#define IF2CREQ4 if2creq4.word +#define IF2CREQ4_Busy if2creq4.bit._Busy +#define IF2CREQ4_MN5 if2creq4.bit._MN5 +#define IF2CREQ4_MN4 if2creq4.bit._MN4 +#define IF2CREQ4_MN3 if2creq4.bit._MN3 +#define IF2CREQ4_MN2 if2creq4.bit._MN2 +#define IF2CREQ4_MN1 if2creq4.bit._MN1 +#define IF2CREQ4_MN0 if2creq4.bit._MN0 +#define IF2CREQ4_MN if2creq4.bitc._MN +__IO_EXTERN IF2CMSK4STR if2cmsk4; +#define IF2CMSK4 if2cmsk4.word +#define IF2CMSK4_WR if2cmsk4.bit._WR +#define IF2CMSK4_Mask if2cmsk4.bit._Mask +#define IF2CMSK4_Arb if2cmsk4.bit._Arb +#define IF2CMSK4_Control if2cmsk4.bit._Control +#define IF2CMSK4_CIP if2cmsk4.bit._CIP +#define IF2CMSK4_TxReq if2cmsk4.bit._TxReq +#define IF2CMSK4_DataA if2cmsk4.bit._DataA +#define IF2CMSK4_DataB if2cmsk4.bit._DataB +__IO_EXTERN IO_LWORD if2msk124; +#define IF2MSK124 if2msk124 +__IO_EXTERN IF2MSK24STR if2msk24; +#define IF2MSK24 if2msk24.word +#define IF2MSK24_MXtd if2msk24.bit._MXtd +#define IF2MSK24_MDir if2msk24.bit._MDir +__IO_EXTERN IO_WORD if2msk14; +#define IF2MSK14 if2msk14 +__IO_EXTERN IO_LWORD if2arb124; +#define IF2ARB124 if2arb124 +__IO_EXTERN IF2ARB24STR if2arb24; +#define IF2ARB24 if2arb24.word +#define IF2ARB24_MsgVal if2arb24.bit._MsgVal +#define IF2ARB24_Xtd if2arb24.bit._Xtd +#define IF2ARB24_DIR if2arb24.bit._DIR +__IO_EXTERN IO_WORD if2arb14; +#define IF2ARB14 if2arb14 +__IO_EXTERN IF2MCTR4STR if2mctr4; +#define IF2MCTR4 if2mctr4.word +#define IF2MCTR4_NewDat if2mctr4.bit._NewDat +#define IF2MCTR4_MsgLst if2mctr4.bit._MsgLst +#define IF2MCTR4_IntPnd if2mctr4.bit._IntPnd +#define IF2MCTR4_UMask if2mctr4.bit._UMask +#define IF2MCTR4_TxIE if2mctr4.bit._TxIE +#define IF2MCTR4_RxIE if2mctr4.bit._RxIE +#define IF2MCTR4_RmtEn if2mctr4.bit._RmtEn +#define IF2MCTR4_TxRqst if2mctr4.bit._TxRqst +#define IF2MCTR4_EoB if2mctr4.bit._EoB +#define IF2MCTR4_DLC3 if2mctr4.bit._DLC3 +#define IF2MCTR4_DLC2 if2mctr4.bit._DLC2 +#define IF2MCTR4_DLC1 if2mctr4.bit._DLC1 +#define IF2MCTR4_DLC0 if2mctr4.bit._DLC0 +#define IF2MCTR4_DLC if2mctr4.bitc._DLC +__IO_EXTERN IO_LWORD if2dta124; +#define IF2DTA124 if2dta124 +__IO_EXTERN IO_WORD if2dta14; +#define IF2DTA14 if2dta14 +__IO_EXTERN IO_WORD if2dta24; +#define IF2DTA24 if2dta24 +__IO_EXTERN IO_LWORD if2dtb124; +#define IF2DTB124 if2dtb124 +__IO_EXTERN IO_WORD if2dtb14; +#define IF2DTB14 if2dtb14 +__IO_EXTERN IO_WORD if2dtb24; +#define IF2DTB24 if2dtb24 +__IO_EXTERN IO_LWORD if2dta_swp124; +#define IF2DTA_SWP124 if2dta_swp124 +__IO_EXTERN IO_WORD if2dta_swp24; +#define IF2DTA_SWP24 if2dta_swp24 +__IO_EXTERN IO_WORD if2dta_swp14; +#define IF2DTA_SWP14 if2dta_swp14 +__IO_EXTERN IO_LWORD if2dtb_swp124; +#define IF2DTB_SWP124 if2dtb_swp124 +__IO_EXTERN IO_WORD if2dtb_swp24; +#define IF2DTB_SWP24 if2dtb_swp24 +__IO_EXTERN IO_WORD if2dtb_swp14; +#define IF2DTB_SWP14 if2dtb_swp14 +__IO_EXTERN IO_LWORD treqr124; /* CAN 4 Status Flags */ +#define TREQR124 treqr124 +__IO_EXTERN IO_WORD treqr24; +#define TREQR24 treqr24 +__IO_EXTERN IO_WORD treqr14; +#define TREQR14 treqr14 +__IO_EXTERN IO_LWORD treqr344; +#define TREQR344 treqr344 +__IO_EXTERN IO_LWORD newdt124; +#define NEWDT124 newdt124 +__IO_EXTERN IO_WORD newdt24; +#define NEWDT24 newdt24 +__IO_EXTERN IO_WORD newdt14; +#define NEWDT14 newdt14 +__IO_EXTERN IO_LWORD intpnd124; +#define INTPND124 intpnd124 +__IO_EXTERN IO_WORD intpnd24; +#define INTPND24 intpnd24 +__IO_EXTERN IO_WORD intpnd14; +#define INTPND14 intpnd14 +__IO_EXTERN IO_LWORD msgval124; +#define MSGVAL124 msgval124 +__IO_EXTERN IO_WORD msgval24; +#define MSGVAL24 msgval24 +__IO_EXTERN IO_WORD msgval14; +#define MSGVAL14 msgval14 +__IO_EXTERN BCTRLSTR bctrl; /* EDSU/MPU Registers */ +#define BCTRL bctrl.lword +#define BCTRL_SR bctrl.bit._SR +#define BCTRL_SW bctrl.bit._SW +#define BCTRL_SX bctrl.bit._SX +#define BCTRL_UR bctrl.bit._UR +#define BCTRL_UW bctrl.bit._UW +#define BCTRL_UX bctrl.bit._UX +#define BCTRL_FCPU bctrl.bit._FCPU +#define BCTRL_FDMA bctrl.bit._FDMA +#define BCTRL_EEMM bctrl.bit._EEMM +#define BCTRL_PFD bctrl.bit._PFD +#define BCTRL_SINT1 bctrl.bit._SINT1 +#define BCTRL_SINT0 bctrl.bit._SINT0 +#define BCTRL_EINT1 bctrl.bit._EINT1 +#define BCTRL_EINT0 bctrl.bit._EINT0 +#define BCTRL_EINTT bctrl.bit._EINTT +#define BCTRL_EINTR bctrl.bit._EINTR +#define BCTRL_SINT bctrl.bitc._SINT +#define BCTRL_EINT bctrl.bitc._EINT +__IO_EXTERN BSTATSTR bstat; +#define BSTAT bstat.lword +#define BSTAT_IDX4 bstat.bit._IDX4 +#define BSTAT_IDX3 bstat.bit._IDX3 +#define BSTAT_IDX2 bstat.bit._IDX2 +#define BSTAT_IDX1 bstat.bit._IDX1 +#define BSTAT_IDX0 bstat.bit._IDX0 +#define BSTAT_CDMA bstat.bit._CDMA +#define BSTAT_CSZ1 bstat.bit._CSZ1 +#define BSTAT_CSZ0 bstat.bit._CSZ0 +#define BSTAT_CRW1 bstat.bit._CRW1 +#define BSTAT_CRW0 bstat.bit._CRW0 +#define BSTAT_PV bstat.bit._PV +#define BSTAT_RST bstat.bit._RST +#define BSTAT_INT1 bstat.bit._INT1 +#define BSTAT_INT0 bstat.bit._INT0 +#define BSTAT_INTT bstat.bit._INTT +#define BSTAT_INTR bstat.bit._INTR +#define BSTAT_IDX bstat.bitc._IDX +#define BSTAT_CSZ bstat.bitc._CSZ +#define BSTAT_CRW bstat.bitc._CRW +#define BSTAT_INT bstat.bitc._INT +__IO_EXTERN IO_LWORD biac; +#define BIAC biac +__IO_EXTERN IO_LWORD boac; +#define BOAC boac +__IO_EXTERN BIRQSTR birq; +#define BIRQ birq.lword +#define BIRQ_BD31 birq.bit._BD31 +#define BIRQ_BD30 birq.bit._BD30 +#define BIRQ_BD29 birq.bit._BD29 +#define BIRQ_BD28 birq.bit._BD28 +#define BIRQ_BD27 birq.bit._BD27 +#define BIRQ_BD26 birq.bit._BD26 +#define BIRQ_BD25 birq.bit._BD25 +#define BIRQ_BD24 birq.bit._BD24 +#define BIRQ_BD23 birq.bit._BD23 +#define BIRQ_BD22 birq.bit._BD22 +#define BIRQ_BD21 birq.bit._BD21 +#define BIRQ_BD20 birq.bit._BD20 +#define BIRQ_BD19 birq.bit._BD19 +#define BIRQ_BD18 birq.bit._BD18 +#define BIRQ_BD17 birq.bit._BD17 +#define BIRQ_BD16 birq.bit._BD16 +#define BIRQ_BD15 birq.bit._BD15 +#define BIRQ_BD14 birq.bit._BD14 +#define BIRQ_BD13 birq.bit._BD13 +#define BIRQ_BD12 birq.bit._BD12 +#define BIRQ_BD11 birq.bit._BD11 +#define BIRQ_BD10 birq.bit._BD10 +#define BIRQ_BD9 birq.bit._BD9 +#define BIRQ_BD8 birq.bit._BD8 +#define BIRQ_BD7 birq.bit._BD7 +#define BIRQ_BD6 birq.bit._BD6 +#define BIRQ_BD5 birq.bit._BD5 +#define BIRQ_BD4 birq.bit._BD4 +#define BIRQ_BD3 birq.bit._BD3 +#define BIRQ_BD2 birq.bit._BD2 +#define BIRQ_BD1 birq.bit._BD1 +#define BIRQ_BD0 birq.bit._BD0 +__IO_EXTERN BCR0STR bcr0; +#define BCR0 bcr0.lword +#define BCR0_SRX1 bcr0.bit._SRX1 +#define BCR0_SW1 bcr0.bit._SW1 +#define BCR0_SRX0 bcr0.bit._SRX0 +#define BCR0_SW0 bcr0.bit._SW0 +#define BCR0_URX1 bcr0.bit._URX1 +#define BCR0_UW1 bcr0.bit._UW1 +#define BCR0_URX0 bcr0.bit._URX0 +#define BCR0_UW0 bcr0.bit._UW0 +#define BCR0_MPE bcr0.bit._MPE +#define BCR0_COMB bcr0.bit._COMB +#define BCR0_CTC1 bcr0.bit._CTC1 +#define BCR0_CTC0 bcr0.bit._CTC0 +#define BCR0_OBS1 bcr0.bit._OBS1 +#define BCR0_OBS0 bcr0.bit._OBS0 +#define BCR0_OBT1 bcr0.bit._OBT1 +#define BCR0_OBT0 bcr0.bit._OBT0 +#define BCR0_EP3 bcr0.bit._EP3 +#define BCR0_EP2 bcr0.bit._EP2 +#define BCR0_EP1 bcr0.bit._EP1 +#define BCR0_EP0 bcr0.bit._EP0 +#define BCR0_EM1 bcr0.bit._EM1 +#define BCR0_EM0 bcr0.bit._EM0 +#define BCR0_ER1 bcr0.bit._ER1 +#define BCR0_ER0 bcr0.bit._ER0 +#define BCR0_CTC bcr0.bitc._CTC +#define BCR0_OBS bcr0.bitc._OBS +#define BCR0_OBT bcr0.bitc._OBT +#define BCR0_EP bcr0.bitc._EP +#define BCR0_EM bcr0.bitc._EM +#define BCR0_ER bcr0.bitc._ER +__IO_EXTERN BCR1STR bcr1; +#define BCR1 bcr1.lword +#define BCR1_SRX1 bcr1.bit._SRX1 +#define BCR1_SW1 bcr1.bit._SW1 +#define BCR1_SRX0 bcr1.bit._SRX0 +#define BCR1_SW0 bcr1.bit._SW0 +#define BCR1_URX1 bcr1.bit._URX1 +#define BCR1_UW1 bcr1.bit._UW1 +#define BCR1_URX0 bcr1.bit._URX0 +#define BCR1_UW0 bcr1.bit._UW0 +#define BCR1_MPE bcr1.bit._MPE +#define BCR1_COMB bcr1.bit._COMB +#define BCR1_CTC1 bcr1.bit._CTC1 +#define BCR1_CTC0 bcr1.bit._CTC0 +#define BCR1_OBS1 bcr1.bit._OBS1 +#define BCR1_OBS0 bcr1.bit._OBS0 +#define BCR1_OBT1 bcr1.bit._OBT1 +#define BCR1_OBT0 bcr1.bit._OBT0 +#define BCR1_EP3 bcr1.bit._EP3 +#define BCR1_EP2 bcr1.bit._EP2 +#define BCR1_EP1 bcr1.bit._EP1 +#define BCR1_EP0 bcr1.bit._EP0 +#define BCR1_EM1 bcr1.bit._EM1 +#define BCR1_EM0 bcr1.bit._EM0 +#define BCR1_ER1 bcr1.bit._ER1 +#define BCR1_ER0 bcr1.bit._ER0 +#define BCR1_CTC bcr1.bitc._CTC +#define BCR1_OBS bcr1.bitc._OBS +#define BCR1_OBT bcr1.bitc._OBT +#define BCR1_EP bcr1.bitc._EP +#define BCR1_EM bcr1.bitc._EM +#define BCR1_ER bcr1.bitc._ER +__IO_EXTERN IO_LWORD bad0; +#define BAD0 bad0 +__IO_EXTERN IO_LWORD bad1; +#define BAD1 bad1 +__IO_EXTERN IO_LWORD bad2; +#define BAD2 bad2 +__IO_EXTERN IO_LWORD bad3; +#define BAD3 bad3 +__IO_EXTERN IO_LWORD bad4; +#define BAD4 bad4 +__IO_EXTERN IO_LWORD bad5; +#define BAD5 bad5 +__IO_EXTERN IO_LWORD bad6; +#define BAD6 bad6 +__IO_EXTERN IO_LWORD bad7; +#define BAD7 bad7 +__IO_EXTERN IO_LWORD fsv1; /* FSV & BSV Registers */ +#define FSV1 fsv1 +__IO_EXTERN IO_LWORD bsv1; +#define BSV1 bsv1 +__IO_EXTERN IO_LWORD fsv2; +#define FSV2 fsv2 +__IO_EXTERN IO_LWORD bsv2; +#define BSV2 bsv2 +/* include : INC465k_BSYNC.INC */ +/*-------------------------------------------------------------------*/ +/* INC465k.BSYNC : Macros Bus Sync*/ + +#define RB_SYNC if(RBSYNC) +#define CB_SYNC4 if(CBSYNC4) +/*-------------------------------------------------------------------*/ +#endif /* __FASM__ */ +#endif /* __MB91XXX_H */ +#endif /* __IO_DEFINE */ diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..c74f757 --- /dev/null +++ b/readme.txt @@ -0,0 +1,58 @@ +========================================================================== + FLASH Programming Demo for MB91F465K +========================================================================== + Fujitsu Microelectronics Europe GmbH + http://emea.fujitsu.com/microelectronics + + The following software is for demonstration purposes only. It is not + fully tested, nor validated in order to fullfill its task under all + circumstances. Therefore, this software or any part of it must only be + used in an evaluation laboratory environment. + This software is subject to the rules of our standard DISCLAIMER, that is + delivered with our SW-tools on the Fujitsu Microcontrollers CD + (V3.4 or higher "\START.HTM") or on our Internet Pages: + http://www.fme.gsdc.de/gsdc.htm + http://emea.fujitsu.com/microelectronics +========================================================================== + +History +Date Ver Author Softune Description +10.07.07 1.0 MVo V60L06 First Version + +========================================================================== + +This is simple demo showing how to use the FLASH programming Auto +Algorithms. + +Target of this demo is to show application of the following aspects of +FLASH memory erase/write: + +1) Preparation of FLASH Read/Write Mode (via BootROM routine) +2) Sector Erase +3) Sector Erase Suspend/Resume +4) Write Halfword to FLASH memory addresses + +Remarks: + +A) Reload Timer 0 is setup to demonstrate handling of Interrupt Requests + via polling and subsequent Sector Erase Suspend, Restore Global + Interrupt Flag, Handling of IRQ and Sector Erase Resume. + +B) Handling of RAMCODE is added to Start91460.asm because FLASH prog. + routines have to be run from RAM since no code fetching is possible + while write/erase of FLASH memory. + +Connect MCU UART4 to Terminal Program (19200Baud 8N1). After Power On +a welcome message is output on UART4. The Action of Reload Timer 0 is +to increase a counter displayed on LED D1..D8 of SK-91F465K-120PMT each +0.010s. +The FLASH memory Sector content at Addresses 0xA0000 up to 0xA001F is +shown. +After this the Sector 0xA0000 will be erased by Sector +Erase command (this Sector Erase Commands is repeatedly interrupted by +Reload Timer 0 Interrupts which are handled from FLASH memory (Sector +Erase Suspend/Resume). +When the Sectors are earsed a few data are programmed to some given +addresses in the sector 0xA0000. +Finaly the FLASH memory content at addresses 0xA0000 up to 0xA001F is shown +again to confirm the programmed values. diff --git a/tags b/tags new file mode 100644 index 0000000..992b012 --- /dev/null +++ b/tags @@ -0,0 +1,543 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.8 // +AS Makefile /^AS = $(PREFIX)fasm911s$/;" m +ASCII uart.c /^const char ASCII[] = "0123456789ABCDEF";$/;" v +ASFLAGS Makefile /^ASFLAGS = -g -w 2 -O 0 -linf ON -lsrc ON -lsec ON$/;" m +CC Makefile /^CC = $(PREFIX)fcc911s$/;" m +CFLAGS Makefile /^CFLAGS = -g -w 1 -O 4 -B -K SPEED -K LONGADDRESS$/;" m +CONV Makefile /^CONV = $(PREFIX)f2ms$/;" m +CONVFLAGS Makefile /^CONVFLAGS = -cwno$/;" m +CPUT Makefile /^CPUT = -cpu MB91F465K #TODO: change to X$/;" m +DEFINES Makefile /^DEFINES =$/;" m +DEPDIR Makefile /^DEPDIR = .deps$/;" m +DPOLL Flash.h 17;" d +DefaultIRQHandler vectors.c /^void DefaultIRQHandler (void)$/;" f +Echo4 uart.c /^char Echo4(void) \/* Echo UART and return ch *\/$/;" f +FLASH_CheckPendingInterrupt Flash.c /^unsigned char FLASH_CheckPendingInterrupt()$/;" f +FLASH_PrepareReadMode Flash.c /^void FLASH_PrepareReadMode()$/;" f +FLASH_PrepareWriteHalfWordMode Flash.c /^void FLASH_PrepareWriteHalfWordMode()$/;" f +FLASH_ReadReset Flash.c /^unsigned char FLASH_ReadReset()$/;" f +FLASH_ResumeSectorErase Flash.c /^unsigned char FLASH_ResumeSectorErase(unsigned int secaddr)$/;" f +FLASH_SectorBlankCheck Flash.c /^unsigned char FLASH_SectorBlankCheck(unsigned int secaddr, unsigned int size)$/;" f +FLASH_SectorErase Flash.c /^unsigned char FLASH_SectorErase(unsigned int secadr)$/;" f +FLASH_WriteHalfWord Flash.c /^unsigned char FLASH_WriteHalfWord(unsigned int adr, unsigned short int data)$/;" f +FMODwait Start91460.asm /^FMODwait: $/;" l +Getch4 uart.c /^char Getch4(void) \/* waits for and returns incomming char *\/$/;" f +IFlag Flash.c /^static unsigned int IFlag;$/;" v file: +InitIrqLevels vectors.c /^void InitIrqLevels(void)$/;" f +InitUart4 uart.c /^void InitUart4(void)$/;" f +L0 Start91460.asm /^L0:$/;" l +L1 Start91460.asm /^L1:$/;" l +LD Makefile /^LD = $(PREFIX)flnk911s$/;" m +LDFLAGS Makefile /^LDFLAGS = -g -AL 2$/;" m +LDM0 Flash.c /^ LDM0 (R0)$/;" f +LIBR Makefile /^LIBR = $(PREFIX)flibs$/;" m +LIBRFLAGS Makefile /^LIBRFLAGS = -dt s,d,r,a -pl 60 -pw 132 -g -cwno $(CPUT)$/;" m +NoMAINCSVreset Start91460.asm /^NoMAINCSVreset: $/;" l +NoSUBCSVreset Start91460.asm /^NoSUBCSVreset: $/;" l +OBJS Makefile /^OBJS = Flash.obj MAIN.obj RLT.obj uart.obj vectors.obj Start91460.obj mb91465k.obj$/;" m +PLLwait Start91460.asm /^PLLwait: $/;" l +PREFIX Makefile /^PREFIX = wine $(FUJDEV)\/Bin\/$/;" m +PS Flash.c /^ MOV R0,PS ; Write back PS$/;" v +Putch4 uart.c /^void Putch4(char ch) \/* sends a char *\/$/;" f +Putdec4 uart.c /^void Putdec4(unsigned long x, int digits)$/;" f +Puthex4 uart.c /^void Puthex4(unsigned long n, unsigned char digits)$/;" f +Puts4 uart.c /^void Puts4(const char *Name2) \/* Puts a String to UART *\/$/;" f +R0 Flash.c /^ MOV R0,PS ; Write back PS$/;" v +R0 Flash.c /^ OR R4,R0 ; Set Flag as saved$/;" v +R4 Flash.c /^ OR R4,R0 ; Set Flag as saved$/;" v +RLT_CLOCKMODE_DIV128 RLT.h 21;" d +RLT_CLOCKMODE_DIV2 RLT.h 16;" d +RLT_CLOCKMODE_DIV32 RLT.h 18;" d +RLT_CLOCKMODE_DIV64 RLT.h 20;" d +RLT_CLOCKMODE_DIV8 RLT.h 17;" d +RLT_CLOCKMODE_EXT RLT.h 19;" d +RLT_Channel0_ISR RLT.c /^__interrupt void RLT_Channel0_ISR()$/;" f +RLT_Channel1_ISR RLT.c /^__interrupt void RLT_Channel1_ISR()$/;" f +RLT_Channel2_ISR RLT.c /^__interrupt void RLT_Channel2_ISR()$/;" f +RLT_Channel3_ISR RLT.c /^__interrupt void RLT_Channel3_ISR()$/;" f +RLT_Channel4_ISR RLT.c /^__interrupt void RLT_Channel4_ISR()$/;" f +RLT_Channel5_ISR RLT.c /^__interrupt void RLT_Channel5_ISR()$/;" f +RLT_Channel6_ISR RLT.c /^__interrupt void RLT_Channel6_ISR()$/;" f +RLT_Channel7_ISR RLT.c /^__interrupt void RLT_Channel7_ISR()$/;" f +RLT_EnableInterrupt RLT.c /^void RLT_EnableInterrupt(unsigned char channel)$/;" f +RLT_InitializeTimer RLT.c /^void RLT_InitializeTimer(unsigned char channel, unsigned char runmode, unsigned char clockmode, unsigned char triggermode, unsigned char outputmode)$/;" f +RLT_OUTOUTMODE_HIGHLEVEL RLT.h 28;" d +RLT_OUTPUTMODE_LOWLEVEL RLT.h 29;" d +RLT_RUMMODE_RELOAD RLT.h 14;" d +RLT_RUNMODE_ONESHOT RLT.h 13;" d +RLT_SetReloadValue RLT.c /^void RLT_SetReloadValue(unsigned char channel, unsigned short int value)$/;" f +RLT_TRIGGER_BOTHEDGES RLT.h 26;" d +RLT_TRIGGER_EXT_FALLINGEDGE RLT.h 24;" d +RLT_TRIGGER_EXT_RISINGEDGE RLT.h 25;" d +RLT_TRIGGER_SOFTWARE RLT.h 23;" d +RLT_TriggerTimer RLT.c /^void RLT_TriggerTimer(unsigned char channel)$/;" f +SETIMR Flash.h 19;" d +TARGET Makefile /^TARGET = $(TNAME).abs$/;" m +TARGET_MHX Makefile /^TARGET_MHX = $(TNAME).mhx$/;" m +TLOVER Flash.h 18;" d +TNAME Makefile /^TNAME = fuj$/;" m +__FLASH_H__ Flash.h 9;" d +__IO_DEFINE mb91465k.asm /^#define __IO_DEFINE$/;" d +__IO_EXTERN mb91465k.h 33;" d +__IO_EXTERN mb91465k.h 35;" d +__RLT_H__ RLT.h 9;" d +__abort Start91460.asm /^ __abort:$/;" l +__exit Start91460.asm /^ __exit:$/;" l +__start Start91460.asm /^__start: ; start point $/;" l +__systemstack Start91460.asm /^ __systemstack:$/;" l +__systemstack_top Start91460.asm /^ __systemstack_top: $/;" l +__userstack Start91460.asm /^ __userstack:$/;" l +__userstack_top Start91460.asm /^ __userstack_top:$/;" l +_adcr0 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v +_adcr1 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v +_adcs mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v +_adcs0 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v +_adct mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v +_adct0 mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v +_adech mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v +_aderh mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v +_aderl mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v +_adsch mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v +_bad2 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v +_bad3 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v +_bad4 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v +_bad5 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v +_bcr0 mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v +_bcr1 mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v +_bctrl mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v +_bgr000 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v +_bgr002 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v +_bgr004 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v +_bgr01 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v +_bgr03 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v +_bgr100 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v +_bgr101 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v +_bgr102 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v +_bgr103 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v +_bgr104 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v +_birq mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v +_boac mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v +_brpe4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v +_brper4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v +_bsd0 mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v +_bsd1 mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v +_bsdc mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v +_bsrr mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v +_bsv1 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v +_btr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v +_canckd mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v +_canpre mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v +_clkr mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v +_cmt1 mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v +_cmt2 mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v +_csvcr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v +_csvtr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v +_ctrlr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v +_cucr mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v +_cutd mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v +_cutr1 mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v +_cutr2 mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v +_ddr14 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v +_ddr15 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v +_ddr16 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v +_ddr17 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v +_ddr20 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v +_ddr21 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v +_ddr22 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v +_ddr24 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v +_ddr28 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v +_ddr29 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v +_dicr mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v +_divr0 mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v +_divr1 mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v +_dmaca1 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v +_dmaca2 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v +_dmaca4 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v +_dmacb1 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v +_dmacb2 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v +_dmacb4 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v +_dmacr mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v +_dmada1 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v +_dmada2 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v +_dmada4 mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v +_dmasa0 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v +_dmasa2 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v +_dmasa3 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v +_eccr02 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v +_eccr03 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v +_eccr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v +_eirr0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v +_elvr0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v +_elvr1 mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v +_enir0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v +_epfr16 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v +_epfr17 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v +_epfr18 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v +_epfr19 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v +_epfr22 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v +_epfr24 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v +_epfr26 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v +_epfr27 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v +_epilr14 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v +_epilr17 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v +_epilr18 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v +_epilr19 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v +_epilr20 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v +_epilr24 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v +_epilr26 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v +_epilr27 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v +_epilr28 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v +_errcnt4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v +_escr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v +_escr03 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v +_escr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v +_fcha0 mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v +_fcha1 mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v +_fchcr mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v +_fmac mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v +_fmcr mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v +_fmcs mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v +_fmps mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v +_fsr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v +_fsv1 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v +_fsv2 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v +_gcn10 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v +_gcn12 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v +_gcn20 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v +_gcn22 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v +_hrcl mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v +_hwwd mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v +_hwwde mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v +_ibcr0 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v +_ibsr0 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v +_iccr0 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v +_icr02 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v +_icr03 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v +_icr04 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v +_icr05 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v +_icr08 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v +_icr09 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v +_icr10 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v +_icr11 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v +_icr14 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v +_icr15 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v +_icr16 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v +_icr17 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v +_icr20 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v +_icr21 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v +_icr22 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v +_icr23 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v +_icr26 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v +_icr27 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v +_icr28 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v +_icr29 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v +_icr32 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v +_icr33 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v +_icr34 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v +_icr35 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v +_icr38 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v +_icr39 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v +_icr40 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v +_icr41 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v +_icr44 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v +_icr45 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v +_icr46 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v +_icr47 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v +_icr50 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v +_icr51 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v +_icr52 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v +_icr53 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v +_icr56 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v +_icr57 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v +_icr58 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v +_icr59 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v +_icr62 mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v +_icr63 mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v +_ics01 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v +_ics23 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v +_ics45 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v +_idar0 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v +_if1arb124 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v +_if1arb14 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v +_if1arb24 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v +_if1cmsk4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v +_if1creq4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v +_if1dta14 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v +_if1dta24 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v +_if1dta_swp14 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v +_if1dta_swp24 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v +_if1dtb124 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v +_if1dtb14 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v +_if1dtb_swp124 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v +_if1dtb_swp24 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v +_if1msk14 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v +_if2arb14 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v +_if2cmsk4 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v +_if2dta124 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v +_if2dta14 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v +_if2dta_swp124 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v +_if2dta_swp24 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v +_if2dtb14 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v +_if2dtb24 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v +_if2dtb_swp14 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v +_if2dtb_swp24 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v +_if2mctr4 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v +_if2msk124 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v +_if2msk14 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v +_if2msk24 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v +_intpnd124 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v +_ipcp2 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v +_ipcp3 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v +_ipcp5 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v +_ipcp6 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v +_ipcp7 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v +_itbal0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v +_itmk0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v +_itmkh0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v +_itmkl0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v +_modr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v +_msgval124 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v +_msgval14 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v +_msgval24 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v +_newdt124 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v +_newdt14 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v +_newdt24 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v +_occp2 mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v +_occp3 mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v +_occp5 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v +_occp6 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v +_occp7 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v +_ocs01 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v +_ocs23 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v +_ocs45 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v +_oscc1 mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v +_osccr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v +_oscrh mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v +_oscrl mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v +_oscs2 mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v +_pcnh00 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v +_pcnh01 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v +_pcnh02 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v +_pcnh03 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v +_pcnh04 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v +_pcnh05 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v +_pcnh06 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v +_pcnh07 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v +_pcnh08 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v +_pcnh09 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v +_pcnh10 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v +_pcnh11 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v +_pcnl00 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v +_pcnl01 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v +_pcnl02 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v +_pcnl03 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v +_pcnl04 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v +_pcnl05 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v +_pcnl06 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v +_pcnl07 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v +_pcnl08 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v +_pcnl09 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v +_pcnl10 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v +_pcnl11 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v +_pcsr00 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v +_pcsr01 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v +_pcsr02 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v +_pcsr03 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v +_pcsr04 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v +_pcsr05 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v +_pcsr06 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v +_pcsr07 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v +_pcsr08 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v +_pcsr09 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v +_pcsr10 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v +_pcsr11 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v +_pdr15 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v +_pdr16 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v +_pdr17 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v +_pdr18 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v +_pdr21 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v +_pdr22 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v +_pdr24 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v +_pdr26 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v +_pdr29 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v +_pdrd16 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v +_pdrd17 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v +_pdrd18 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v +_pdrd19 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v +_pdrd22 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v +_pdrd24 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v +_pdrd26 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v +_pdrd27 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v +_pfr14 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v +_pfr15 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v +_pfr18 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v +_pfr19 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v +_pfr20 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v +_pfr21 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v +_pfr26 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v +_pfr27 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v +_pfr28 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v +_pfr29 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v +_pilr14 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v +_pilr15 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v +_pilr16 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v +_pilr19 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v +_pilr20 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v +_pilr21 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v +_pilr22 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v +_pilr27 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v +_pilr28 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v +_pilr29 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v +_pllctrl mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v +_plldivg mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v +_pllmulg mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v +_podr15 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v +_podr16 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v +_podr17 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v +_podr18 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v +_podr21 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v +_podr22 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v +_podr24 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v +_podr26 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v +_podr29 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v +_porten mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v +_ppcr14 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v +_ppcr15 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v +_ppcr16 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v +_ppcr19 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v +_ppcr20 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v +_ppcr21 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v +_ppcr22 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v +_ppcr27 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v +_ppcr28 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v +_ppcr29 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v +_pper15 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v +_pper16 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v +_pper17 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v +_pper18 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v +_pper21 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v +_pper22 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v +_pper24 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v +_pper26 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v +_pper29 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v +_ptmr00 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v +_ptmr01 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v +_ptmr02 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v +_ptmr03 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v +_ptmr04 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v +_ptmr05 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v +_ptmr06 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v +_ptmr07 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v +_ptmr08 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v +_ptmr09 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v +_ptmr10 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v +_ptmr11 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v +_rbsync mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v +_rdr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v +_rdr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v +_rdr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v +_regctr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v +_regsel mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v +_rsrr mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v +_scr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v +_scr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v +_scr04 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v +_smr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v +_smr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v +_smr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v +_smr04 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v +_ssr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v +_ssr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v +_ssr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v +_ssr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v +_statr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v +_stcr mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v +_tccs0 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v +_tccs2 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v +_tccs3 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v +_tccs5 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v +_tccs6 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v +_tcdt0 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v +_tcdt2 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v +_tcdt3 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v +_tcdt4 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v +_tcdt6 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v +_tcdt7 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v +_tdr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v +_tdr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v +_tdr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v +_tmcsr0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v +_tmcsr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v +_tmcsr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v +_tmcsr5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v +_tmcsr6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v +_tmcsrh0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v +_tmcsrh1 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v +_tmcsrh4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v +_tmcsrh5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v +_tmcsrh6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v +_tmcsrh7 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v +_tmcsrl0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v +_tmcsrl1 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v +_tmcsrl2 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v +_tmcsrl5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v +_tmcsrl6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v +_tmcsrl7 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v +_tmr2 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v +_tmr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v +_tmr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v +_tmr5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v +_tmrlr1 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v +_tmrlr2 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v +_tmrlr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v +_tmrlr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v +_tmrlr7 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v +_treqr124 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v +_treqr24 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v +_wait64_loop Start91460.asm /^_wait64_loop:$/;" l +_wpr mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v +_wtcer mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v +_wtcr mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v +_wtmr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v +_wtsr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v +clock_startup Start91460.asm /^clock_startup:$/;" l +copy_iram1 Start91460.asm /^copy_iram1: $/;" l +copy_iram_end Start91460.asm /^copy_iram_end: $/;" l +copy_rom1 Start91460.asm /^copy_rom1:$/;" l +copy_rom2 Start91460.asm /^copy_rom2:$/;" l +copy_rom_end Start91460.asm /^copy_rom_end:$/;" l +data_clr0 Start91460.asm /^data_clr0:$/;" l +data_clr1 Start91460.asm /^data_clr1:$/;" l +data_clr2 Start91460.asm /^data_clr2:$/;" l +data_clr_end Start91460.asm /^data_clr_end:$/;" l +emu_sram_cs_mb91461r Start91460.asm /^emu_sram_cs_mb91461r: $/;" l +emu_sram_cs_mb91461r Start91460.asm /^emu_sram_cs_mb91461r:$/;" l +fill_sstack1 Start91460.asm /^fill_sstack1:$/;" l +fill_sstack2 Start91460.asm /^fill_sstack2:$/;" l +fill_sstack_end Start91460.asm /^fill_sstack_end:$/;" l +fill_ustack1 Start91460.asm /^fill_ustack1:$/;" l +fill_ustack2 Start91460.asm /^fill_ustack2:$/;" l +fill_ustack_end Start91460.asm /^fill_ustack_end:$/;" l +gearDownLoop Start91460.asm /^gearDownLoop: $/;" l +gearUpLoop Start91460.asm /^gearUpLoop: $/;" l +hseq_1 Flash.h 13;" d +hseq_2 Flash.h 14;" d +main MAIN.c /^void main(void)$/;" f +mainNotStopped Start91460.asm /^mainNotStopped: $/;" l +mainStabTime Start91460.asm /^ mainStabTime: ; Wait for stabilisation time$/;" l +noClockStartup Start91460.asm /^noClockStartup:$/;" l +notOnPll Start91460.asm /^notOnPll:$/;" l +notOnSubClock Start91460.asm /^notOnSubClock:$/;" l +smd_cs Start91460.asm /^smd_cs: $/;" l +smd_cs Start91460.asm /^smd_cs:$/;" l +smd_cs_mb91461r Start91460.asm /^smd_cs_mb91461r:$/;" l +smd_tbr Start91460.asm /^smd_tbr: $/;" l +start_main Start91460.asm /^start_main:$/;" l +startnop Start91460.asm /^startnop: $/;" l +subStabTime Start91460.asm /^subStabTime: $/;" l +xFFFFFFEF Flash.c /^ ANDCCR #0xFFFFFFEF ; Clear Interrupt Flag$/;" v diff --git a/uart.c b/uart.c new file mode 100644 index 0000000..f4ccfb7 --- /dev/null +++ b/uart.c @@ -0,0 +1,129 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*---------------------------------------------------------------------------*/ + +#include "mb91465k.h" + +const char ASCII[] = "0123456789ABCDEF"; + +void InitUart4(void) +{ + // Initialize UART asynchronous mode + // BGR04 = 1666; // 9600 Baud @ 16MHz + BGR04 = 832; // 19200 Baud @ 16MHz + // BGR04 = 416; // 38400 Baud @ 16MHz + + // BGR04 = 2083; // 9600 Baud @ 20MHz + // BGR04 = 1041; // 19200 Baud @ 20MHz + // BGR04 = 520; // 38400 Baud @ 20MHz + + // BGR04 = 2499; // 9600 Baud @ 24MHz + // BGR04 = 1249; // 19200 Baud @ 24MHz + // BGR04 = 624; // 38400 Baud @ 24MHz + SCR04 = 0x17; // 8N1 + SMR04 = 0x0d; // enable SOT3, Reset, normal mode + SSR04 = 0x00; // LSB first + PFR19 = (PFR19 & 0xFC) | 0x03; // enable UART: SIN,SOT for async. transfer + EPFR19 = 0x00; // enable UART +} + +void Putch4(char ch) /* sends a char */ +{ + while (SSR04_TDRE == 0); /* wait for transmit buffer empty */ + TDR04 = ch; /* put ch into buffer */ +} + +char Getch4(void) /* waits for and returns incomming char */ +{ + volatile unsigned ch; + + for(;;) + { + + while(SSR04_RDRF == 0) /* wait for data received */ + HWWD = 0x00; + + ch = RDR04; + + if ((SSR04 & 0xE0) != 0) /* Check for errors PE, ORE, FRE */ + { + SCR04_CRE = 1; /* Clear error flags */ + } + else + return (ch); /* return char */ + } +} + + +void Puts4(const char *Name2) /* Puts a String to UART */ +{ + volatile int i,len; + + len = strlen(Name2); + + for (i=0; i> div)&0xF); /* get hex-digit value */ + Putch4(digit + ((digit < 0xA) ? '0' : 'A' - 0xA)); + div-=4; /* next digit shift */ + } +} + +void Putdec4(unsigned long x, int digits) +{ + int i; + char buf[10],sign=1; + + if (digits < 0) { /* should be print of zero? */ + digits *= (-1); + sign =1; + } + buf[digits]='\0'; /* end sign of string */ + + for (i=digits; i>0; i--) { + buf[i-1] = ASCII[x % 10]; + x = x/10; + } + + if ( sign ) + { + for (i=0; buf[i]=='0'; i++) { /* no print of zero */ + if ( i