#set others 7 ; MB91460 series
;
;
-#set DEVICE MB91465K ; <<< select device
-;
-#set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector
+#set DEVICE MB91465X ; <<< select device
;=========================================================================================
; 4.3 Stack Type and Stack Size
;=========================================================================================
; Check the stack information files (*.stk) in the LIB\911 directory.
;
;=========================================================================================
-; 4.4 Copy code from Flash to I-RAM
-;=========================================================================================
-;
-#set I_RAM ON ; <<< select if code in section IRAM
-; should be copied
-; If this option is activated code located in the section IRAM is copied during startup
-; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
-;
-;=========================================================================================
; 4.7 Clock Configuration
;=========================================================================================
;=========================================================================================
#set PSCLOCK_MAIN 0x30 ; select Main Oscillation
;
;=========================================================================================
-; 5.1 CLOCKSPEED == CLOCK_USER <<<
-;=========================================================================================
-; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the
-; corresponding application note.
-;
-#if (CLOCKSPEED == CLOCK_USER )
- #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource
- #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF
- #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
- #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG;
- #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG;
- ; Clock Divider
- #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz
- #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz
- #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz
- ; CAN Clock
- #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz
- #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz
- #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD;
- ; Voltage Regulator
- #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;
- #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;
- ; Memory Controller
- #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;
- #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;
- #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;
-#endif
-;
-;=========================================================================================
; 5.2 CLOCKSPEED == NO_CLOCK
;=========================================================================================
;
;=========================================================================================
.export __start
.import _main
- .import _RAM_INIT
- .import _ROM_INIT
;=========================================================================================
; 6.1 Define Stack Size
;=========================================================================================
+ .section DATA, data, align=4
.SECTION SSTACK, STACK, ALIGN=4
#if STACK_RESERVE == ON
.EXPORT __systemstack, __systemstack_top
__systemstack_top:
#endif
- .SECTION USTACK, STACK, ALIGN=4
-#if STACK_RESERVE == ON
- .EXPORT __userstack, __userstack_top
- __userstack:
- .RES.B STACK_USR_SIZE
- __userstack_top:
-
-#endif
;=========================================================================================
; 6.2 Define Sections
;=========================================================================================
- .section DATA, data, align=4
- .section INIT, data, align=4
- .section IRAM, code, align=4
- .section CONST, const, align=4
- .section INTVECT, const, align=4
-
-#if I_RAM
- .import _RAM_IRAM
- .import _ROM_IRAM
-#endif
+ .section CODE, code, align=4
-#if (BOOT_FLASH_SEC == OFF)
- .data.w 0xFFFFFFFF
- .data.w 0xFFFFFFFF
- .data.w 0xFFFFFFFF
- .data.w 0xFFFFFFFF
-#else
- .res.w 4
-#endif
-
;-----------------------------------------------------------------------------------------
; MACRO Clear RC Watchdog
;-----------------------------------------------------------------------------------------
LDI #0x4C7,R7 ; clear RC watchdog
BANDL #0x7,@R7
#endm
-;-----------------------------------------------------------------------------------------
-; MACRO WAIT_LOOP
-;-----------------------------------------------------------------------------------------
-#macro wait_loop loop_number
-#local _wait64_loop
- LDI #loop_number, R0
-_wait64_loop:
- ADD #-1, R0
- BNE _wait64_loop
-#endm
- .section CODE, code, align=4
.section CODE_START, code, align=4
-#pragma section CODE=IRAM,attr=CODE
-
;=========================================================================================
; 7. S T A R T
ClearRCwatchdog ; clear harware watchdog
;=========================================================================================
-; 7.1 Initialise Stack Pointer and Table Base Register
+; 7.1 Initialise Stack Pointer
;=========================================================================================
#if STACKUSE == SYSSTACK
- ORCCR #0x20
- LDI #__userstack_top, SP ; initialize SP
- ANDCCR #0xDF
- LDI #__systemstack_top, SP ; initialize SP
-#endif
-
-#if STACKUSE == USRSTACK
ANDCCR #0xDF
LDI #__systemstack_top, SP ; initialize SP
- ORCCR #0x20
- LDI #__userstack_top, SP ; initialize SP
#endif
- LDI #INTVECT, R0 ; set Table Base
-smd_tbr:
- MOV R0, TBR
-
#if (CLOCKSOURCE != NOCLOCK)
;=========================================================================================
; 7.2 Check for CSV reset and set CSV
ORB R1, @R0 ; store data to CLKR register
#endif
-
-#if ENABLE_SUBCLOCK == ON
- LDI #0x0484, R0 ; Clock source control reg CLKR
- LDI #0x08, R1 ; enable subclock operation
- ORB R1, @R0 ; store data to CLKR register
- LDI #0x4CA, R0 ; Sub Clock oszilation
- LDI #0x00, R1 ; stabilitsation time = 32 ms
- AND R1, @R0
- BORH #0x02, @R0
-#endif
-
;=========================================================================================
; 7.6.5 Wait for PLL oscillation stabilisation
;=========================================================================================
LDI #CANCLOCK, R1 ; Load CANCLOCK
STB R1, @R0 ; set CANCLOCK
-;=========================================================================================
-; 7.6.6.4 Switch Main Clock Mode
-;=========================================================================================
-#if CLOCKSOURCE == MAINCLOCK
-
-;=========================================================================================
-; 7.6.6.5 Switch Subclock Mode
-;=========================================================================================
-#elif ( (CLOCKSOURCE == SUBCLOCK) )
- #if ENABLE_SUBCLOCK == ON
- LDI #0x4CA, R12
-subStabTime:
- ClearRCwatchdog ; clear harware watchdog
- BTSTH #8, @R12 ; wait until sub clock stabilisation
- BEQ subStabTime ; time is over
- LDI #0x0, R1
- STB R1, @R12
-
- LDI #0x0484, R0 ; Clock source control reg CLKR
- LDI #0x01, R1 ; load value to select main clock
- ORB R1, @R0 ; enable main clock (1/2 external)
- LDI #0x03, R1 ; load value to select subclock
- ORB R1, @R0 ; enable subclock as clock source
- #else
- #error: Wrong setting! The clock source is subclock, but the subclock is disabled.
- #endif
-
;=========================================================================================
; 7.6.7 Switch to PLL Mode
;=========================================================================================
-#elif ( (CLOCKSOURCE == MAINPLLCLOCK) )
+#if ( (CLOCKSOURCE == MAINPLLCLOCK) )
#if (DIV_G != 0x00)
LDI #0x0490, R0 ; PLL Ctrl Register
#endif
noClockStartup:
-
-;=========================================================================================
-; 7.7 Set BusInterface
-;=========================================================================================
-; Start restriction; No ext. bus interface
-#if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \
- (DEVICE != MB91463N) && (DEVICE != MB91465X)
-; End restriction
- NOP
-smd_cs_mb91461r:
-emu_sram_cs_mb91461r:
-smd_cs:
-
-#endif ; #endif (excl. devices)
- ClearRCwatchdog
-
-;=========================================================================================
-; 7.8 Copy code from Flash to I-RAM
-;=========================================================================================
-#if I_RAM == ON
- LDI #_RAM_IRAM, R0
- LDI #_ROM_IRAM, R1
- LDI #sizeof(IRAM), R13
- CMP #0, R13
- BEQ copy_iram_end
-copy_iram1:
- ADD #-1, R13
- LDUB @(R13, R1), R12
- BNE:D copy_iram1
- STB R12, @(R13, R0)
-copy_iram_end:
- ClearRCwatchdog
-#endif
-
-;=========================================================================================
-; Standard C startup
-;=========================================================================================
-;=========================================================================================
-; 7.10 Clear data
-;=========================================================================================
-; clear DATA section
-; According to ANSI, the DATA section must be cleared during start-up
- LDI:8 #0, R0
- LDI #sizeof DATA &~0x3, R1
- LDI #DATA, R13
- CMP #0, R1
- BEQ data_clr1
-data_clr0:
- ADD2 #-4, R1
- BNE:D data_clr0
- ST R0, @(R13, R1)
-data_clr1:
- LDI:8 #sizeof DATA & 0x3, R1
- LDI #DATA + (sizeof DATA & ~0x3), R13
-
- CMP #0, R1
- BEQ data_clr_end
-data_clr2:
- ADD2 #-1, R1
- BNE:D data_clr2
- STB R0, @(R13, R1)
-data_clr_end:
ClearRCwatchdog
-;=========================================================================================
-; 7.11 Copy Init section from ROM to RAM
-;=========================================================================================
-; copy rom
-; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
-; (start value)
-; The Application must copy the Section (Init) into the RAM area.
- LDI #_RAM_INIT, R0
- LDI #_ROM_INIT, R1
- LDI #sizeof(INIT), R2
- CMP #0, R2
- BEQ:D copy_rom_end
- LDI #3, R12
- AND R2, R12
- BEQ:D copy_rom2
- MOV R2, R13
- MOV R2, R3
- SUB R12, R3
-copy_rom1:
- ADD #-1, R13
- LDUB @(R13, R1), R12
- CMP R3, R13
- BHI:D copy_rom1
- STB R12, @(R13, R0)
- CMP #0, R3
- BEQ:D copy_rom_end
-copy_rom2:
- ADD #-4, R13
- LD @(R13, R1), R12
- BGT:D copy_rom2
- ST R12, @(R13, R0)
-copy_rom_end:
- ClearRCwatchdog
-
start_main:
;=========================================================================================
; 7.14 call main routine
projects / pyfrprog.git / blobdiff