Differences to the manual
-------------------------


# Port Data Register
  - Bitnames in headerfiles are D7 to D0

# ROM Select Register
  - ROMS, Bitnames in headerfile are D00 to D15

# CAN IFx Data A and Data B Registers IFxDTA_SWPyz
  - IFx Data A and Data B Registers with Little endian order are named IFxDTA_SWPyz
    for example CAN 0
        Hardware Manual: Address: 0x00C030H; Register Name: IF1DTA20
        Header File    : Address: 0x00C030H; Register Name: IF1DTA_SWP20 

# ADC Status Register, Timing Register, Enable Register and Data Register:
	- Status Register: ADCS (16Bit access) in HWM only 2 8Bit types ADCS0 and ADCS1
	- Data Register: ADCR (16Bit access) in HWM only 2 8Bit types ADCR1 and ADCR0
	- Timing Register: ADCT (16Bit access) in HWM only 2 8Bit types ADCT1 and ADCT0
	- Enable Register: ADER (32Bit access) in HWM only 2 16Bit types ADERL and ADERH