From: Bernhard Urban Date: Fri, 4 Sep 2009 22:20:36 +0000 (+0200) Subject: dirty ohci commit for thestack; nicer patch will follow X-Git-Tag: firstresponse~41 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=ppcskel.git;a=commitdiff_plain;h=bf20e0275f40af8a6c7db3bcbfbb20d930ff40a5 dirty ohci commit for thestack; nicer patch will follow --- diff --git a/irq.c b/irq.c index 449a85c..389ae75 100644 --- a/irq.c +++ b/irq.c @@ -54,8 +54,6 @@ void irq_handler(void) { u32 enabled = read32(BW_PI_IRQMASK); u32 flags = read32(BW_PI_IRQFLAG); - printf( "========================\n" - "flags1: 0x%08X\n", flags); flags = flags & enabled; @@ -67,7 +65,7 @@ void irq_handler(void) u32 hw_enabled = read32(HW_PPCIRQMASK); u32 hw_flags = read32(HW_PPCIRQFLAG); - printf("In IRQ handler: 0x%08x 0x%08x 0x%08x\n", hw_enabled, hw_flags, hw_flags & hw_enabled); + //printf("In IRQ handler: 0x%08x 0x%08x 0x%08x\n", hw_enabled, hw_flags, hw_flags & hw_enabled); hw_flags = hw_flags & hw_enabled; @@ -117,7 +115,6 @@ void irq_handler(void) write32(HW_PPCIRQFLAG, IRQF_OHCI0); } if (hw_flags & IRQF_OHCI1) { - printf("IRQ: OHCI1\n"); write32(HW_PPCIRQFLAG, IRQF_OHCI1); //TODO: ohci1_irq(); } @@ -128,12 +125,9 @@ void irq_handler(void) write32(HW_PPCIRQFLAG, hw_flags); } - printf("hw_flags1: 0x%08x\n", read32(HW_PPCIRQFLAG)); - // not necessary here, but "cleaner"? write32(BW_PI_IRQFLAG, 1< #include "bootmii_ppc.h" #include "ohci.h" #include "irq.h" +#include "string.h" #define gecko_printf printf #define dma_addr(address) virt_to_phys(address) @@ -39,14 +40,6 @@ static void dbg_op_state() { void ohci_init() { gecko_printf("ohci-- init\n"); dbg_op_state(); - /* - u32 i = 0; - for(; i <= 0x200; i+=4) { - gecko_printf("0x0d050000 + %X: %X\n", i, read32(0x0d050000+i)); - udelay(10000); //'cause usb gecko is lame - } - * see output in ohci.default - */ /* disable hc interrupts */ set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE); @@ -62,8 +55,38 @@ void ohci_init() { /* enable interrupts of both usb host controllers */ set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000); + + + u32 temp = 0; + u32 hcctrl = read32(OHCI0_HC_CONTROL); + switch(hcctrl & OHCI_CTRL_HCFS) { + case OHCI_USB_OPER: + temp = 0; + break; + case OHCI_USB_SUSPEND: + case OHCI_USB_RESUME: + hcctrl &= OHCI_CTRL_RWC; + hcctrl |= OHCI_USB_RESUME; + temp = 10; + break; + case OHCI_USB_RESET: + hcctrl &= OHCI_CTRL_RWC; + hcctrl |= OHCI_USB_RESET; + temp = 50; + break; + } + write32(OHCI0_HC_CONTROL, hcctrl); + (void) read32(OHCI0_HC_CONTROL); + udelay(temp*1000); + + memset(&hcca_oh0, 0, sizeof(struct ohci_hcca)); + + + dbg_op_state(); + + /* reset HC */ - set32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR); + write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR); /* wait max. 30us */ u32 ts = 30; @@ -93,8 +116,7 @@ void ohci_init() { /* set periodicstart */ #define FIT (1<<31) u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff; - printf("OHCI0_HC_FMINTERVAL: %08X OCHI0_HC_FMINTERVAL&0x3fff: %08X\n", read32(OHCI0_HC_FM_INTERVAL), fmInterval); - u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT; + u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT; write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT)); write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff); @@ -105,7 +127,7 @@ void ohci_init() { } /* start HC operations */ - set32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER); + write32(OHCI0_HC_CONTROL, (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_RWC) | OHCI_CONTROL_INIT | OHCI_USB_OPER); /* wake on ConnectStatusChange, matching external hubs */ set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);