u8 what [4]; /* spec only identifies 252 bytes :) */
} ALIGNED(256);
+struct endpoint_descriptor {
+ u32 flags;
+ u32 tailp;
+ u32 headp;
+ u32 nexted;
+} ALIGNED(16);
+
+#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f
+#define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f)
+#define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s)
+#define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf)
+#define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7)
+#define OHCI_ENDPOINT_DIRECTION_MASK 0x00001800
+#define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000
+#define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800
+#define OHCI_ENDPOINT_DIRECTION_IN 0x00001000
+#define OHCI_ENDPOINT_LOW_SPEED 0x00002000
+#define OHCI_ENDPOINT_FULL_SPEED 0x00000000
+#define OHCI_ENDPOINT_SKIP 0x00004000
+#define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000
+#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000
+#define OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK (0x7ff << 16)
+#define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff)
+#define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16)
+#define OHCI_ENDPOINT_HALTED 0x00000001
+#define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002
+#define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc
+
+
+struct general_td {
+ u32 flags;
+ u32 cbp;
+ u32 nexttd;
+ u32 be;
+} ALIGNED(16);
+
+#define OHCI_TD_BUFFER_ROUNDING 0x00040000
+#define OHCI_TD_DIRECTION_PID_MASK 0x00180000
+#define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
+#define OHCI_TD_DIRECTION_PID_OUT 0x00080000
+#define OHCI_TD_DIRECTION_PID_IN 0x00100000
+#define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
+#define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
+#define OHCI_TD_INTERRUPT_MASK 0x00e00000
+#define OHCI_TD_TOGGLE_CARRY 0x00000000
+#define OHCI_TD_TOGGLE_0 0x02000000
+#define OHCI_TD_TOGGLE_1 0x03000000
+#define OHCI_TD_TOGGLE_MASK 0x03000000
+#define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3)
+#define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28)
+#define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28)
+#define OHCI_TD_CONDITION_CODE_MASK 0xf0000000
+
+#define OHCI_TD_INTERRUPT_IMMEDIATE 0x00
+#define OHCI_TD_INTERRUPT_NONE 0x07
+
+#define OHCI_TD_CONDITION_NO_ERROR 0x00
+#define OHCI_TD_CONDITION_CRC_ERROR 0x01
+#define OHCI_TD_CONDITION_BIT_STUFFING 0x02
+#define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
+#define OHCI_TD_CONDITION_STALL 0x04
+#define OHCI_TD_CONDITION_NO_RESPONSE 0x05
+#define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
+#define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
+#define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
+#define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
+#define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c
+#define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d
+#define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f
+
#endif