/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT (3 << 0)
#define OHCI_INTR_INIT \
- (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
- | OHCI_INTR_RD | OHCI_INTR_WDH)
+ (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE)
/* OHCI ROOT HUB REGISTER MASKS */
} ALIGNED(256);
struct endpoint_descriptor {
+ /* required by HC */
u32 flags;
u32 tailp;
u32 headp;
u32 nexted;
+
+ /* required by software */
+ u32 tdcount;
+ u8 type;
} ALIGNED(16);
#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f
/* required by software */
u32 bufaddr;
- u16 buflen;
+ u32 buflen;
+ u32 pad1;
+ u32 pad2;
} ALIGNED(16);
#define OHCI_TD_BUFFER_ROUNDING 0x00040000