#include "host.h"
#include "../usbspec/usb11spec.h"
+/* activate control_quirk */
+#define _USE_C_Q
+
/* macro for accessing u32 variables that need to be in little endian byte order;
*
* whenever you read or write from an u32 field that the ohci host controller
(((dword) & 0x0000FF00) << 8) | \
(((dword) & 0x000000FF) << 24) )
-static struct endpoint_descriptor *allocate_endpoint();
static struct general_td *allocate_general_td();
-static void control_quirk();
static void dbg_op_state();
-//static void dbg_td_flag(u32 flag);
static void configure_ports(u8 from_init);
static void setup_port(u32 reg, u8 from_init);
static struct ohci_hcca hcca_oh0;
-static struct endpoint_descriptor *allocate_endpoint()
-{
- struct endpoint_descriptor *ep;
- ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
- memset(ep, 0, sizeof(struct endpoint_descriptor));
- ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
- ep->headp = ep->tailp = ep->nexted = LE(0);
- return ep;
-}
-
static struct general_td *allocate_general_td()
{
struct general_td *td;
return td;
}
-static void control_quirk()
-{
- static struct endpoint_descriptor *ed = 0; /* empty ED */
- static struct general_td *td = 0; /* dummy TD */
- u32 head;
- u32 current;
- u32 status;
-
- /*
- * One time only.
- * Allocate and keep a special empty ED with just a dummy TD.
- */
- if (!ed) {
- ed = allocate_endpoint();
- if (!ed)
- return;
-
- td = allocate_general_td(0);
- if (!td) {
- free(ed);
- ed = NULL;
- return;
- }
-
- ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
- ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
- }
-
- /*
- * The OHCI USB host controllers on the Nintendo Wii
- * video game console stop working when new TDs are
- * added to a scheduled control ED after a transfer has
- * has taken place on it.
- *
- * Before scheduling any new control TD, we make the
- * controller happy by always loading a special control ED
- * with a single dummy TD and letting the controller attempt
- * the transfer.
- * The controller won't do anything with it, as the special
- * ED has no TDs, but it will keep the controller from failing
- * on the next transfer.
- */
- head = read32(OHCI0_HC_CTRL_HEAD_ED);
- if (head) {
- printf("head: 0x%08X\n", head);
- /*
- * Load the special empty ED and tell the controller to
- * process the control list.
- */
- sync_after_write(ed, 16);
- sync_after_write(td, 16);
- write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
-
- status = read32(OHCI0_HC_CONTROL);
- set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
- write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
-
- /* spin until the controller is done with the control list */
- current = read32(OHCI0_HC_CTRL_CURRENT_ED);
- while(!current) {
- udelay(10);
- current = read32(OHCI0_HC_CTRL_CURRENT_ED);
- }
-
- printf("current: 0x%08X\n", current);
-
- /* restore the old control head and control settings */
- write32(OHCI0_HC_CONTROL, status);
- write32(OHCI0_HC_CTRL_HEAD_ED, head);
- } else {
- printf("nohead!\n");
- }
-}
-
static void dbg_op_state()
{
}
}
+#ifdef _DU_OHCI_F_HALT
static void dbg_td_flag(u32 flag)
{
printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
printf(" R: %X\n", (flag>>18)&1);
printf("********************************************************\n");
}
+#endif
-static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
+static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
{
if(src->actlen) {
dest->cbp = LE(virt_to_phys(src->buffer));
dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
switch(src->pid) {
case USB_PID_SETUP:
+#ifdef _DU_OHCI_Q
printf("pid_setup\n");
+#endif
dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
dest->flags |= LE(OHCI_TD_TOGGLE_0);
dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
break;
case USB_PID_OUT:
+#ifdef _DU_OHCI_Q
printf("pid_out\n");
+#endif
dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
dest->flags |= LE(OHCI_TD_TOGGLE_1);
break;
case USB_PID_IN:
+#ifdef _DU_OHCI_Q
printf("pid_in\n");
+#endif
dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
- dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
+ if(src->maxp > src->actlen) {
+ dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
+#ifdef _DU_OHCI_Q
+ printf("round buffer!\n");
+#endif
+ }
/*
* let the endpoint do the togglestuff!
* TODO: just temporary solution!
* there can be also inregular PID_IN pakets (@Status Stage)
*/
dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
-#if 0
- /* should be done by HC!
- * first pid_in start with DATA0 */
- */
- dummyconfig.headp = LE( src->togl ?
- LE(dummyconfig.headp) | OHCI_ENDPOINT_TOGGLE_CARRY :
- LE(dummyconfig.headp) & ~OHCI_ENDPOINT_TOGGLE_CARRY);
-#endif
break;
}
dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
}
+#ifdef _DU_OHCI_F_HALT
static void dump_address(void *addr, u32 size, const char* str)
{
printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
hexdump(addr, size);
}
+#endif
+static struct endpoint_descriptor _edhead;
struct endpoint_descriptor *edhead = 0;
void hcdi_fire()
{
+#ifdef _DU_OHCI_F
printf("<^> <^> <^> hcdi_fire(start)\n");
+#endif
if(edhead == 0)
return;
- control_quirk(); //required? YES! :O ... erm... or no? :/ ... in fact I have no idea
+#ifdef _USE_C_Q
+ /* quirk... 11ms seems to be a minimum :O */
+ udelay(11000);
+#endif
+
write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
/* sync it all */
sync_after_write(edhead, sizeof(struct endpoint_descriptor));
+#ifdef _DU_OHCI_F
dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
+#endif
struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
- printf("STRUCT LEN: %d\n", sizeof(struct general_td));
while(virt_to_phys(x)) {
sync_after_write(x, sizeof(struct general_td));
+#ifdef _DU_OHCI_F
dump_address(x, sizeof(struct general_td), "x(before)");
+#endif
if(x->buflen > 0) {
sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
+#ifdef _DU_OHCI_F
dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
+#endif
}
x = phys_to_virt(LE(x->nexttd));
}
set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
+ struct general_td *n=0, *prev = 0, *next = 0;
/* poll until edhead->headp is null */
do {
sync_before_read(edhead, sizeof(struct endpoint_descriptor));
+#ifdef _DU_OHCI_F
printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
+ udelay(10000);
+#endif
+
+ /* if halted, debug output plz. will break the transfer */
+ if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
+ n = phys_to_virt(LE(edhead->headp)&~0xf);
+ prev = phys_to_virt((u32)prev);
+#ifdef _DU_OHCI_F_HALT
+ printf("halted!\n");
+#endif
+
+ sync_before_read((void*) n, sizeof(struct general_td));
+#ifdef _DU_OHCI_F_HALT
+ printf("n: 0x%08X\n", n);
+ dump_address(n, sizeof(struct general_td), "n(after)");
+#endif
+ if(n->buflen > 0) {
+ sync_before_read((void*) n->bufaddr, n->buflen);
+#ifdef _DU_OHCI_F_HALT
+ dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
+#endif
+ }
+#ifdef _DU_OHCI_F_HALT
+ dbg_td_flag(LE(n->flags));
+#endif
+
+ sync_before_read((void*) prev, sizeof(struct general_td));
+#ifdef _DU_OHCI_F_HALT
+ printf("prev: 0x%08X\n", prev);
+ dump_address(prev, sizeof(struct general_td), "prev(after)");
+#endif
+ if(prev->buflen >0) {
+ sync_before_read((void*) prev->bufaddr, prev->buflen);
+#ifdef _DU_OHCI_F_HALT
+ dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
+#endif
+ }
+#ifdef _DU_OHCI_F_HALT
+ dbg_td_flag(LE(prev->flags));
+ printf("halted end!\n");
+#endif
+ return;
+ }
+ prev = (struct general_td*) (LE(edhead->headp)&~0xf);
} while(LE(edhead->headp)&~0xf);
- struct general_td *n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
+ n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
+#ifdef _DU_OHCI_F
printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
+#endif
- struct general_td *prev = 0, *next = 0;
+ prev = 0; next = 0;
/* reverse done queue */
while(virt_to_phys(n) && edhead->tdcount) {
sync_before_read((void*) n, sizeof(struct general_td));
+#ifdef _DU_OHCI_F
printf("n: 0x%08X\n", n);
printf("next: 0x%08X\n", next);
printf("prev: 0x%08X\n", prev);
+#endif
next = n;
n = (struct general_td*) phys_to_virt(LE(n->nexttd));
n = next;
prev = 0;
while(virt_to_phys(n)) {
+#ifdef _DU_OHCI_F
dump_address(n, sizeof(struct general_td), "n(after)");
-
+#endif
if(n->buflen > 0) {
sync_before_read((void*) n->bufaddr, n->buflen);
+#ifdef _DU_OHCI_F
dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
+#endif
}
+#ifdef _DU_OHCI_F
dbg_td_flag(LE(n->flags));
+#endif
prev = n;
n = (struct general_td*) n->nexttd;
free(prev);
write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
- free(edhead);
edhead = 0;
+#ifdef _DU_OHCI_F
printf("<^> <^> <^> hcdi_fire(end)\n");
+#endif
}
/**
* Enqueue a transfer descriptor.
*/
-u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
+u8 hcdi_enqueue(const struct usb_transfer_descriptor *td) {
+#ifdef _DU_OHCI_Q
printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
+#endif
if(!edhead) {
- edhead = allocate_endpoint();
+ edhead = &_edhead;
+ memset(edhead, 0, sizeof(struct endpoint_descriptor));
edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
edhead->headp = edhead->tailp = edhead->nexted = LE(0);
- edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
- OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
+ if(td->fullspeed) {
+ edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
+ } else {
+ edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
+ }
+ edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
edhead->tdcount = 0;
n = phys_to_virt(LE(n->nexttd));
}
n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
+#ifdef _DU_OHCI_Q
printf("n: 0x%08X\n", n);
printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
+#endif
}
+#ifdef _DU_OHCI_Q
printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
+#endif
return 0;
}
/**
* Remove an transfer descriptor from transfer queue.
*/
-u8 hcdi_dequeue(usb_transfer_descriptor *td) {
+u8 hcdi_dequeue(struct usb_transfer_descriptor *td) {
return 0;
}
/* disable hc interrupts */
set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
-#if 1
- /* after a warm start we have some really odd memory issues.
- * some malloc/free/sync/mmu fail?! no idea!
- */
- if((read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) != OHCI_USB_RESET) {
- (void) malloc(256);
- printf("WTF malloc\n");
- }
-#endif
-
/* save fmInterval and calculate FSMPS */
#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
#define FI 0x2edf /* 12000 bits per frame (-1) */
static void configure_ports(u8 from_init)
{
+#ifdef _DU_OHCI_RH
printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
+#endif
setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
+#ifdef _DU_OHCI_RH
printf("configure_ports done\n");
+#endif
}
static void setup_port(u32 reg, u8 from_init)
/* clear CSC flag, set PES and start port reset (PRS) */
write32(reg, RH_PS_PES);
while(!(read32(reg) & RH_PS_PES)) {
+#ifdef _DU_OHCI_RH
printf("fu\n");
+#endif
return;
}
/* spin until port reset is complete */
while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
+#ifdef _DU_OHCI_RH
printf("loop done\n");
+#endif
- (void) usb_add_device();
+ /* returns usb_device struct */
+ (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8);
}
}
projects / ppcskel.git / blobdiff