#include "bootmii_ppc.h"
#include "ohci.h"
+#include "irq.h"
+#include "string.h"
#define gecko_printf printf
-#define set32(address, flags) write32(address, read32(address) | flags)
-#define dma_addr(address) (u32)address
-
-/* stolen from libogc - gc/ogc/machine/processor.h */
-#define _CPU_ISR_Disable( _isr_cookie ) \
- { register u32 _disable_mask = 0; \
- _isr_cookie = 0; \
- __asm__ __volatile__ ( \
- "mfmsr %0\n" \
- "rlwinm %1,%0,0,17,15\n" \
- "mtmsr %1\n" \
- "extrwi %0,%0,1,16" \
- : "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) \
- : "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- }
-
-#define _CPU_ISR_Restore( _isr_cookie ) \
- { register u32 _enable_mask = 0; \
- __asm__ __volatile__ ( \
- " cmpwi %0,0\n" \
- " beq 1f\n" \
- " mfmsr %1\n" \
- " ori %1,%1,0x8000\n" \
- " mtmsr %1\n" \
- "1:" \
- : "=r"((_isr_cookie)),"=&r" ((_enable_mask)) \
- : "0"((_isr_cookie)),"1" ((_enable_mask)) \
- ); \
- }
+#define dma_addr(address) virt_to_phys(address)
static struct ohci_hcca hcca_oh0;
void ohci_init() {
gecko_printf("ohci-- init\n");
dbg_op_state();
- /*
- u32 i = 0;
- for(; i <= 0x200; i+=4) {
- gecko_printf("0x0d050000 + %X: %X\n", i, read32(0x0d050000+i));
- udelay(10000); //'cause usb gecko is lame
- }
- * see output in ohci.default
- */
+
+ /* disable hc interrupts */
+ set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
+
+ /* save fmInterval and calculate FSMPS */
+#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
+#define FI 0x2edf /* 12000 bits per frame (-1) */
+ u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
+ if(fmint != FI)
+ gecko_printf("ohci-- fminterval delta: %d\n", fmint - FI);
+ fmint |= FSMP (fmint) << 16;
/* enable interrupts of both usb host controllers */
set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
+
+
+ u32 temp = 0;
+ u32 hcctrl = read32(OHCI0_HC_CONTROL);
+ switch(hcctrl & OHCI_CTRL_HCFS) {
+ case OHCI_USB_OPER:
+ temp = 0;
+ break;
+ case OHCI_USB_SUSPEND:
+ case OHCI_USB_RESUME:
+ hcctrl &= OHCI_CTRL_RWC;
+ hcctrl |= OHCI_USB_RESUME;
+ temp = 10;
+ break;
+ case OHCI_USB_RESET:
+ hcctrl &= OHCI_CTRL_RWC;
+ hcctrl |= OHCI_USB_RESET;
+ temp = 50;
+ break;
+ }
+ write32(OHCI0_HC_CONTROL, hcctrl);
+ (void) read32(OHCI0_HC_CONTROL);
+ udelay(temp*1000);
+
+ memset(&hcca_oh0, 0, sizeof(struct ohci_hcca));
+
+
+ dbg_op_state();
+
+
/* reset HC */
- set32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
+ write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
/* wait max. 30us */
u32 ts = 30;
within 2msec else HC enters RESUME */
- //u32 cookie = irq_kill();
- u32 cookie;
- _CPU_ISR_Disable(cookie);
-
+ u32 cookie = irq_kill();
/* Tell the controller where the control and bulk lists are
* The lists are empty now. */
/* set periodicstart */
#define FIT (1<<31)
u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
- u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
+ u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
- write32(OHCI0_HC_FM_INTERVAL, read32(OHCI0_HC_FM_INTERVAL) | (fit ^ FIT));
+ write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
/* testing bla */
}
/* start HC operations */
- set32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
+ write32(OHCI0_HC_CONTROL, (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_RWC) | OHCI_CONTROL_INIT | OHCI_USB_OPER);
/* wake on ConnectStatusChange, matching external hubs */
set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
- //irq_restore(cookie);
- _CPU_ISR_Restore(cookie);
-
+ irq_restore(cookie);
dbg_op_state();
+}
+void ohci0_irq() {
+ gecko_printf("ohci_irq\n");
+ write32(OHCI0_HC_INT_STATUS, ~0);
}
+