From d75d3fb65ad33c25a042c6679d6814433edaa196 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Wed, 19 May 2010 19:31:35 +0200 Subject: [PATCH] display/history: komisches init verhalten ausserdem sollen vorerst nur 71byte ram verwendet werden. --- src/beh_history_tb.vhd | 1 - src/display.vhd | 9 +++++++-- src/gen_pkg.vhd | 4 ++-- src/history.vhd | 18 +++++++++--------- 4 files changed, 18 insertions(+), 14 deletions(-) diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index cdd6e2a..e30ad07 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -85,7 +85,6 @@ begin s_char <= hbyte(to_unsigned(character'pos(ctmp),8)); wait on s_done; s_take <= '0'; - wait on d_new_eingabe; icwait(sys_clk, 2); j := 1; while j <= i loop diff --git a/src/display.vhd b/src/display.vhd index 8fca39c..17a717e 100644 --- a/src/display.vhd +++ b/src/display.vhd @@ -26,7 +26,7 @@ entity display is end entity display; architecture beh of display is - type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH, + type DISPLAY_STATE is (S_INIT, SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1); signal state_int, state_next : DISPLAY_STATE; signal d_zeile_int, d_zeile_next : hzeile; @@ -45,7 +45,7 @@ begin begin if sys_res_n = '0' then -- internal - state_int <= SIDLE; + state_int <= S_INIT; -- out d_zeile_int <= (others => '0'); d_spalte_int <= (others => '0'); @@ -71,6 +71,8 @@ begin state_next <= state_int; case state_int is + when S_INIT => + state_next <= SIDLE; when SIDLE => if d_new_eingabe = '1' then state_next <= S_NEW_INPUT; @@ -129,6 +131,9 @@ begin command_data_next <= command_data_int; case state_int is + when S_INIT => + d_spalte_next <= (others => '0'); + d_zeile_next <= (others => '0'); when SIDLE => null; when S_NEW_INPUT => diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index cf80155..0236b72 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -18,8 +18,8 @@ package gen_pkg is -- integer ist 32bit (31bit + sign) subtype cinteger is integer; - -- vorerst: 2 * 71 - constant H_RAM_SIZE : integer := 142; + -- vorerst: 1 * 71 + constant H_RAM_SIZE : integer := 71; -- danach: 50 * 71 * 2 = 7100 -- constant H_RAM_SIZE : integer := 7100; constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE); diff --git a/src/history.vhd b/src/history.vhd index c9f5656..1c69612 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -102,12 +102,12 @@ begin case state_int is when SIDLE => -- S_S_FIN: tmp.. - if d_get = '1' then - state_next <= S_D_INIT; + if s_take = '1' then + state_next <= S_S_INIT; elsif do_it = '1' then state_next <= S_S_FIN; - elsif s_take = '1' then - state_next <= S_S_INIT; + elsif d_get = '1' then + state_next <= S_D_INIT; end if; when S_S_INIT => if s_backspace = '1' then @@ -158,13 +158,13 @@ begin when S_S_INIT => null; when S_S_WRITE => - -- wr_next <= '1'; - address_next <= '0' & s_cnt_int; + wr_next <= '1'; + address_next <= s_cnt_int; data_in_next <= s_char; s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); when S_S_BS => - -- wr_next <= '1'; - address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1); + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(s_cnt_int) - 1); data_in_next <= (others => '0'); if unsigned(s_cnt_int) /= 0 then s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1); @@ -178,7 +178,7 @@ begin d_new_eingabe_next <= '1'; when S_D_INIT => - address_next <= '0' & d_spalte; + address_next <= d_spalte; d_new_eingabe_next <= '0'; d_new_result_next <= '0'; when S_D_WAIT => -- 2.25.1