From cea82ae4c0bea03d5fef0d0930d1d38082d0a831 Mon Sep 17 00:00:00 2001 From: Alexander Oh Date: Thu, 27 May 2010 03:04:42 +0200 Subject: [PATCH] cleanup of warnings and latches and possible gated clocks --- src/history.vhd | 2 +- src/pc_communication.vhd | 30 +++++------------------------- 2 files changed, 6 insertions(+), 26 deletions(-) diff --git a/src/history.vhd b/src/history.vhd index 424d0c9..e260583 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -222,7 +222,7 @@ begin process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int, data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int, was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int, - p_write, p_sp_read_int, p_sp_write_int) + p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte) variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0); variable spalte_tmp : hspalte; variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0); diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd index 8c48088..610ec68 100644 --- a/src/pc_communication.vhd +++ b/src/pc_communication.vhd @@ -30,8 +30,6 @@ entity pc_communication is end entity pc_communication; architecture beh of pc_communication is - signal push_history, push_history_next : std_logic; - signal spalte, spalte_next : integer range 1 to hspalte_max + 1; signal zeile , zeile_next : integer range 1 to hzeile_max + 1; signal spalte_up, spalte_up_next : std_logic; @@ -39,7 +37,6 @@ architecture beh of pc_communication is signal new_i, new_i_next : std_logic; signal tx_done_i, tx_done_i_next : std_logic; signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0); - signal d_done_i : std_logic; signal s_done, s_done_next : std_logic; signal char, char_next : hbyte; @@ -55,7 +52,6 @@ begin d_get <= get; char_next <= d_char; tx_new <= new_i; - d_done_i <= d_done; tx_done_i_next <= tx_done; tx_data <= tx_data_i; @@ -63,7 +59,6 @@ begin begin if sys_res_n = '0' then state <= IDLE; - push_history <= '0'; spalte <= 1; zeile <= 1; get <= '0'; @@ -73,7 +68,6 @@ begin tx_done_i <= '0'; s_done <= '0'; elsif rising_edge(sys_clk) then - push_history <= push_history_next; spalte <= spalte_next; zeile <= zeile_next; state <= state_next; @@ -89,22 +83,7 @@ begin end if; end process sync; - async_push_history : process (rx_new, rx_data, btn_a) - begin - if rx_new = '1' then - if rx_data = X"41" then - push_history_next <= '1'; - else - push_history_next <= '0'; - end if; - elsif btn_a = '1' then - push_history_next <= '1'; - else - push_history_next <= '0'; - end if; - end process async_push_history; - - output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up) + output_pc : process (state, zeile, spalte, char, tx_data_i, tx_done_i, spalte_up) begin get_next <= '0'; new_i_next <= '0'; @@ -114,6 +93,7 @@ begin spalte_next <= spalte; zeile_next <= zeile; tx_data_i_next <= tx_data_i; + char_en <= '0'; if spalte_up = '1' then if spalte = hspalte_max then @@ -138,7 +118,6 @@ begin get_next <= '1'; char_en <= '1'; when FORWARD => - char_en <= '0'; tx_data_i_next <= char; new_i_next <= '1'; if (tx_done_i = '1') then @@ -150,11 +129,12 @@ begin end case; end process output_pc; - next_state_pc : process (rx_new, btn_a, d_done, tx_done_i, s_done) + next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done) begin + state_next <= state; case state is when IDLE => - if rx_new = '1' or btn_a = '1' then + if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then state_next <= FETCH; end if; when FETCH => -- 2.25.1