From c4835e02b7f9b0d71547aec609667b7b5aed75ce Mon Sep 17 00:00:00 2001 From: Alexander Oh Date: Thu, 27 May 2010 07:37:10 +0200 Subject: [PATCH] inserting a dummy state --- src/beh_history_tb.vhd | 3 +++ src/history.vhd | 10 +++++++--- src/pc_communication.vhd | 5 +++-- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index eaa4fe3..d05236a 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -50,6 +50,8 @@ architecture sim of beh_history_tb is --dummy button signal btn_a_int : std_logic; + --output beautifier + signal tx_debug : character; signal stop : boolean := false; begin @@ -177,6 +179,7 @@ begin pc_char => pc_char, pc_busy => pc_busy ); + tx_debug <= character'val(to_integer(unsigned(tx_data))); process begin diff --git a/src/history.vhd b/src/history.vhd index 46acf19..ddd26f6 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -42,7 +42,7 @@ end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE, - S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ); + S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -201,9 +201,11 @@ begin state_next <= SIDLE; end if; when S_PC_INIT => + state_next <= S_PC_DUMMY; + when S_PC_DUMMY => state_next <= S_PC_READ; when S_PC_READ => - if d_get = '0' then + if pc_get = '0' then state_next <= SIDLE; end if; when S_P_READ => @@ -245,7 +247,7 @@ begin address_next <= address_int; data_in_next <= data_in_int; pc_done_next <= '0'; - pc_char_next <= pc_char_int; --(others => '0'); + pc_char_next <= pc_char_int; pc_busy_next <= '0'; p_rdone_next <= p_rdone_int; p_wdone_next <= p_wdone_int; @@ -356,6 +358,8 @@ begin addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte)); address_next <= addr_tmp; pc_busy_next <= '1'; + when S_PC_DUMMY => + pc_busy_next <= '1'; when S_PC_READ => pc_char_next <= data_out; pc_done_next <= '1'; diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd index 89dff25..dcdb060 100644 --- a/src/pc_communication.vhd +++ b/src/pc_communication.vhd @@ -87,13 +87,14 @@ begin when FETCH => get_next <= '1'; when WAIT_HIST => - tx_data_i_next <= pc_char; + tx_data_i_next <= pc_char; when FORWARD => new_i_next <= '1'; when WAIT_UART => null; when UART_DONE => if tx_data_i = x"00" or spalte = hspalte_max then + tx_data_i_next <= x"0a"; zeile_next <= zeile + 1; spalte_next <= 1; if zeile = hzeile_max then @@ -105,7 +106,7 @@ begin end case; end process output_pc; - next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, + next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile) begin state_next <= state; -- 2.25.1