From aca9c1f209b80c70a5768b3896f23acd16e22490 Mon Sep 17 00:00:00 2001
From: Bernhard Urban <lewurm@gmail.com>
Date: Wed, 19 May 2010 16:17:00 +0200
Subject: [PATCH] display: nicht jede zeile neu... ausserdem vorerst fixe werte
 im ram

---
 src/display.vhd | 13 +++++++------
 src/history.vhd |  4 ++--
 src/sp_ram.vhd  |  3 ++-
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/display.vhd b/src/display.vhd
index d01b115..507c739 100644
--- a/src/display.vhd
+++ b/src/display.vhd
@@ -108,11 +108,12 @@ begin
 				end if;
 			when S_NOP1 =>
 				if free = '1' then
-					if unsigned(d_spalte_int) = 71 then
-						state_next <= SIDLE;
-					else
-						state_next <= S_COUNTUP;
-					end if;
+					state_next <= SIDLE;
+					--if unsigned(d_spalte_int) = 71 then
+					--	state_next <= SIDLE;
+					--else
+					--	state_next <= S_COUNTUP;
+					--end if;
 				end if;
 		end case;
 	end process;
@@ -131,7 +132,7 @@ begin
 			when SIDLE =>
 				null;
 			when S_NEW_INPUT =>
-				d_spalte_next <= (others => '0');
+				null;
 			when S_NEW_RESULT =>
 				d_spalte_next <= (others => '0');
 				case d_zeile_int is
diff --git a/src/history.vhd b/src/history.vhd
index cd6dbcd..4572456 100644
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -158,12 +158,12 @@ begin
 			when S_S_INIT =>
 				null;
 			when S_S_WRITE =>
-				wr_next <= '1';
+				-- wr_next <= '1';
 				address_next <= '0' & s_cnt_int;
 				data_in_next <= s_char;
 				s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
 			when S_S_BS =>
-				wr_next <= '1';
+				-- wr_next <= '1';
 				address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1);
 				data_in_next <= (others => '0');
 				if unsigned(s_cnt_int) /= 0 then
diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index 4d39020..de0f668 100644
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -20,7 +20,8 @@ end entity sp_ram;
 architecture beh of sp_ram is
 	subtype RAM_ENTRY_TYPE is hbyte;
 	type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
-	signal ram : RAM_TYPE := (others => x"00");
+	signal ram : RAM_TYPE := (1 => x"41", 2 => x"42", 3 => x"43", 4 => x"44",
+	5 => x"45", 6 => x"46", 7 => x"47", 8 => x"48", 9 => x"49", 10 => x"50", others => x"00");
 begin
 	process(sys_clk)
 	begin
-- 
2.25.1