From 9bbe2b05fdf9bce3b58a2cabd54f69da1d09e4f8 Mon Sep 17 00:00:00 2001
From: Bernhard Urban <lewurm@gmail.com>
Date: Sat, 10 Apr 2010 21:45:23 +0200
Subject: [PATCH] quartus fuer windows: o cmd starten und windows.cmd
 ausfuehren o ins erstellte projekt verzeichnis (quartus/calc) und calc.qpf
 (quartus projektfile) oeffnen

---
 .gitignore          |  3 +++
 quartus/project.tcl | 58 +++++++++++++++++++++++++++++++++++++++++++++
 quartus/windows.cmd |  4 ++++
 src/calc.vhd        | 18 +++++++++-----
 4 files changed, 77 insertions(+), 6 deletions(-)
 create mode 100644 quartus/project.tcl
 create mode 100644 quartus/windows.cmd

diff --git a/.gitignore b/.gitignore
index adcd924..42d40cc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -18,3 +18,6 @@ sim/
 
 #modelsim
 src/transcript
+
+#quartus
+quartus/calc/
diff --git a/quartus/project.tcl b/quartus/project.tcl
new file mode 100644
index 0000000..5097c58
--- /dev/null
+++ b/quartus/project.tcl
@@ -0,0 +1,58 @@
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "calc"]} {
+		puts "Project calc is not open"
+		set make_assignments 0
+	}
+} else {
+	# Only open if not already open
+	if {[project_exists calc]} {
+		project_open -revision calc calc
+	} else {
+		project_new -revision calc calc
+	}
+	set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+	set_global_assignment -name FAMILY Stratix
+	set_global_assignment -name DEVICE EP1S10F672C6
+	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+	set_global_assignment -name MISC_FILE "calc.dpf"
+	set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+	set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+	set_global_assignment -name TOP_LEVEL_ENTITY calc
+	set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
+	set_global_assignment -name VHDL_FILE ../../src/calc.vhd
+	set_global_assignment -name VHDL_FILE ../../src/alu.vhd
+
+	set_location_assignment PIN_N3 -to sys_clk
+	set_location_assignment PIN_AF17 -to sys_res_n
+
+	set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
+	set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+
+	set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+	set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# Commit assignments
+	export_assignments
+
+	# Close project
+	if {$need_to_close_project} {
+		project_close
+	}
+}
diff --git a/quartus/windows.cmd b/quartus/windows.cmd
new file mode 100644
index 0000000..41938be
--- /dev/null
+++ b/quartus/windows.cmd
@@ -0,0 +1,4 @@
+md calc
+cd calc
+quartus_sh -t ..\project.tcl
+cd ..
diff --git a/src/calc.vhd b/src/calc.vhd
index c17199c..7347002 100644
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -44,14 +44,20 @@ begin
 		opcode => opcode
 	);
 
-	process
+	process (sys_clk, sys_res_n)
 	begin
-		op1 <= op3;
-		opcode <= DIV;
-		op2 <= to_signed(2,CBITS);
+		if sys_res_n = '0' then
+			op1 <= (others => '0');
+			opcode <= NOP;
+			op2 <= (others => '0');
+			do_calc <= '0';
+		elsif rising_edge(sys_clk) then
+			op1 <= op3;
+			opcode <= DIV;
+			op2 <= to_signed(2,CBITS);
 
-		do_calc <= calc_done;
-		wait until sys_clk = '1';
+			do_calc <= calc_done;
+		end if;
 	end process;
 end architecture top;
 
-- 
2.25.1