From 93dc6bc02ca94deeb68534a7a17191ea5494be83 Mon Sep 17 00:00:00 2001
From: Bernhard Urban <lewurm@gmail.com>
Date: Tue, 25 May 2010 20:02:51 +0200
Subject: [PATCH] rs232: mapping fuer uart

---
 quartus/project_gen.tcl |  6 +++++
 src/calc.vhd            | 51 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index 242d42b..a6204ef 100644
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -49,6 +49,8 @@ if {$make_assignments} {
 	set_global_assignment -name VHDL_FILE ../../src/history.vhd
 	set_global_assignment -name VHDL_FILE ../../src/calc.vhd
 	set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
+	set_global_assignment -name VHDL_FILE ../../src/uart_tx.vhd
+	set_global_assignment -name VHDL_FILE ../../src/uart_rx.vhd
 	
 	#vga ip-core
 	set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
@@ -118,6 +120,10 @@ if {$make_assignments} {
 	set_location_assignment PIN_Y26 -to ps2_clk
 	set_location_assignment PIN_E21 -to ps2_data
 
+	#rs232
+	set_location_assignment PIN_D22 -to txd
+	set_location_assignment PIN_D23 -to rxd
+
 	set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
 	set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
 	#warning fix fuer pll
diff --git a/src/calc.vhd b/src/calc.vhd
index cdee994..bd4e903 100644
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -16,7 +16,8 @@ entity calc is
 		-- btnA
 		-- TODO: pins
 		-- rs232
-		-- TODO: pins
+		rxd : in std_logic;
+		txd : out std_logic;
 		-- vga
 		vsync_n : out std_logic;
 		hsync_n : out std_logic;
@@ -59,6 +60,12 @@ architecture top of calc is
 	signal do_it, finished : std_logic;
 	-- debouncing
 	signal sys_res_n_sync : std_logic;
+	-- rs232
+	signal rx_new, rxd_sync : std_logic;
+	signal rx_data : std_logic_vector (7 downto 0);
+	signal tx_new, tx_done : std_logic;
+	signal tx_data : std_logic_vector (7 downto 0);
+	signal txd_out : std_logic;
 begin
 	-- vga/ipcore
 	textmode_vga_inst : entity work.textmode_vga(struct)
@@ -204,5 +211,47 @@ begin
 		data_in => sys_res_n,
 		data_out => sys_res_n_sync
 	);
+
+	-- synchronizer fuer rxd
+	sync_rxd_inst : entity work.sync(beh)
+	generic map (
+		SYNC_STAGES => 2,
+		RESET_VALUE => '1'
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n_sync,
+		data_in => rxd,
+		data_out => rxd_sync
+	);
+
+	-- rs232-rx
+	rs232rx_inst : entity work.uart_rx(beh)
+	generic map (
+		CLK_FREQ => 33330000,
+		BAUDRATE => 115200
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n_sync,
+		rxd => rxd_sync,
+		rx_data => rx_data,
+		rx_new => rx_new
+	);
+
+	-- rs232-tx
+	rs232tx_inst : entity work.uart_tx(beh)
+	generic map (
+		CLK_FREQ => 33330000,
+		BAUDRATE => 115200
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		txd => txd_out,
+		tx_data => tx_data,
+		tx_new => tx_new,
+		tx_done => tx_done
+	);
 end architecture top;
 
-- 
2.25.1