From 8d4e7625be7e403d727286f7a927f51127b1cfeb Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Tue, 25 May 2010 18:57:35 +0200 Subject: [PATCH] uart_tx: testbench done --- src/TODO | 3 ++ src/beh_uart_tx_tb.do | 43 +--------------- src/beh_uart_tx_tb.vhd | 111 ++++++++++++++++++++++++++++------------- src/uart_tx.vhd | 13 ++--- 4 files changed, 84 insertions(+), 86 deletions(-) diff --git a/src/TODO b/src/TODO index 58845a9..f71752a 100644 --- a/src/TODO +++ b/src/TODO @@ -10,6 +10,9 @@ - postlayout: nochmal testen obs im tilab wirklich ned geht. + +- gen_pkg: unsigned fuer hspalte, hzeile + == BUGS == - warum ist in beh_history s_done und finished manchmal 'X'? diff --git a/src/beh_uart_tx_tb.do b/src/beh_uart_tx_tb.do index 4f70701..014c50c 100644 --- a/src/beh_uart_tx_tb.do +++ b/src/beh_uart_tx_tb.do @@ -2,50 +2,9 @@ alias rr "restart -f" #signale hinzufuegen +add wave * add wave inst/* -delete wave /beh_parser_tb/inst/op1_int -delete wave /beh_parser_tb/inst/op1 -delete wave /beh_parser_tb/inst/op1_next -add wave -radix decimal inst/op1_int - -delete wave /beh_parser_tb/inst/op2_int -delete wave /beh_parser_tb/inst/op2 -delete wave /beh_parser_tb/inst/op2_next -add wave -radix decimal inst/op2_int - -delete wave /beh_parser_tb/inst/op3 -add wave -radix decimal inst/op3 -delete wave /beh_parser_tb/inst/opM -add wave -radix decimal inst/opM - -delete wave /beh_parser_tb/inst/z_int -delete wave /beh_parser_tb/inst/z_next -add wave -radix decimal inst/z_int -add wave -radix decimal inst/z_next - -delete wave /beh_parser_tb/inst/strich_int -delete wave /beh_parser_tb/inst/strich_next -add wave -radix decimal inst/strich_int -add wave -radix decimal inst/strich_next - -delete wave /beh_parser_tb/inst/punkt_int -delete wave /beh_parser_tb/inst/punkt_next -add wave -radix decimal inst/punkt_int -add wave -radix decimal inst/punkt_next - -delete wave /beh_parser_tb/inst/wtmp_int -delete wave /beh_parser_tb/inst/wtmp_next -add wave -radix decimal inst/wtmp_int -add wave -radix decimal inst/wtmp_next - -delete wave /beh_parser_tb/inst/p_write_int -delete wave /beh_parser_tb/inst/p_write_next -delete wave /beh_parser_tb/inst/p_write -add wave -hex inst/p_write_int -add wave -hex inst/p_write_next - - #rauszoomen wave zoomout 500.0 diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd index 3951f9e..58fb2ab 100644 --- a/src/beh_uart_tx_tb.vhd +++ b/src/beh_uart_tx_tb.vhd @@ -7,51 +7,92 @@ entity beh_uart_tx_tb is end entity beh_uart_tx_tb; architecture sim of beh_uart_tx_tb is + constant CLK_FREQ : integer := 33000000; + constant BAUDRATE : integer := 115200; + constant BAUD : integer := CLK_FREQ/BAUDRATE; - constant clk_period : time := 2ns; - signal clock : std_logic; - signal reset : std_logic; - signal done : std_logic; - signal newsig : std_logic; - signal data : std_logic_vector(7 downto 0); - signal serial_out : std_logic; + signal sys_clk, sys_res_n, txd, tx_new, tx_done : std_logic; + signal tx_data : std_logic_vector (7 downto 0); + signal stop : boolean := false; begin inst : entity work.uart_tx(beh) + generic map ( + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE + ) port map ( - sys_clk => clock, - sys_res => reset, - txd => serial_out, - tx_data => data, - tx_new => newsig, - tx_done => done + sys_clk => sys_clk, + sys_res_n => sys_res_n, + txd => txd, + tx_data => tx_data, + tx_new => tx_new, + tx_done => tx_done ); - stimuli : process + process begin - newsig <= '0'; - wait for 10ns; - --send 'Hallo Welt' - data <= X"42"; - newsig <= '1'; - wait for 1000ns; + sys_clk <= '0'; + wait for 15 ns; + sys_clk <= '1'; + wait for 15 ns; + if stop = true then + wait; + end if; + end process; - assert false report "Test finished" severity failure; - end process stimuli; + process + procedure exec_tc(testnr : integer; + constant expectedresult : std_logic_vector(9 downto 0); + constant testvector : std_logic_vector(7 downto 0)) is + variable success : boolean := true; + begin + tx_new <= '1'; + tx_data <= testvector; + icwait(sys_clk, 1); - res_gen : process - begin - reset <= '0'; - wait for 20ns; - reset <= '1'; - wait for 1000ns; - end process res_gen; + -- ein BAUD-cycle auf high warten + icwait(sys_clk, BAUD); + + -- in der mitte abtasten + icwait(sys_clk, BAUD/2); + for i in 0 to 9 loop + if txd /= expectedresult(9-i) then + success := false; + end if; + if i /= 9 then + icwait(sys_clk, BAUD); + end if; + end loop; - clock_gen : process + wait until tx_done = '1'; + tx_new <= '0'; + wait until tx_done = '0'; + if success then + report "testfall " & integer'image(testnr) & " war erfolgreich"; + else + report "testfall " & integer'image(testnr) & " schlug fehl"; + end if; + icwait(sys_clk, 3); + end; begin - clock <= '0'; - wait for clk_period/2; - clock <= '1'; - wait for clk_period/2; - end process clock_gen; + sys_res_n <= '0'; + tx_new <= '0'; + tx_data <= (others => '0'); + icwait(sys_clk, 10); + sys_res_n <= '1'; + icwait(sys_clk, 2); + + -- 1. parameter: testfallnummer + -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1' + -- 3. parameter: byte das gesendet werden soll + exec_tc(1, b"0000011111", b"00001111"); + exec_tc(2, b"0101010101", b"10101010"); + exec_tc(3, b"0110011001", b"11001100"); + exec_tc(4, b"0001100111", b"00110011"); + exec_tc(5, b"0010101011", b"01010101"); + exec_tc(6, b"0100110111", b"10011011"); + stop <= true; + wait; + end process; end sim; diff --git a/src/uart_tx.vhd b/src/uart_tx.vhd index 4c97578..8f15f5b 100644 --- a/src/uart_tx.vhd +++ b/src/uart_tx.vhd @@ -1,12 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---use work.gen_pkg.all; - ---package int_types is --- type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE); --- type PARITY_TYPE is (ODD, EVEN, NONE); ---end package int_types; +use work.gen_pkg.all; entity uart_tx is generic ( @@ -32,7 +27,7 @@ architecture beh of uart_tx is signal txd_next, txd_int : std_logic; signal tx_done_next, tx_done_int : std_logic; signal tx_to_send : std_logic_vector(0 to 10); - signal bitcnt_int, bitcnt_next : integer range 0 to 10; + signal bitcnt_int, bitcnt_next : integer range 0 to 11; signal baudcnt_int, baudcnt_next : integer range 0 to BAUD; begin txd <= txd_int; @@ -54,12 +49,12 @@ begin bitcnt_int <= bitcnt_next; baudcnt_int <= baudcnt_next; -- HIGHBIT (1) | STARTBIT (1) | DATA (8) | STOPBIT (1) - -- TODO: passt das wegen der endianess? tx_to_send <= '1' & '0' & tx_data & '1'; end if; end process; - process(tx_new, tx_to_send, state_int, bitcnt_int, baudcnt_int) + process(tx_new, tx_to_send, state_int, bitcnt_int, baudcnt_int, + tx_done_int, txd_int) begin state_next <= state_int; tx_done_next <= tx_done_int; -- 2.25.1