From 8900b48531adafaf9f58f367bc2da5de904180f6 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Sun, 16 May 2010 18:52:30 +0200 Subject: [PATCH] top-level/pll: pinmapping fixed und pll angepasst --- quartus/project_gen.tcl | 20 +- src/vpll.vhd | 647 +++++++++++++++++++++++----------------- 2 files changed, 383 insertions(+), 284 deletions(-) diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl index 9c46c01..584c736 100644 --- a/quartus/project_gen.tcl +++ b/quartus/project_gen.tcl @@ -91,18 +91,18 @@ if {$make_assignments} { #vga set_location_assignment PIN_F1 -to hsync_n set_location_assignment PIN_F2 -to vsync_n - set_location_assignment E22 -to r[0] - set_location_assignment T4 -to r[1] - set_location_assignment T7 -to r[2] - set_location_assignment E23 -to g[0] - set_location_assignment T5 -to g[1] - set_location_assignment T24 -to g[2] - set_location_assignment E24 -to b[0] - set_location_assignment T6 -to b[1] + set_location_assignment PIN_E22 -to r[0] + set_location_assignment PIN_T4 -to r[1] + set_location_assignment PIN_T7 -to r[2] + set_location_assignment PIN_E23 -to g[0] + set_location_assignment PIN_T5 -to g[1] + set_location_assignment PIN_T24 -to g[2] + set_location_assignment PIN_E24 -to b[0] + set_location_assignment PIN_T6 -to b[1] #ps/2 - set_location_assignment Y26 -to ps2_clk - set_location_assignment E21 -to ps2_data + set_location_assignment PIN_Y26 -to ps2_clk + set_location_assignment PIN_E21 -to ps2_data set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk diff --git a/src/vpll.vhd b/src/vpll.vhd index dbb347f..9790567 100644 --- a/src/vpll.vhd +++ b/src/vpll.vhd @@ -1,274 +1,373 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: vpll.vhd --- Megafunction Name(s): --- altpll --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 4.1 Build 181 06/29/2004 SJ Full Version --- ************************************************************ - - ---Copyright (C) 1991-2004 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY vpll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; --- pllena : IN STD_LOGIC := '1'; --- areset : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC --- locked : OUT STD_LOGIC - ); -END vpll; - - -ARCHITECTURE SYN OF vpll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0); - -signal pllena_int : std_logic; -signal areset_int : std_logic; -signal locked : std_logic; - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_duty_cycle : NATURAL; - lpm_type : STRING; - clk0_multiply_by : NATURAL; - invalid_lock_multiplier : NATURAL; - inclk0_input_frequency : NATURAL; - gate_lock_signal : STRING; - clk0_divide_by : NATURAL; - pll_type : STRING; - valid_lock_multiplier : NATURAL; - clk0_time_delay : STRING; - spread_frequency : NATURAL; - intended_device_family : STRING; - operation_mode : STRING; - compensate_clock : STRING; - clk0_phase_shift : STRING - ); - PORT ( - clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - pllena : IN STD_LOGIC ; - extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - locked : OUT STD_LOGIC ; - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire3_bv(0 DOWNTO 0) <= "0"; - sub_wire3 <= To_stdlogicvector(sub_wire3_bv); - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= NOT(To_stdlogicvector(sub_wire5_bv)); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - locked <= sub_wire2; - sub_wire4 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0); - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire3(0 DOWNTO 0) & sub_wire6; - sub_wire8 <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0); - -areset_int <= '0'; -pllena_int <= '1'; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_duty_cycle => 50, - lpm_type => "altpll", - clk0_multiply_by => 5435, - invalid_lock_multiplier => 5, - inclk0_input_frequency => 30003, - gate_lock_signal => "NO", - clk0_divide_by => 6666, - pll_type => "AUTO", - valid_lock_multiplier => 1, - clk0_time_delay => "0", - spread_frequency => 0, - intended_device_family => "Stratix", - operation_mode => "NORMAL", - compensate_clock => "CLK0", - clk0_phase_shift => "0" - ) - PORT MAP ( - clkena => sub_wire4, - inclk => sub_wire7, - pllena => pllena_int, - extclkena => sub_wire8, - areset => areset_int, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix" --- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435" --- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" --- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0" --- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" --- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena" --- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0 --- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 --- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: vpll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY vpll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END vpll; + + +ARCHITECTURE SYN OF vpll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + spread_frequency : NATURAL + ); + PORT ( + clkena : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + extclkena : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire2_bv(0 DOWNTO 0) <= "0"; + sub_wire2 <= To_stdlogicvector(sub_wire2_bv); + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= NOT(To_stdlogicvector(sub_wire4_bv)); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire3 <= sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire4(0 DOWNTO 0); + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire2(0 DOWNTO 0) & sub_wire5; + sub_wire7 <= sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0) & sub_wire2(0 DOWNTO 0); + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3333, + clk0_duty_cycle => 50, + clk0_multiply_by => 2500, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30003, + intended_device_family => "Stratix", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + spread_frequency => 0 + ) + PORT MAP ( + clkena => sub_wire3, + inclk => sub_wire6, + extclkena => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3333" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2500" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 +-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE +-- Retrieval info: LIB_FILE: altera_mf -- 2.25.1