From 7c42d302d04814bced7207f42a16a0876121c368 Mon Sep 17 00:00:00 2001
From: Alexander Oh <oh.a@gmx.at>
Date: Tue, 25 May 2010 15:50:29 +0200
Subject: [PATCH] removed unresolvedness of some signals and multiple sources

---
 src/beh_pc_communication_tb.vhd |  1 +
 src/pc_communication.vhd        | 46 ++++++++++++++++-----------------
 2 files changed, 24 insertions(+), 23 deletions(-)

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index b43d99e..1ed8b75 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -98,6 +98,7 @@ begin
 		d_spalte <= "0000000";
 		tx_done <= '0';
 		rx_new <= '0';
+		d_char <= (others => '0');
 		
 		wait for 90 ns;
 		sys_res_n <= '1';
diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 3251284..4bc09d4 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -32,11 +32,13 @@ end entity pc_communication;
 architecture beh of pc_communication is
 	signal push_history, push_history_next : std_logic;
 
-	signal spalte, spalte_next : hspalte;
-	signal zeile , zeile_next : hzeile;
+	signal spalte, spalte_next : integer range 0 to 71;
+	signal zeile , zeile_next : integer range 0 to 71;
 	signal spalte_up, spalte_up_next : std_logic;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
+	signal tx_done_i, tx_done_i_next : std_logic;
+	signal d_done_i, d_done_i_next : std_logic;
 
 	signal char, char_next : hbyte;
 	signal char_en : std_logic;
@@ -46,24 +48,25 @@ architecture beh of pc_communication is
 begin
 
 
-	d_zeile <= zeile;
-	d_spalte <= spalte;
+	d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+	d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
 	d_get <= get;
 	char_next <= d_char;
 	tx_new <= new_i;
+	d_done_i <= d_done;
+	tx_done_i <= tx_done;
 
 	sync: process (sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
 			state <= IDLE;
 			push_history <= '0';
-			spalte <= "0000000";
-			spalte_next <= "0000000";
-			zeile <= "0000000";
-			zeile_next <= "0000000";
+			spalte <= 0;
+			zeile <= 0;
 			get <= '0';
 			new_i <= '0';
 			tx_data <= "00000000";
+			spalte_up <= '0';
 		elsif rising_edge(sys_clk) then
 			push_history <= push_history_next;
 			spalte <= spalte_next;
@@ -71,6 +74,7 @@ begin
 			state <= state_next;
 			get <= get_next;
 			new_i <= new_i_next;
+			spalte_up <= spalte_up_next;
 			if (char_en = '1') then
 				char <= char_next;
 			end if;
@@ -78,22 +82,18 @@ begin
 	end process sync;
 
 	process (spalte_up, spalte, zeile)
-	variable spalte_tmp, zeile_tmp : integer;
-	variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
 	begin
 		if (spalte_up = '1') then
-			if (spalte > X"45") then
-				spalte_next <= "0000000";
-				zeile_tmp := to_integer(unsigned(zeile)) + 1;
-				zeile2_tmp := std_logic_vector(to_unsigned(zeile_tmp,8));
-				zeile_next <= hzeile(zeile2_tmp(6 downto 0));
+			if (spalte > 71) then
+				spalte_next <= 0;
+				zeile_next <= zeile + 1;
 			else
-				spalte_tmp := to_integer(unsigned(spalte)) + 1;
-				spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
-				spalte_next <= hspalte(spalte2_tmp(6 downto 0));
+				spalte_next <= spalte + 1;
 				zeile_next <= zeile;
 			end if;
-			spalte_up <= '0';
+		else
+			spalte_next <= spalte;
+			zeile_next <= zeile;
 		end if;
 	end process;
 
@@ -116,8 +116,7 @@ begin
 	begin
 		get_next <= '0';
 		new_i_next <= '0';
-		spalte_next <= "0000000";
-		zeile_next <= "0000000";
+		spalte_up_next <= '0';
 		case state is
 			when IDLE =>
 				null;
@@ -128,6 +127,9 @@ begin
 				char_en <= '0';
 				tx_data <= char;
 				new_i_next <= '1';
+				if (tx_done = '1') then
+					spalte_up_next <= '1';
+				end if;
 			when DONE =>
 				null;
 		end case;
@@ -135,7 +137,6 @@ begin
 
 	next_state_pc : process (rx_new, btn_a, d_done, tx_done)
 	begin
-		spalte_up <= '0';
 		case state is
 			when IDLE =>
 				if rx_new = '1' or btn_a = '1' then
@@ -149,7 +150,6 @@ begin
 			when FORWARD =>
 				if (tx_done = '1') then
 					state_next <= FETCH;
-					spalte_up <= '1';
 				end if;
 			when DONE =>
 				state_next <= IDLE;
-- 
2.25.1