From 78b81af08fdecb68941b50aa298dc6b8492ce770 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Thu, 27 May 2010 21:48:17 +0200 Subject: [PATCH] pc-com: nur dumpen bei enter und ein state removed logic: 2993 --- src/TODO | 5 ----- src/gen_pkg.vhd | 7 +------ src/pc_communication.vhd | 34 ++++++++++++++-------------------- 3 files changed, 15 insertions(+), 31 deletions(-) diff --git a/src/TODO b/src/TODO index c108b2c..65cb854 100644 --- a/src/TODO +++ b/src/TODO @@ -3,11 +3,6 @@ einfach eine zeile skippen (= kein CR und newline machen) wenn das erste byte in der zeile ein nullbyte ist? -- fuer jede entity eine component definition machen und diese verwenden (in der - top-level entity und in den simulationen). - $ grep 'work.' *.vhd - sollte hilfreich sein. - == low prio == - logic elements eliminieren diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index 922911c..6b2e92e 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -109,8 +109,7 @@ package gen_pkg is end component parser; component scanner is - port - ( + port ( sys_clk : in std_logic; sys_res_n : in std_logic; -- PS/2 @@ -186,19 +185,15 @@ package gen_pkg is port ( sys_clk : in std_logic; sys_res_n : in std_logic; - --button btn_a : in std_logic; - --uart_tx tx_data : out std_logic_vector(7 downto 0); tx_new : out std_logic; tx_done : in std_logic; - --uart_rx rx_data : in std_logic_vector(7 downto 0); rx_new : in std_logic; - -- History pc_zeile : out hzeile; pc_spalte : out hspalte; diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd index 410bc4f..8a29ba7 100644 --- a/src/pc_communication.vhd +++ b/src/pc_communication.vhd @@ -7,19 +7,15 @@ entity pc_communication is port ( sys_clk : in std_logic; sys_res_n : in std_logic; - --button btn_a : in std_logic; - --uart_tx tx_data : out std_logic_vector(7 downto 0); tx_new : out std_logic; tx_done : in std_logic; - --uart_rx rx_data : in std_logic_vector(7 downto 0); rx_new : in std_logic; - -- History pc_zeile : out hzeile; pc_spalte : out hspalte; @@ -37,7 +33,7 @@ architecture beh of pc_communication is signal tx_done_i, tx_done_i_next : std_logic; signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0); - type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, + type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT, NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT, PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5, PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT); @@ -72,7 +68,7 @@ begin end process sync; process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a, - pc_done) + pc_done, rx_data) variable tmp : std_logic_vector(6 downto 0); begin get_next <= '0'; @@ -84,8 +80,7 @@ begin state_next <= state; case state is when IDLE => --- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then - if (rx_new = '1') or btn_a = '0' then + if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then state_next <= PRINT_NO0_WAIT; end if; @@ -161,22 +156,21 @@ begin when FORWARD => tx_data_i_next <= pc_char; new_i_next <= '1'; - -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt - get_next <= '1'; - state_next <= WAIT_UART; - when WAIT_UART => - new_i_next <= '1'; + -- halte pc_get weiterhin high sodass pc_char garantiert + -- gleicht bleibt (blockiert history!) get_next <= '1'; if tx_done_i = '1' then state_next <= UART_DONE; end if; when UART_DONE => - state_next <= FETCH; - spalte_next <= spalte + 1; - if spalte = HSPALTE_MAX + 1 then - state_next <= NL; - spalte_next <= 1; - zeile_next <= zeile + 1; + if tx_done_i = '0' then + state_next <= FETCH; + spalte_next <= spalte + 1; + if spalte = HSPALTE_MAX + 1 then + state_next <= NL; + spalte_next <= 1; + zeile_next <= zeile + 1; + end if; end if; when NL => tx_data_i_next <= x"0a"; @@ -195,7 +189,7 @@ begin when CR_WAIT => tmp := std_logic_vector(to_unsigned(zeile,7)); if tmp(0) = '0' then - -- es handelt sich um eingabe + -- es handelt sich um eingabe im naechsten schritt -- => print zeilennummer state_next <= PRINT_NO0_WAIT; else -- 2.25.1