From 6c9cfad9bf36e7150d94748f77ef7ec907434320 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Tue, 25 May 2010 21:28:01 +0200 Subject: [PATCH] uart-testing: testbench fuer loopback --- src/beh_loopback_tb.do | 16 ++++++ src/beh_loopback_tb.vhd | 112 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 src/beh_loopback_tb.do create mode 100644 src/beh_loopback_tb.vhd diff --git a/src/beh_loopback_tb.do b/src/beh_loopback_tb.do new file mode 100644 index 0000000..24b5e5a --- /dev/null +++ b/src/beh_loopback_tb.do @@ -0,0 +1,16 @@ +#alias fuer simulation neustarten +alias rr "restart -f" + +#signale hinzufuegen +add wave * +add wave inst_rx/* +add wave inst_tx/* + +#rauszoomen +wave zoomout 500.0 + +#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen) +run -all + +#ganz nach links scrollen +wave seetime 0 diff --git a/src/beh_loopback_tb.vhd b/src/beh_loopback_tb.vhd new file mode 100644 index 0000000..a44bdbd --- /dev/null +++ b/src/beh_loopback_tb.vhd @@ -0,0 +1,112 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.gen_pkg.all; + +entity beh_loopback_tb is +end entity beh_loopback_tb; + +architecture sim of beh_loopback_tb is + constant CLK_FREQ : integer := 33000000; + constant BAUDRATE : integer := 115200; + constant BAUD : integer := CLK_FREQ/BAUDRATE; + + signal sys_clk, sys_res_n, rxd, rx_new : std_logic; + signal rx_data : std_logic_vector (7 downto 0); + signal txd, tx_new, tx_done : std_logic; + signal tx_data : std_logic_vector (7 downto 0); + signal stop : boolean := false; +begin + inst_rx : entity work.uart_rx(beh) + generic map ( + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + rxd => rxd, + rx_data => rx_data, + rx_new => rx_new + ); + inst_tx : entity work.uart_tx(beh) + generic map ( + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE + ) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + txd => txd, + tx_data => tx_data, + tx_new => tx_new, + tx_done => tx_done + ); + + process + begin + sys_clk <= '0'; + wait for 15 ns; + sys_clk <= '1'; + wait for 15 ns; + if stop = true then + wait; + end if; + end process; + + process + procedure exec_tc(testnr : integer; + constant testvector : std_logic_vector(9 downto 0); + constant expectedresult : std_logic_vector(7 downto 0)) is + begin + -- vorher auf high setzen um falling edge simulieren zu koennen + rxd <= '1'; + icwait(sys_clk, 2); + + for i in 0 to 9 loop + rxd <= testvector(9-i); + if i /= 9 then + icwait(sys_clk, BAUD); + end if; + end loop; + + wait until rx_new = '1'; + if expectedresult = rx_data then + report "testfall " & integer'image(testnr) & " war erfolgreich"; + else + report "testfall " & integer'image(testnr) & " schlug fehl"; + end if; + tx_new <= '1'; + tx_data <= rx_data; + icwait(sys_clk, 1); + wait until tx_done = '1'; + tx_new <= '0'; + wait until tx_done = '0'; + icwait(sys_clk, 3); + end; + + variable testvector : std_logic_vector(9 downto 0); + variable expectedresult : std_logic_vector(7 downto 0); + begin + sys_res_n <= '0'; + rxd <= '1'; + tx_new <= '0'; + tx_data <= (others => '0'); + icwait(sys_clk, 10); + sys_res_n <= '1'; + icwait(sys_clk, 2); + + -- 1. parameter: testfallnummer + -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1' + -- 3. parameter: byte das rauskommen soll + exec_tc(1, b"0000011111", b"00001111"); + exec_tc(2, b"0101010101", b"10101010"); + exec_tc(3, b"0110011001", b"11001100"); + exec_tc(4, b"0001100111", b"00110011"); + exec_tc(5, b"0010101011", b"01010101"); + exec_tc(6, b"0100110111", b"10011011"); + + stop <= true; + wait; + end process; +end sim; -- 2.25.1