From 296b97dc82442c2ff794f729003dd4358ed7e10c Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Sun, 16 May 2010 13:44:53 +0200 Subject: [PATCH] display: simple implementierung + testbench --- src/beh_display_tb.do | 14 +++++ src/beh_display_tb.vhd | 116 +++++++++++++++++++++++++++++++++++++++++ src/display.vhd | 66 +++++++++++++++++++---- 3 files changed, 185 insertions(+), 11 deletions(-) create mode 100644 src/beh_display_tb.do create mode 100644 src/beh_display_tb.vhd diff --git a/src/beh_display_tb.do b/src/beh_display_tb.do new file mode 100644 index 0000000..2f52a4c --- /dev/null +++ b/src/beh_display_tb.do @@ -0,0 +1,14 @@ +#alias fuer simulation neustarten +alias rr "restart -f" + +#signale hinzufuegen +add wave inst/* + +#rauszoomen +wave zoomout 500.0 + +#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen) +run -all + +#ganz nach links scrollen +wave seetime 0 diff --git a/src/beh_display_tb.vhd b/src/beh_display_tb.vhd new file mode 100644 index 0000000..02a8257 --- /dev/null +++ b/src/beh_display_tb.vhd @@ -0,0 +1,116 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.gen_pkg.all; +use work.textmode_vga_component_pkg.all; +use work.textmode_vga_pkg.all; +use work.textmode_vga_platform_dependent_pkg.all; + +entity beh_display_tb is +end entity beh_display_tb; + +architecture sim of beh_display_tb is + -- system + signal sys_clk, sys_res_n : std_logic; + -- vga/display + signal free : std_logic; + signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0); + signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0); + -- history/display + signal d_new_eingabe, d_new_result : std_logic; + signal d_zeile : hzeile; + signal d_spalte : hspalte; + signal d_get, d_done : std_logic; + signal d_char : hbyte; + -- history/scanner + signal s_char : hbyte; + signal s_take, s_done, s_backspace : std_logic; + + signal stop : boolean := false; +begin + -- display + inst : entity work.display(beh) + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + -- history + d_new_eingabe => d_new_eingabe, + d_new_result => d_new_result, + d_zeile => d_zeile, + d_spalte => d_spalte, + d_get => d_get, + d_done => d_done, + d_char => d_char, + -- vga + command => command, + command_data => command_data, + free => free + ); + + process + begin + sys_clk <= '0'; + wait for 15 ns; + sys_clk <= '1'; + wait for 15 ns; + if stop = true then + wait; + end if; + end process; + + process + variable input : hstring := "123513 "; + variable ctmp : character; + + variable checkall : boolean := true; + variable i : integer := 1; + begin + -- init & reset + sys_res_n <= '0'; + d_new_eingabe <= '0'; + d_new_result <= '0'; + d_done <= '0'; + d_char <= x"00"; + free <= '1'; + + icwait(sys_clk, 5); + sys_res_n <= '1'; + + while i <= 71 loop + d_new_eingabe <= '1'; + wait on d_get; -- = '1'; + icwait(sys_clk, 1); + + ctmp := input(to_integer(unsigned(d_spalte))); + d_char <= hbyte(to_unsigned(character'pos(ctmp),8)); + + d_done <= '1'; + wait on d_get; -- = '0'; + icwait(sys_clk, 1); + d_done <= '0'; + d_new_eingabe <= '0'; + + free <= '0'; + icwait(sys_clk, 3); + free <= '1'; + icwait(sys_clk, 3); + + -- fuer NOP + free <= '0'; + icwait(sys_clk, 3); + free <= '1'; + + i := i + 1; + end loop; + + + if checkall then + report "alle testfaelle des Displays waren erfolgreich!"; + else + report "nicht alle testfaelle des Displays waren erfolgreich!"; + end if; + icwait(sys_clk, 10); + stop <= true; + wait; + end process; +end architecture sim; diff --git a/src/display.vhd b/src/display.vhd index f0a3cc0..f540dd2 100644 --- a/src/display.vhd +++ b/src/display.vhd @@ -26,7 +26,8 @@ entity display is end entity display; architecture beh of display is - type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT); + type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH, + S_PUTCH, S_WAIT, S_NOP1, S_NOP2); signal state_int, state_next : DISPLAY_STATE; signal d_zeile_int, d_zeile_next : hzeile; signal d_spalte_int, d_spalte_next : hspalte; @@ -70,17 +71,39 @@ begin case state_int is when SIDLE => - if free = '1' then - if d_new_eingabe = '1' then - state_next <= S_NEW_INPUT; - end if; - if d_new_result = '1' then - state_next <= S_NEW_RESULT; - end if; + if d_new_eingabe = '1' then + state_next <= S_NEW_INPUT; + end if; + if d_new_result = '1' then + state_next <= S_NEW_RESULT; end if; when S_NEW_RESULT | S_NEW_INPUT => + state_next <= S_COUNTUP; + when S_COUNTUP => + state_next <= S_GETCH; + when S_GETCH => + if free = '1' and d_done = '1' then + state_next <= S_PUTCH; + end if; + when S_PUTCH => if free = '0' then - state_next <= SIDLE; + state_next <= S_WAIT; + end if; + when S_WAIT => + if free = '1' and d_done = '0' then + state_next <= S_NOP1; + end if; + when S_NOP1 => + if free = '0' then + state_next <= S_NOP2; + end if; + when S_NOP2 => + if free = '1' then + if unsigned(d_spalte_int) = 71 then + state_next <= SIDLE; + else + state_next <= S_COUNTUP; + end if; end if; end case; end process; @@ -91,13 +114,34 @@ begin begin d_zeile_next <= d_zeile_int; d_spalte_next <= d_spalte_int; - d_get_next <= d_get_int; + d_get_next <= '0'; command_next <= command_int; command_data_next <= command_data_int; case state_int is - when SIDLE | S_NEW_INPUT | S_NEW_RESULT => + when SIDLE => + null; + when S_NEW_INPUT => + d_spalte_next <= (others => '0'); + when S_NEW_RESULT => + d_spalte_next <= (others => '0'); + case d_zeile_int is + when "11111" => d_zeile_next <= "00000"; + when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1); + end case; + when S_COUNTUP => + d_get_next <= '1'; + d_spalte_next <= std_logic_vector(unsigned(d_spalte_int) + 1); + when S_GETCH => + d_get_next <= '1'; + when S_PUTCH => + command_next <= COMMAND_SET_CHAR; + command_data_next <= x"000000" & std_logic_vector(d_char); + when S_WAIT | S_NOP2 => null; + when S_NOP1 => + command_next <= COMMAND_NOP; + command_data_next <= x"00000000"; end case; end process; end architecture beh; -- 2.25.1