From 085080e9ed940745f5f168c66f4101d8c3943a45 Mon Sep 17 00:00:00 2001
From: Alexander Oh <oh.a@gmx.at>
Date: Thu, 27 May 2010 02:47:11 +0200
Subject: [PATCH] added pc_communication and btn_a to quartus project

---
 quartus/project_gen.tcl         |  4 +++
 src/beh_pc_communication_tb.vhd |  2 +-
 src/calc.vhd                    | 58 +++++++++++++++++++++++++++++----
 3 files changed, 57 insertions(+), 7 deletions(-)

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index a6204ef..d608f10 100644
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -51,6 +51,7 @@ if {$make_assignments} {
 	set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
 	set_global_assignment -name VHDL_FILE ../../src/uart_tx.vhd
 	set_global_assignment -name VHDL_FILE ../../src/uart_rx.vhd
+	set_global_assignment -name VHDL_FILE ../../src/pc_communication.vhd
 	
 	#vga ip-core
 	set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
@@ -124,6 +125,9 @@ if {$make_assignments} {
 	set_location_assignment PIN_D22 -to txd
 	set_location_assignment PIN_D23 -to rxd
 
+	#btn_a
+	set_location_assignment PIN_A3 -to btn_a
+
 	set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
 	set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
 	#warning fix fuer pll
diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 7e2d691..bdce739 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -29,7 +29,7 @@ architecture sim of beh_pc_communication_tb is
 		signal d_spalte : hspalte;
 		signal d_char : hbyte;
 begin
-	-- display
+	-- pc_communication
 	inst : entity work.pc_communication(beh)
 	port map (
 		sys_clk => sys_clk,
diff --git a/src/calc.vhd b/src/calc.vhd
index d398bd3..420e273 100644
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -14,7 +14,7 @@ entity calc is
 		sys_clk : in std_logic;
 		sys_res_n : in std_logic;
 		-- btnA
-		-- TODO: pins
+		btn_a : in std_logic;
 		-- rs232
 		rxd : in std_logic;
 		txd : out std_logic;
@@ -56,6 +56,12 @@ architecture top of calc is
 	signal p_wdone : std_logic;
 	signal p_write : hbyte;
 	signal p_finished : std_logic;
+	--history/pc_com
+	signal pc_get : std_logic;
+	signal pc_spalte : hspalte;
+	signal pc_zeile : hzeile;
+	signal pc_char : hbyte;
+	signal pc_done : std_logic;
 	-- parser/scanner
 	signal do_it, finished : std_logic;
 	-- debouncing
@@ -65,6 +71,9 @@ architecture top of calc is
 	signal rx_data : std_logic_vector (7 downto 0);
 	signal tx_new, tx_done : std_logic;
 	signal tx_data : std_logic_vector (7 downto 0);
+
+	signal btn_a_sync : std_logic;
+
 begin
 	-- vga/ipcore
 	textmode_vga_inst : entity work.textmode_vga(struct)
@@ -143,11 +152,11 @@ begin
 		p_write => p_write,
 		p_finished => p_finished,
 		-- pc communication
-		pc_get =>  '0',
-		pc_spalte => (others => '0'),
-		pc_zeile => (others => '0'),
-		pc_char => open,
-		pc_done => open
+		pc_get =>  pc_get,
+		pc_spalte => pc_spalte,
+		pc_zeile => pc_zeile,
+		pc_char => pc_char,
+		pc_done => pc_done
 
 	);
 
@@ -231,6 +240,21 @@ begin
 		data_out => rxd_sync
 	);
 
+	-- debouncer fuer btn_a
+	btn_a_debounce_inst : debounce
+	generic map (
+		CLK_FREQ => 33330000,
+		TIMEOUT => 1 ms,
+		RESET_VALUE => '1',
+		SYNC_STAGES => 2
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => '1',
+		data_in => btn_a,
+		data_out => btn_a_sync
+	);
+
 	-- rs232-rx
 	rs232rx_inst : entity work.uart_rx(beh)
 	generic map (
@@ -259,5 +283,27 @@ begin
 		tx_new => tx_new,
 		tx_done => tx_done
 	);
+
+	pc_com_inst : entity work.pc_communication(beh)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		--button
+		btn_a => btn_a_sync,
+		--uart_tx
+		tx_data => tx_data,
+		tx_new => tx_new,
+		tx_done => tx_done,
+		--uart_rx
+		rx_data => rx_data,
+		rx_new => rx_new,
+		-- History
+		d_zeile => pc_zeile,
+		d_spalte => pc_spalte,
+		d_get => pc_get,
+		d_done => pc_done,
+		d_char => pc_char
+	);
+
 end architecture top;
 
-- 
2.25.1