From 030287b141ae40fd8c7e9e8060ee7a96ba109499 Mon Sep 17 00:00:00 2001 From: Alexander Oh Date: Thu, 27 May 2010 06:16:30 +0200 Subject: [PATCH] implemented busy state this is basically to see if the arbiter works correctly and it enters a busy state after the fetch was accepted. --- src/beh_history_tb.vhd | 19 +++++++++++-------- src/beh_pc_communication_tb.vhd | 15 +++++++++------ src/calc.vhd | 3 +++ src/gen_pkg.vhd | 2 +- src/history.vhd | 5 ++++- src/pc_communication.vhd | 13 +++++++++---- 6 files changed, 37 insertions(+), 20 deletions(-) diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index 2a24d04..eaa4fe3 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -46,6 +46,7 @@ architecture sim of beh_history_tb is signal pc_spalte : hspalte; signal pc_get, pc_done : std_logic; signal pc_char : hbyte; + signal pc_busy : std_logic; --dummy button signal btn_a_int : std_logic; @@ -84,6 +85,7 @@ begin pc_spalte => pc_spalte, pc_zeile => pc_zeile, pc_char => pc_char, + pc_busy => pc_busy, pc_done => pc_done ); @@ -168,11 +170,12 @@ begin rx_data => (others => '0'), rx_new => '0', -- History - pc_zeile => pc_zeile, - pc_spalte => pc_spalte, - pc_get => pc_get, - pc_done => pc_done, - pc_char => pc_char + pc_zeile => pc_zeile, + pc_spalte => pc_spalte, + pc_get => pc_get, + pc_done => pc_done, + pc_char => pc_char, + pc_busy => pc_busy ); process @@ -311,13 +314,13 @@ begin btn_pressed : process is begin - btn_a_int <= '0'; + btn_a_int <= '1'; wait until sys_res_n = '1'; wait for 50000 * 15 ns; wait until rising_edge(sys_clk); - btn_a_int <= '1'; - wait for 30 ns; btn_a_int <= '0'; + wait for 30 ns; + btn_a_int <= '1'; wait; end process btn_pressed; end architecture sim; diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd index ae8ed74..9d12996 100644 --- a/src/beh_pc_communication_tb.vhd +++ b/src/beh_pc_communication_tb.vhd @@ -23,6 +23,7 @@ architecture sim of beh_pc_communication_tb is signal rx_new : std_logic; signal pc_get : std_logic; signal pc_done : std_logic; + signal pc_busy : std_logic; signal rx_data, tx_data : std_logic_vector(7 downto 0); signal pc_zeile : hzeile; @@ -52,6 +53,7 @@ begin pc_spalte => pc_spalte, pc_get => pc_get, pc_done => pc_done, + pc_busy => pc_busy, pc_char => pc_char ); @@ -65,16 +67,15 @@ begin stub_history : process file f : text open read_mode is "../../src/pc_communication.test"; - --variable rb : hbyte; variable rb : character; variable good : boolean; variable i : integer; variable buf : my_string; variable l : line; begin - --take control of the situation. pc_char <= (others => '0'); pc_done <= '0'; + pc_busy <= '0'; wait until sys_res_n = '1'; while not endfile (f) loop @@ -84,14 +85,16 @@ begin while i < l'length loop pc_done <= '0'; wait until rising_edge(pc_get); + wait for 90 ns; + pc_busy <= '1'; pc_char <= (others => '0'); wait for 300 ns; pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8))); i := i + 1; + pc_busy <= '0'; pc_done <= '1'; wait for 30 ns; - end loop; end loop; @@ -116,16 +119,16 @@ begin -- init & reset -- we only simulate pressing of button a by now! sys_res_n <= '0'; - btn_a <= '0'; + btn_a <= '1'; rx_data <= ( others => '0'); rx_new <= '0'; wait for 90 ns; sys_res_n <= '1'; wait for 30 ns; - btn_a <= '1'; - wait for 30 ns; btn_a <= '0'; + wait for 30 ns; + btn_a <= '1'; wait; --wait for 1000 ns; --assert false report "test beendet" severity failure; diff --git a/src/calc.vhd b/src/calc.vhd index 5cfefaa..21ae1cd 100644 --- a/src/calc.vhd +++ b/src/calc.vhd @@ -62,6 +62,7 @@ architecture top of calc is signal pc_zeile : hzeile; signal pc_char : hbyte; signal pc_done : std_logic; + signal pc_busy : std_logic; -- parser/scanner signal do_it, finished : std_logic; -- debouncing @@ -156,6 +157,7 @@ begin pc_spalte => pc_spalte, pc_zeile => pc_zeile, pc_char => pc_char, + pc_busy => pc_busy, pc_done => pc_done ); @@ -301,6 +303,7 @@ begin pc_zeile => pc_zeile, pc_spalte => pc_spalte, pc_get => pc_get, + pc_busy => pc_busy, pc_done => pc_done, pc_char => pc_char ); diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index 44b1596..216d9f0 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -20,7 +20,7 @@ package gen_pkg is -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes constant hspalte_max : integer := 71; - constant hzeile_max : integer := 50; + constant hzeile_max : integer := 100; constant H_RAM_SIZE : integer := 7100; constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE); subtype hspalte is std_logic_vector(6 downto 0); diff --git a/src/history.vhd b/src/history.vhd index dd2ce8b..46acf19 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -103,6 +103,7 @@ begin pc_char_int <= (others => '0'); pc_done_int <= '0'; + pc_busy_int <= '0'; address_int <= (0 => '1', others => '0'); data_in_int <= x"00"; @@ -128,6 +129,7 @@ begin pc_char_int <= pc_char_next; pc_done_int <= pc_done_next; + pc_busy_int <= pc_busy_next; address_int <= address_next; data_in_int <= data_in_next; @@ -244,6 +246,7 @@ begin data_in_next <= data_in_int; pc_done_next <= '0'; pc_char_next <= pc_char_int; --(others => '0'); + pc_busy_next <= '0'; p_rdone_next <= p_rdone_int; p_wdone_next <= p_wdone_int; p_read_next <= p_read_int; @@ -286,7 +289,6 @@ begin addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int; end if; s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0); - wr_next <= '1'; address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp)); data_in_next <= (others => '0'); @@ -353,6 +355,7 @@ begin addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte)); address_next <= addr_tmp; + pc_busy_next <= '1'; when S_PC_READ => pc_char_next <= data_out; pc_done_next <= '1'; diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd index b404446..89dff25 100644 --- a/src/pc_communication.vhd +++ b/src/pc_communication.vhd @@ -24,6 +24,7 @@ entity pc_communication is pc_zeile : out hzeile; pc_spalte : out hspalte; pc_get : out std_logic; + pc_busy : in std_logic; --signals if the history module actually grants our request. pc_done : in std_logic; pc_char : in hbyte ); @@ -104,17 +105,21 @@ begin end case; end process output_pc; - next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state, - tx_data_i ,tx_done_i, zeile) + next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, + state, tx_data_i ,tx_done_i, zeile) begin state_next <= state; case state is when IDLE => - if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then + if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '0' then state_next <= FETCH; end if; when FETCH => - state_next <= WAIT_HIST; + if pc_busy = '1' then + state_next <= WAIT_HIST; + else + state_next <= FETCH; + end if; when WAIT_HIST => if (pc_done = '1') then state_next <= FORWARD; -- 2.25.1