From: Alexander Oh <oh.a@gmx.at>
Date: Tue, 25 May 2010 22:34:54 +0000 (+0200)
Subject: First working version with beh simulation
X-Git-Tag: abgabe~35
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=ed21cbbd893717c29b0820a80fb55d697baf7730

First working version with beh simulation

simulation now runs up to the point where everything is dumped.
---

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 63ba7cc..9b9a489 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -74,16 +74,17 @@ begin
 	begin
 		--take control of the situation.
 		d_char <= (others => '0');
+		d_done <= '0';
 		wait until sys_res_n = '1';
 
 		while not endfile (f) loop
 			readline(f, l);
 			i := 1;
 			while i < l'length loop
-				wait until rising_edge(d_get);
 				d_done <= '0';
+				wait until rising_edge(d_get);
 				d_char <= (others => '0');
-				wait for 90 ns;
+				wait for 300 ns;
 
 				d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
 				d_done <= '1';
@@ -97,9 +98,10 @@ begin
 
 	stub_uart : process
 	begin
+		tx_done <= '0';
+		wait until sys_res_n = '1';
 		while true loop
 			tx_done <= '0';
-			wait until sys_res_n = '1';
 			wait until rising_edge(tx_new);
 			wait for 300 ns;
 			tx_done <= '1';
@@ -115,15 +117,13 @@ begin
 		btn_a <= '0';
 		tx_data <= ( others => '0');
 		rx_data <= ( others => '0');
-		d_zeile <= ( others => '0');
-		d_spalte <= ( others => '0');
 		rx_new <= '0';
 		
 		wait for 90 ns;
 		sys_res_n <= '1';
 		wait for 30 ns;
 		btn_a <= '1';
-		wait for 15 ns;
+		wait for 30 ns;
 		btn_a <= '0';
 		wait;
 		--wait for 1000 ns;
diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 06884f0..44e43cd 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -32,8 +32,8 @@ end entity pc_communication;
 architecture beh of pc_communication is
 	signal push_history, push_history_next : std_logic;
 
-	signal spalte, spalte_next : integer range 0 to 71;
-	signal zeile , zeile_next : integer range 0 to 71;
+	signal spalte, spalte_next : integer range 1 to 73;
+	signal zeile , zeile_next : integer range 1 to 73;
 	signal spalte_up, spalte_up_next : std_logic;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
@@ -61,8 +61,8 @@ begin
 		if sys_res_n = '0' then
 			state <= IDLE;
 			push_history <= '0';
-			spalte <= 0;
-			zeile <= 0;
+			spalte <= 1;
+			zeile <= 1;
 			get <= '0';
 			new_i <= '0';
 			tx_data <= "00000000";
@@ -86,11 +86,18 @@ begin
 	process (spalte_up, spalte, zeile)
 	begin
 		if (spalte_up = '1') then
-			if (spalte > 71) then
-				spalte_next <= 0;
-				zeile_next <= zeile + 1;
+			if (spalte > 72) then
+				if zeile + 1 > 50 then 
+					spalte_next <= 1;
+					zeile_next <= 1;
+					--done <= '1'; lets assume this false
+					assert false severity failure;
+				else
+					spalte_next <= 1;
+					zeile_next <= zeile + 1;
+				end if;
 			else
-				spalte_next <= spalte + 1;
+				spalte_next <= spalte + 1; --overflow here!
 				zeile_next <= zeile;
 			end if;
 		else