From: Bernhard Urban Date: Thu, 20 May 2010 17:25:02 +0000 (+0200) Subject: history/display: nach d_new_result = '1' werden die naechsten 70 bytes vom display X-Git-Tag: alpha~1 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=9f86188ebcedaf3cc7a7106b0a8d6a96493d41bc history/display: nach d_new_result = '1' werden die naechsten 70 bytes vom display angefordert um das ergebnis auszulesen. momentan wird jedes byte im speicher mit dem zeichen 'A' initialisiert und daher werden nach dem druecken von ENTER 70x'A' ausgegeben. Naechster Schritt: parser einbauen :) --- diff --git a/spec/speck.tex b/spec/speck.tex index 8a08c8f..ea9abb6 100644 --- a/spec/speck.tex +++ b/spec/speck.tex @@ -624,6 +624,9 @@ behandelt??) \emph{read} auf \emph{\"ubernehmen} ist n\"otig um leerzeichen \"ubernehmen zu k\"oennen. \item History $\Rightarrow$ Display: ein zus\"atzliches Signal \emph{d\_new\_bs}. +\item Display $\Rightarrow$ History: die Breite f\"ur \emph{d\_zeile} muss +ebenfalls so breit wie \emph{p\_zeile} sein (zumindest vereinfacht das die +Implementierung) \end{itemize} \end{document} diff --git a/src/beh_display_tb.vhd b/src/beh_display_tb.vhd index 5b6e6a1..6b0b19b 100644 --- a/src/beh_display_tb.vhd +++ b/src/beh_display_tb.vhd @@ -70,6 +70,7 @@ begin sys_res_n <= '0'; d_new_eingabe <= '0'; d_new_result <= '0'; + d_new_bs <= '0'; d_done <= '0'; d_char <= x"00"; free <= '1'; diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index baf097a..4c98d76 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -264,6 +264,7 @@ begin wait on do_it; -- = '0' icwait(sys_clk, 1); finished <= '0'; + icwait(sys_clk, 850); run_tc := false; else @@ -275,7 +276,7 @@ begin report "=================="; end loop f_loop; - icwait(sys_clk, 20); + icwait(sys_clk, 850); stop <= true; wait; end process; diff --git a/src/display.vhd b/src/display.vhd index 8b0a9cc..19c9d24 100644 --- a/src/display.vhd +++ b/src/display.vhd @@ -28,8 +28,8 @@ end entity display; architecture beh of display is type DISPLAY_STATE is (SIDLE, S_NEW_BS, S_BACK, S_BLANK, S_NEW_RESULT, - S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, - S_WAIT, S_NOP1); + S_ZEILEUP, S_NEW_INPUT, S_COUNTUP, S_GETCH, S_CR1, S_NL1, S_PUTCH1, + S_PUTCH2, S_WAIT, S_NOP1, S_READ_RESULT); signal state_int, state_next : DISPLAY_STATE; signal d_zeile_int, d_zeile_next : hzeile; signal d_spalte_int, d_spalte_next : hspalte; @@ -89,7 +89,7 @@ begin end if; when S_NEW_RESULT => - state_next <= S_CR1; + state_next <= S_ZEILEUP; when S_NEW_INPUT => state_next <= S_COUNTUP; @@ -109,15 +109,37 @@ begin istate_next <= b"010"; -- => danach S_BACK end if; + when S_ZEILEUP => + case istate_int is + when b"011" => + state_next <= S_WAIT; + istate_next <= b"111"; + when others => state_next <= S_CR1; + end case; + when S_CR1 => if free = '0' then state_next <= S_WAIT; - istate_next <= b"000"; -- => danach S_NL1 + case istate_int is + when b"110" => istate_next <= b"101"; -- => danach S_NL1 und SIDLe + when others => istate_next <= b"000"; -- => danach S_NL1 und S_COUNTUP + end case; end if; when S_NL1 => if free = '0' then state_next <= S_WAIT; - istate_next <= b"111"; -- => wieder nach SIDLE + case istate_int is + when b"101" => istate_next <= b"011"; -- => danach S_ZEILEUP + when others => istate_next <= b"100"; -- => danach S_READ_RESULT + end case; + end if; + when S_READ_RESULT => + if unsigned(d_spalte_int) /= 70 then + state_next <= S_COUNTUP; + istate_next <= b"100"; -- => wieder nach S_READ_RESULT + else + state_next <= S_WAIT; + istate_next <= b"110"; -- => danach S_CR1 und d_spalte_next clearen und d_zeile_next inkrementieren end if; when S_COUNTUP => @@ -142,6 +164,10 @@ begin when b"000" => state_next <= S_NL1; when b"001" => state_next <= S_BLANK; when b"010" => state_next <= S_BACK; + when b"011" => state_next <= S_ZEILEUP; + when b"100" => state_next <= S_READ_RESULT; + when b"110" => state_next <= S_CR1; + when b"101" => state_next <= S_NL1; when others => state_next <= SIDLE; end case; end if; @@ -150,7 +176,7 @@ begin -- out process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int, - command_data_int, d_char) + command_data_int, d_char, istate_int) begin d_zeile_next <= d_zeile_int; d_spalte_next <= d_spalte_int; @@ -162,11 +188,6 @@ begin when SIDLE => null; when S_NEW_RESULT => - d_spalte_next <= (others => '0'); - case d_zeile_int is - when "11111" => d_zeile_next <= "00000"; - when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1); - end case; when S_NEW_INPUT => null; @@ -181,12 +202,20 @@ begin command_next <= COMMAND_SET_CHAR; command_data_next <= x"ffffff" & x"20"; -- white space + when S_ZEILEUP => + d_spalte_next <= (others => '0'); + case d_zeile_int is + when "1111111" => d_zeile_next <= (others => '0'); + when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1); + end case; + when S_CR1 => command_next <= COMMAND_SET_CHAR; command_data_next <= x"ffffff" & x"0d"; -- carrige return when S_NL1 => command_next <= COMMAND_SET_CHAR; command_data_next <= x"ffffff" & x"0a"; -- newline + when S_READ_RESULT => null; when S_COUNTUP => d_get_next <= '1'; diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index b4ed94d..9e27eae 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -18,11 +18,11 @@ package gen_pkg is -- integer ist 32bit (31bit + sign) subtype cinteger is integer; - -- TODO: 50 * 71 * 2 = 7100 - constant H_RAM_SIZE : integer := 71; + -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes + constant H_RAM_SIZE : integer := 7100; constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE); subtype hspalte is std_logic_vector(6 downto 0); - subtype hzeile is std_logic_vector(4 downto 0); + subtype hzeile is std_logic_vector(6 downto 0); subtype hbyte is std_logic_vector(7 downto 0); subtype hstring is string(1 to 72); subtype hstr_int is integer range 0 to 72; diff --git a/src/history.vhd b/src/history.vhd index 76c4bf7..ca9800f 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -34,9 +34,10 @@ end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, - S_D_INIT, S_D_WRITE); + S_D_INIT, S_D_READ, S_S_FIN_POSUP); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; + signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); signal s_done_int, s_done_next : std_logic; signal s_cnt_int, s_cnt_next : hspalte; signal d_new_eingabe_int, d_new_eingabe_next : std_logic; @@ -67,6 +68,7 @@ begin -- internal state_int <= SIDLE; was_bs_int <= '0'; + pos_int <= (others => '0'); -- out s_done_int <= '0'; s_cnt_int <= (0 => '1', others => '0'); @@ -85,6 +87,7 @@ begin -- internal state_int <= state_next; was_bs_int <= was_bs_next; + pos_int <= pos_next; -- out s_done_int <= s_done_next; s_cnt_int <= s_cnt_next; @@ -129,16 +132,18 @@ begin state_next <= S_S_DONE; when S_S_FIN => if do_it = '0' then - state_next <= SIDLE; + state_next <= S_S_FIN_POSUP; end if; + when S_S_FIN_POSUP => + state_next <= SIDLE; when S_S_DONE => if s_take = '0' then state_next <= SIDLE; end if; when S_D_INIT => - state_next <= S_D_WRITE; - when S_D_WRITE => + state_next <= S_D_READ; + when S_D_READ => if d_get = '0' then state_next <= SIDLE; end if; @@ -146,14 +151,16 @@ begin end process; -- out - process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int, + process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int, data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int, - was_bs_int, s_take) + was_bs_int, s_take, pos_int) variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0); + variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0); begin s_done_next <= '0'; s_cnt_next <= s_cnt_int; was_bs_next <= was_bs_int; + pos_next <= pos_int; d_new_result_next <= d_new_result_int; d_new_eingabe_next <= d_new_eingabe_int; d_new_bs_next <= '0'; @@ -175,7 +182,7 @@ begin -- TODO: '/=' billiger als '<' ? if unsigned(s_cnt_int) /= 71 then wr_next <= '1'; - address_next <= s_cnt_int; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); data_in_next <= s_char; s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); else @@ -184,22 +191,26 @@ begin end if; when S_S_BS => -- ab 1 darf nicht mehr dekrementiert werden + addr_tmp := (others => '0'); if unsigned(s_cnt_int) /= 1 then - addr_tmp := std_logic_vector(unsigned(s_cnt_int) - 1); + addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1); d_new_bs_next <= '1'; else - addr_tmp := s_cnt_int; + addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int; end if; - s_cnt_next <= addr_tmp; + s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0); wr_next <= '1'; - address_next <= addr_tmp; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp)); data_in_next <= (others => '0'); was_bs_next <= '1'; when S_S_FIN => finished_next <= '1'; s_cnt_next <= (0 => '1', others => '0'); d_new_result_next <= '1'; + when S_S_FIN_POSUP => + -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); when S_S_DONE => s_done_next <= '1'; if was_bs_int = '0' then @@ -210,10 +221,15 @@ begin end if; when S_D_INIT => - address_next <= d_spalte; + addr_tmp := (others => '0'); + addr_tmp(hzeile'length - 1 downto 0) := d_zeile; + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH)); + addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); + addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte)); + address_next <= addr_tmp; d_new_eingabe_next <= '0'; d_new_result_next <= '0'; - when S_D_WRITE => + when S_D_READ => d_char_next <= data_out; d_done_next <= '1'; end case; diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd index 4d39020..5c9b66b 100644 --- a/src/sp_ram.vhd +++ b/src/sp_ram.vhd @@ -20,7 +20,7 @@ end entity sp_ram; architecture beh of sp_ram is subtype RAM_ENTRY_TYPE is hbyte; type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE; - signal ram : RAM_TYPE := (others => x"00"); + signal ram : RAM_TYPE := (others => x"41"); begin process(sys_clk) begin