From: Bernhard Urban Date: Sat, 22 May 2010 07:39:52 +0000 (+0200) Subject: scanner: beh- und post-tb angepasst X-Git-Tag: abgabe~55 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=7a5b74318bcc702f114c99b53135dec67022c9bb scanner: beh- und post-tb angepasst --- diff --git a/quartus/project_scanner.tcl b/quartus/project_scanner.tcl new file mode 100644 index 0000000..44d9833 --- /dev/null +++ b/quartus/project_scanner.tcl @@ -0,0 +1,50 @@ +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "calc"]} { + puts "Project calc is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists calc]} { + project_open -revision calc calc + } else { + project_new -revision calc calc + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY Stratix + set_global_assignment -name DEVICE %DEVICE% + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name MISC_FILE "calc.dpf" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + + set_global_assignment -name TOP_LEVEL_ENTITY scanner + set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd + set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd + set_global_assignment -name VHDL_FILE ../../src/scanner.vhd + + #pin mapping/system + set_location_assignment PIN_N3 -to sys_clk + set_location_assignment PIN_AF17 -to sys_res_n + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/sim/screenshots/post_scanner.png b/sim/screenshots/post_scanner.png new file mode 100644 index 0000000..5b66f90 Binary files /dev/null and b/sim/screenshots/post_scanner.png differ diff --git a/src/TODO b/src/TODO index f53db39..9dcc181 100644 --- a/src/TODO +++ b/src/TODO @@ -21,3 +21,4 @@ - coverage fuer abgabe noetig? - bei -cover funktioniert 's' nicht, siehe http://pastebin.com/p8RwNk7j - wo sieht man f_max im quartus? +- wie detailiert muessen die screenshots der simulationen sein? diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd index f5a0a34..342b1c5 100644 --- a/src/beh_scanner_tb.vhd +++ b/src/beh_scanner_tb.vhd @@ -76,7 +76,7 @@ begin return y; end function; - function valid_char (x : std_logic_vector(7 downto 0); last : std_logic_vector(7 downto 0)) return boolean is + function valid_char (x : std_logic_vector(7 downto 0)) return boolean is variable y : boolean; begin case x is @@ -104,7 +104,6 @@ begin variable checkall : boolean := true; variable run_tc, run_inner : boolean := true; variable i, j, k, y : natural; - variable last : std_logic_vector(7 downto 0); begin -- init & reset sys_res_n <= '0'; @@ -165,7 +164,6 @@ begin j := 0; k := 1; mainl : while run_tc loop - last := data; icwait(sys_clk, 1); j := j + 1; @@ -180,14 +178,20 @@ begin case input(j) is when nul => data <= ascii2sc(x"1c"); -- $ (enter) when '!' => data <= ascii2sc(x"0e"); -- ! (backspace) + when '/' => + data <= x"e0"; + icwait(sys_clk, 1); + new_data <= '0'; + icwait(sys_clk, 1); + new_data <= '1'; + data <= SC_KP_DIV; when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8))); end case; icwait(sys_clk, 1); new_data <= '0'; - -- ack'en skippen, falls es ein "spezielles" zeichen ist (steht - -- in abhaengigkeit zum vorherigen zeichen) - if(not valid_char(data, last)) then + -- ack'en skippen, falls es ein "spezielles" zeichen ist + if(not valid_char(data)) then next mainl; end if; diff --git a/src/post_scanner_tb.do b/src/post_scanner_tb.do new file mode 100644 index 0000000..04e2a65 --- /dev/null +++ b/src/post_scanner_tb.do @@ -0,0 +1,23 @@ +#alias fuer simulation neustarten +alias rr "restart -f" + +#signale hinzufuegen +add wave sys_clk +add wave sys_res_n +add wave new_data +add wave data +add wave s_char +add wave s_take +add wave s_done +add wave s_backspace +add wave do_it +add wave finished + +#rauszoomen +wave zoomout 500.0 + +#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen) +run -all + +#ganz nach links scrollen +wave seetime 0 diff --git a/src/post_scanner_tb.vhd b/src/post_scanner_tb.vhd new file mode 100644 index 0000000..0a1ff83 --- /dev/null +++ b/src/post_scanner_tb.vhd @@ -0,0 +1,276 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.gen_pkg.all; + +entity post_scanner_tb is +end entity post_scanner_tb; + +architecture sim of post_scanner_tb is + component scanner is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- PS/2 + new_data : in std_logic; + data : in std_logic_vector(7 downto 0); + -- History + s_char : out hbyte; + s_take : out std_logic; + s_done : in std_logic; + s_backspace : out std_logic; + -- Parser + do_it : out std_logic; + finished : in std_logic + ); + end component scanner; + -- system + signal sys_clk, sys_res_n : std_logic; + -- ps/2 + signal new_data : std_logic; + signal data : std_logic_vector(7 downto 0); + -- history + signal s_char : hbyte; + signal s_take, s_done, s_backspace : std_logic; + -- parser + signal do_it : std_logic; + signal finished : std_logic; + + signal stop : boolean := false; +begin + inst : scanner + port map ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + -- ps/2 + new_data => new_data, + data => data, + -- history + s_char => s_char, + s_take => s_take, + s_done => s_done, + s_backspace => s_backspace, + -- Parser + do_it => do_it, + finished => finished + ); + + process + begin + sys_clk <= '0'; + wait for 15 ns; + sys_clk <= '1'; + wait for 15 ns; + if stop = true then + wait; + end if; + end process; + + process + function ascii2sc (x : hbyte) return hbyte is + variable y : hbyte; + begin + case x is + when x"30" => y := SC_KP_0; + when x"31" => y := SC_KP_1; + when x"32" => y := SC_KP_2; + when x"33" => y := SC_KP_3; + when x"34" => y := SC_KP_4; + when x"35" => y := SC_KP_5; + when x"36" => y := SC_KP_6; + when x"37" => y := SC_KP_7; + when x"38" => y := SC_KP_8; + when x"39" => y := SC_KP_9; + when x"2b" => y := SC_KP_PLUS; + when x"2d" => y := SC_KP_MINUS; + when x"2a" => y := SC_KP_MUL; + when x"2f" => y := SC_KP_DIV; + when x"20" => y := SC_SPACE; + when x"1c" => y := SC_ENTER; + when x"0e" => y := SC_BKSP; + when others => y := x"41"; + end case; + return y; + end function; + + function valid_char (x : std_logic_vector(7 downto 0)) return boolean is + variable y : boolean; + begin + case x is + when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 | + SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 | + SC_KP_8 | SC_KP_9 | SC_KP_PLUS | + SC_KP_MINUS | SC_KP_MUL | + SC_KP_DIV | SC_SPACE | + SC_BKSP | SC_ENTER => + y := true; + when others => y := false; + end case; + return y; + end function; + + -- textio stuff + use std.textio.all; + file f : text open read_mode is "../../src/scanner.test"; + variable l : line; + + variable input : hstring; + variable expectedresult : hstring; + variable realresult : hstring; + + variable checkall : boolean := true; + variable run_tc, run_inner : boolean := true; + variable i, j, k, y : natural; + begin + -- init & reset + sys_res_n <= '0'; + new_data <= '0'; + data <= (others => '0'); + s_done <= '0'; + finished <= '0'; + + icwait(sys_clk, 5); + sys_res_n <= '1'; + + i := 1; + f_loop : while not endfile(f) loop + data <= (others => '0'); + realresult := (others => nul); + + f1_loop : while not endfile(f) loop + readline (f, l); + input := (others => nul); + if (l'length <= 72) then + input(1 to l'length) := l.all; + if (input(1) = '#') then + next f1_loop; + else + exit f1_loop; + end if; + else + report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i); + next f_loop; + end if; + end loop f1_loop; + + f2_loop : while not endfile(f) loop + readline (f, l); + expectedresult := (others => nul); + if (l'length <= 72) then + expectedresult(1 to l'length) := l.all; + if (expectedresult(1) = '#') then + next f2_loop; + else + y := l'length; + exit f2_loop; + end if; + else + report "fehler in scanner.test: eingabe zu lange in testfall " & natural'image(i); + next f_loop; + end if; + end loop f2_loop; + + + + report "testcase(" & natural'image(i) & ").input: " & input; + report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult; + i := i + 1; + + icwait(sys_clk, 5); + run_tc := true; + j := 0; k := 1; + + mainl : while run_tc loop + icwait(sys_clk, 1); + j := j + 1; + + if j = 73 then + run_tc := false; + assert(false) report "wtf @ schleife"; + next mainl; + end if; + + new_data <= '1'; + + case input(j) is + when nul => data <= ascii2sc(x"1c"); -- $ (enter) + when '!' => data <= ascii2sc(x"0e"); -- ! (backspace) + when '/' => + data <= x"e0"; + icwait(sys_clk, 1); + new_data <= '0'; + icwait(sys_clk, 1); + new_data <= '1'; + data <= SC_KP_DIV; + when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8))); + end case; + icwait(sys_clk, 1); + new_data <= '0'; + + -- ack'en skippen, falls es ein "spezielles" zeichen ist + if(not valid_char(data)) then + next mainl; + end if; + + -- wuenschswert waere das hier: + -- > wait on s_backspace, s_take, do_it; + -- geht aber leider nicht, weil sich die signale vllt schon + -- geaendert haben + run_inner := true; + main_inner : while run_inner loop + icwait(sys_clk, 1); + + run_inner := false; + if s_backspace = '1' then + if k > 1 then + realresult(k) := nul; + k := k - 1; + realresult(k) := nul; + end if; + icwait(sys_clk, 1); + s_done <= '1'; + wait on s_take; -- = '0' + icwait(sys_clk, 1); + s_done <= '0'; + elsif do_it = '1' then + -- dauert normalweiser noch laenger (parser braucht + -- relativ lange) + icwait(sys_clk, 7); + finished <= '1'; + wait on do_it; -- = '0' + icwait(sys_clk, 1); + finished <= '0'; + + run_tc := false; + elsif s_take = '1' then + realresult(k) := character'val(to_integer(unsigned(s_char))); + k := k + 1; + + icwait(sys_clk, 1); + s_done <= '1'; + wait on s_take; -- = '0' + icwait(sys_clk, 1); + s_done <= '0'; + else + -- assert(false) report "scanner_tb: kann passieren. wenn tb haengt, dann hier auskommentieren"; + run_inner := true; + end if; + end loop; + end loop; + + report "realresult : " & realresult; + if realresult /= expectedresult then + checkall := false; + end if; + report "=================="; + end loop f_loop; + + if checkall then + report "alle testfaelle des Scanners waren erfolgreich!"; + else + report "nicht alle testfaelle des Scanners waren erfolgreich!"; + end if; + stop <= true; + wait; + end process; +end architecture sim;