From: Bernhard Urban Date: Thu, 27 May 2010 13:49:18 +0000 (+0200) Subject: pc_com: p_busy ist unnoetig und noch ein paar kleinere fehler ausgebessert X-Git-Tag: abgabe~11 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=5198223f6d43e915eed4be1d0bbbbc7f908ef6b1 pc_com: p_busy ist unnoetig und noch ein paar kleinere fehler ausgebessert ... beh_history dauert jetzt wirklich *lang* (ich schaetz so 15-20mins hat es jetzt bei mir gebraucht) logic: 2949 --- diff --git a/src/beh_history_tb.do b/src/beh_history_tb.do index fdb0009..61d841d 100644 --- a/src/beh_history_tb.do +++ b/src/beh_history_tb.do @@ -23,6 +23,10 @@ add wave inst/p_sp_write_int add wave inst/pos_int add wave inst_disp/d_zeile_int +add wave inst_pc_com/* +delete wave /beh_history_tb/inst_pc_com/sys_* +delete wave /beh_history_tb/inst_pc_com/*_next + #rauszoomen wave zoomout 500.0 diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index d05236a..87115c7 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -46,13 +46,9 @@ architecture sim of beh_history_tb is signal pc_spalte : hspalte; signal pc_get, pc_done : std_logic; signal pc_char : hbyte; - signal pc_busy : std_logic; --dummy button signal btn_a_int : std_logic; - --output beautifier - signal tx_debug : character; - signal stop : boolean := false; begin -- history @@ -87,7 +83,6 @@ begin pc_spalte => pc_spalte, pc_zeile => pc_zeile, pc_char => pc_char, - pc_busy => pc_busy, pc_done => pc_done ); @@ -176,10 +171,8 @@ begin pc_spalte => pc_spalte, pc_get => pc_get, pc_done => pc_done, - pc_char => pc_char, - pc_busy => pc_busy + pc_char => pc_char ); - tx_debug <= character'val(to_integer(unsigned(tx_data))); process begin @@ -310,7 +303,8 @@ begin report "=================="; end loop f_loop; - icwait(sys_clk, 850); + -- uart ist ziemlich langsam... + icwait(sys_clk, 1000000000); stop <= true; wait; end process; @@ -319,7 +313,7 @@ begin begin btn_a_int <= '1'; wait until sys_res_n = '1'; - wait for 50000 * 15 ns; + icwait(sys_clk, 50000); wait until rising_edge(sys_clk); btn_a_int <= '0'; wait for 30 ns; diff --git a/src/calc.vhd b/src/calc.vhd index 5f9b832..b967e1f 100644 --- a/src/calc.vhd +++ b/src/calc.vhd @@ -62,7 +62,6 @@ architecture top of calc is signal pc_zeile : hzeile; signal pc_char : hbyte; signal pc_done : std_logic; - signal pc_busy : std_logic; -- parser/scanner signal do_it, finished : std_logic; -- debouncing @@ -155,7 +154,6 @@ begin pc_spalte => pc_spalte, pc_zeile => pc_zeile, pc_char => pc_char, - pc_busy => pc_busy, pc_done => pc_done ); @@ -300,7 +298,6 @@ begin pc_zeile => pc_zeile, pc_spalte => pc_spalte, pc_get => pc_get, - pc_busy => pc_busy, pc_done => pc_done, pc_char => pc_char ); diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd index e1bfe68..fb699ef 100644 --- a/src/calc_s3e.vhd +++ b/src/calc_s3e.vhd @@ -63,7 +63,6 @@ architecture top of calc is signal pc_zeile : hzeile; signal pc_char : hbyte; signal pc_done : std_logic; - signal pc_busy : std_logic; -- parser/scanner signal do_it, finished : std_logic; -- rs232 @@ -155,7 +154,6 @@ begin pc_spalte => pc_spalte, pc_zeile => pc_zeile, pc_char => pc_char, - pc_busy => pc_busy, pc_done => pc_done ); @@ -271,7 +269,6 @@ begin pc_zeile => pc_zeile, pc_spalte => pc_spalte, pc_get => pc_get, - pc_busy => pc_busy, pc_done => pc_done, pc_char => pc_char ); diff --git a/src/history.vhd b/src/history.vhd index 7756204..3858b43 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -13,7 +13,6 @@ entity history is pc_zeile : in hzeile; pc_char : out hbyte; pc_done : out std_logic; - pc_busy : out std_logic; -- Scanner s_char : in hbyte; s_take : in std_logic; @@ -42,7 +41,7 @@ end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE, - S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ); + S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -60,7 +59,6 @@ architecture beh of history is signal p_sp_write_int, p_sp_write_next : hspalte; signal pc_char_next ,pc_char_int : hbyte; signal pc_done_next, pc_done_int : std_logic; - signal pc_busy_next, pc_busy_int : std_logic; -- ram signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -77,7 +75,6 @@ begin p_wdone <= p_wdone_int; p_read <= p_read_int; pc_done <= pc_done_int; - pc_busy <= pc_busy_int; pc_char <= pc_char_int; process(sys_clk, sys_res_n) @@ -103,7 +100,6 @@ begin pc_char_int <= (others => '0'); pc_done_int <= '0'; - pc_busy_int <= '0'; address_int <= (0 => '1', others => '0'); data_in_int <= x"00"; @@ -129,7 +125,6 @@ begin pc_char_int <= pc_char_next; pc_done_int <= pc_done_next; - pc_busy_int <= pc_busy_next; address_int <= address_next; data_in_int <= data_in_next; @@ -201,8 +196,6 @@ begin state_next <= SIDLE; end if; when S_PC_INIT => - state_next <= S_PC_DUMMY; - when S_PC_DUMMY => state_next <= S_PC_READ; when S_PC_READ => if pc_get = '0' then @@ -248,7 +241,6 @@ begin data_in_next <= data_in_int; pc_done_next <= '0'; pc_char_next <= pc_char_int; - pc_busy_next <= '0'; p_rdone_next <= p_rdone_int; p_wdone_next <= p_wdone_int; p_read_next <= p_read_int; @@ -340,8 +332,7 @@ begin when S_D_INIT => addr_tmp := (others => '0'); addr_tmp(hzeile'length - 1 downto 0) := d_zeile; - mul_tmp := std_logic_vector(unsigned(addr_tmp) * - to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte)); address_next <= addr_tmp; @@ -358,12 +349,10 @@ begin addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte)); address_next <= addr_tmp; - pc_busy_next <= '1'; - when S_PC_DUMMY => - pc_busy_next <= '1'; when S_PC_READ => - pc_char_next <= data_out; pc_done_next <= '1'; + pc_char_next <= data_out; + when S_P_READ => wr_next <= '0'; spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1); diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd index b593b33..c422ed7 100644 --- a/src/pc_communication.vhd +++ b/src/pc_communication.vhd @@ -24,26 +24,22 @@ entity pc_communication is pc_zeile : out hzeile; pc_spalte : out hspalte; pc_get : out std_logic; - pc_busy : in std_logic; --signals if the history module actually grants our request. pc_done : in std_logic; pc_char : in hbyte ); end entity pc_communication; architecture beh of pc_communication is - signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1; - signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1; + signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2; + signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1; signal get, get_next : std_logic; signal new_i, new_i_next : std_logic; signal tx_done_i, tx_done_i_next : std_logic; signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0); - type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE); + type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL); signal state, state_next : STATE_PC ; - begin - - pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7))); pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7))); pc_get <= get; @@ -56,10 +52,10 @@ begin if sys_res_n = '0' then state <= IDLE; spalte <= 1; - zeile <= 1; + zeile <= 0; get <= '0'; new_i <= '0'; - tx_data_i <= "00000000"; + tx_data_i <= x"00"; tx_done_i <= '0'; elsif rising_edge(sys_clk) then spalte <= spalte_next; @@ -86,28 +82,34 @@ begin null; when FETCH => get_next <= '1'; - when WAIT_HIST => - tx_data_i_next <= pc_char; when FORWARD => + tx_data_i_next <= pc_char; new_i_next <= '1'; + -- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt + get_next <= '1'; when WAIT_UART => new_i_next <= '1'; - when UART_DONE => - if tx_data_i = x"00" or spalte = HSPALTE_MAX then + get_next <= '1'; + when UART_DONE => null; + -- get_next <= '0'; + -- new_i_next <= '0'; + when CALC_VAL => + spalte_next <= spalte + 1; + if spalte = HSPALTE_MAX + 1 then tx_data_i_next <= x"0a"; - zeile_next <= zeile + 1; + new_i_next <= '1'; + spalte_next <= 1; - if zeile = HZEILE_MAX then - zeile_next <= 1; + zeile_next <= zeile + 1; + if zeile = HZEILE_MAX-1 then + zeile_next <= 0; end if; - else - spalte_next <= spalte + 1; end if; end case; end process output_pc; - next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte, - state, tx_data_i ,tx_done_i, zeile) + next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state, + tx_data_i ,tx_done_i, zeile, pc_char) begin state_next <= state; case state is @@ -117,14 +119,12 @@ begin state_next <= FETCH; end if; when FETCH => - if pc_busy = '1' then - state_next <= WAIT_HIST; - else - state_next <= FETCH; - end if; - when WAIT_HIST => - if (pc_done = '1') then - state_next <= FORWARD; + if pc_done = '1' and tx_done_i = '0' then + if pc_char = x"00" then + state_next <= UART_DONE; + else + state_next <= FORWARD; + end if; end if; when FORWARD => state_next <= WAIT_UART; @@ -133,13 +133,13 @@ begin state_next <= UART_DONE; end if; when UART_DONE => - if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and - zeile = HZEILE_MAX then + state_next <= CALC_VAL; + when CALC_VAL => + if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then state_next <= IDLE; else state_next <= FETCH; end if; end case; end process next_state_pc; - end architecture beh;