From: Bernhard Urban <lewurm@gmail.com>
Date: Sun, 16 May 2010 10:29:28 +0000 (+0200)
Subject: history: ram modul hinzugefuegt
X-Git-Tag: flashable_w00t~6
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=437b9856043060d90cf468d725555a77c265c71e

history: ram modul hinzugefuegt
---

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index f8846a4..9c46c01 100644
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -45,6 +45,7 @@ if {$make_assignments} {
 	set_global_assignment -name VHDL_FILE ../../src/parser.vhd
 	set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
 	set_global_assignment -name VHDL_FILE ../../src/display.vhd
+	set_global_assignment -name VHDL_FILE ../../src/sp_ram.vhd
 	set_global_assignment -name VHDL_FILE ../../src/history.vhd
 	set_global_assignment -name VHDL_FILE ../../src/calc.vhd
 	set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
diff --git a/src/Makefile b/src/Makefile
index 55a3114..f0382f1 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -24,11 +24,11 @@ WORK := work
 # o source files der module
 # o reihenfolge ist wichtig
 # o keine testbechnes hier angeben
-SRCFILES := alu parser scanner display history
+SRCFILES := alu parser scanner display sp_ram history
 
 # o files der packages
 # o keine testbechnes hier angeben
-PKGFILES = gen_pkg math_pkg
+PKGFILES = math_pkg gen_pkg
 PKGFILES += textmode_vga/textmode_vga_platform_dependent_pkg
 PKGFILES += textmode_vga/textmode_vga_pkg
 PKGFILES += textmode_vga/font_pkg
diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index 0121290..a897b0a 100644
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -1,6 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.math_pkg.all;
 
 package gen_pkg is
 	subtype alu_ops is std_logic_vector(2 downto 0);
@@ -17,6 +18,11 @@ package gen_pkg is
 	-- integer ist 32bit (31bit + sign)
 	subtype cinteger is integer;
 
+	-- vorerst: 2 * 71
+	-- constant H_RAM_SIZE : integer := 142;
+	-- danach: 50 * 71 * 2 = 7100
+	constant H_RAM_SIZE : integer := 7100;
+	constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
 	subtype hspalte is std_logic_vector(6 downto 0);
 	subtype hzeile is std_logic_vector(4 downto 0);
 	subtype hbyte is std_logic_vector(7 downto 0);
diff --git a/src/history.vhd b/src/history.vhd
index cf130ec..fc0abbe 100644
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -41,6 +41,11 @@ architecture beh of history is
 	signal d_char_int, d_char_next : hbyte;
 
 	signal finished_int, finished_next : std_logic;
+
+	-- ram
+	signal address, address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+	signal data_out, data_in, data_in_next, data_in_int : hbyte;
+	signal wr, wr_next, wr_int : std_logic;
 begin
 	s_done <= s_done_int;
 	d_new_eingabe <= d_new_eingabe_int;
@@ -50,6 +55,10 @@ begin
 
 	finished <= finished_int;
 
+	address <= address_int;
+	data_in <= data_in_int;
+	wr <= wr_int;
+
 	process(sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
@@ -63,6 +72,10 @@ begin
 			d_char_int <= (others => '0');
 
 			finished_int <= '0';
+
+			address_int <= (others => '0');
+			data_in_int <= x"00";
+			wr_int <= '0';
 		elsif rising_edge(sys_clk) then
 			-- internal
 			state_int <= state_next;
@@ -74,6 +87,10 @@ begin
 			d_char_int <= d_char_next;
 
 			finished_int <= finished_next;
+
+			address_int <= address_next;
+			data_in_int <= data_in_next;
+			wr_int <= wr_next;
 		end if;
 	end process;
 
@@ -96,4 +113,17 @@ begin
 				null;
 		end case;
 	end process;
+
+	sp_ram_inst : entity work.sp_ram(beh)
+	generic map (
+		ADDR_WIDTH => H_RAM_WIDTH
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		address => address,
+		data_out => data_out,
+		wr => wr,
+		data_in => data_in
+	);
 end architecture beh;
diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
new file mode 100644
index 0000000..a2a2371
--- /dev/null
+++ b/src/sp_ram.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+-- "synchronous single port RAM
+entity sp_ram is
+	generic (
+		ADDR_WIDTH : integer range 1 to integer'high
+	);
+	port (
+		sys_clk : in std_logic;
+		sys_res_n : in std_logic;
+		address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+		data_out : out hbyte;
+		wr : in std_logic;
+		data_in : in hbyte
+	);
+end entity sp_ram;
+
+architecture beh of sp_ram is
+	subtype RAM_ENTRY_TYPE is hbyte;
+	type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH) - 1) of RAM_ENTRY_TYPE;
+	signal ram : RAM_TYPE := (others => x"00");
+begin
+	process(sys_clk, sys_res_n)
+	begin
+		if sys_res_n = '0' then
+			ram <= (others => x"00");
+		elsif rising_edge(sys_clk) then
+			data_out <= ram(to_integer(unsigned(address)));
+			if wr = '1' then
+				ram(to_integer(unsigned(address))) <= data_in;
+			end if;
+		end if;
+	end process;
+end architecture beh;