From: Bernhard Urban <lewurm@gmail.com>
Date: Sun, 16 May 2010 09:45:47 +0000 (+0200)
Subject: top-level: weiteres portmapping fuer minimalsetup
X-Git-Tag: flashable_w00t~7
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=38a03425c6cbd469804cd79983e2d35d8ecca453

top-level: weiteres portmapping fuer minimalsetup
---

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index 62d62a3..f8846a4 100644
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -41,10 +41,12 @@ if {$make_assignments} {
 	#include source files
 	set_global_assignment -name TOP_LEVEL_ENTITY calc
 	set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
-	set_global_assignment -name VHDL_FILE ../../src/calc.vhd
 	set_global_assignment -name VHDL_FILE ../../src/alu.vhd
 	set_global_assignment -name VHDL_FILE ../../src/parser.vhd
 	set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
+	set_global_assignment -name VHDL_FILE ../../src/display.vhd
+	set_global_assignment -name VHDL_FILE ../../src/history.vhd
+	set_global_assignment -name VHDL_FILE ../../src/calc.vhd
 	set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
 	
 	#vga ip-core
diff --git a/src/calc.vhd b/src/calc.vhd
index 922a2a6..cda8ee2 100644
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -28,10 +28,26 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+	-- ps/2
+	signal new_data : std_logic;
+	signal data : std_logic_vector(7 downto 0);
 	-- vga
 	signal vga_clk, free : std_logic;
+	-- vga/display
 	signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
 	signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
+	-- history/display
+	signal d_new_eingabe, d_new_result : std_logic;
+	signal d_zeile : hzeile;
+	signal d_spalte : hspalte;
+	signal d_get, d_done : std_logic;
+	signal d_char : hbyte;
+	-- history/scanner
+	signal s_char : hbyte;
+	signal s_take, s_done, s_backspace : std_logic;
+
+	-- tmp: history<>scanner
+	signal do_it, finished : std_logic;
 begin
 	-- vga/ipcore
 	textmode_vga_inst : entity work.textmode_vga(struct)
@@ -62,9 +78,80 @@ begin
 		c0 => vga_clk
 	);
 
-	-- TODO: display
-	-- TODO: history
-	-- TODO: scanner
-	-- TODO: ps/2
+	-- display
+	display_inst : entity work.display(beh)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		-- history
+		d_new_eingabe => d_new_eingabe,
+		d_new_result => d_new_result,
+		d_zeile => d_zeile,
+		d_spalte => d_spalte,
+		d_get => d_get,
+		d_done => d_done,
+		d_char => d_char,
+		-- vga
+		command => command,
+		command_data => command_data,
+		free => free
+	);
+
+	-- history
+	history_inst : entity work.history(beh)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		-- scanner
+		s_char => s_char,
+		s_take => s_take,
+		s_done => s_done,
+		s_backspace => s_backspace,
+		-- display
+		d_new_eingabe => d_new_eingabe,
+		d_new_result => d_new_result,
+		d_zeile => d_zeile,
+		d_spalte => d_spalte,
+		d_get => d_get,
+		d_done => d_done,
+		d_char => d_char,
+		-- TODO: tmp only!
+		do_it => do_it,
+		finished => finished
+	);
+
+	-- scanner
+	scanner_inst : entity work.scanner(beh)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		-- ps/2
+		new_data => new_data,
+		data => data,
+		-- history
+		s_char => s_char,
+		s_take => s_take,
+		s_done => s_done,
+		s_backspace => s_backspace,
+		-- TODO: parser. temporaer mit history verbunden
+		do_it => do_it,
+		finished => finished
+	);
+
+	-- ps/2
+	ps2_inst : entity work.ps2_keyboard_controller(beh)
+	generic map (
+		CLK_FREQ => 33330000,
+		SYNC_STAGES => 2
+	)
+	port map (
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		-- scanner
+		new_data => new_data,
+		data => data,
+		ps2_clk => ps2_clk,
+		ps2_data => ps2_data
+	);
 end architecture top;
 
diff --git a/src/history.vhd b/src/history.vhd
index 3031c22..cf130ec 100644
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -21,9 +21,13 @@ entity history is
 		d_spalte : in hspalte;
 		d_get : in std_logic;
 		d_done : out std_logic;
-		d_char : out hbyte
+		d_char : out hbyte;
 		-- Parser
 		-- TODO: pins
+
+		-- TODO: tmp only!
+		do_it : in std_logic;
+		finished : out std_logic
 	);
 end entity history;
 
@@ -35,6 +39,8 @@ architecture beh of history is
 	signal d_new_result_int, d_new_result_next : std_logic;
 	signal d_done_int, d_done_next : std_logic;
 	signal d_char_int, d_char_next : hbyte;
+
+	signal finished_int, finished_next : std_logic;
 begin
 	s_done <= s_done_int;
 	d_new_eingabe <= d_new_eingabe_int;
@@ -42,6 +48,8 @@ begin
 	d_done <= d_done_int;
 	d_char <= d_char_int;
 
+	finished <= finished_int;
+
 	process(sys_clk, sys_res_n)
 	begin
 		if sys_res_n = '0' then
@@ -53,6 +61,8 @@ begin
 			d_new_eingabe_int <= '0';
 			d_done_int <= '0';
 			d_char_int <= (others => '0');
+
+			finished_int <= '0';
 		elsif rising_edge(sys_clk) then
 			-- internal
 			state_int <= state_next;
@@ -62,6 +72,8 @@ begin
 			d_new_eingabe_int <= d_new_eingabe_next;
 			d_done_int <= d_done_next;
 			d_char_int <= d_char_next;
+
+			finished_int <= finished_next;
 		end if;
 	end process;