From: Bernhard Urban <lewurm@gmail.com>
Date: Wed, 19 May 2010 23:39:45 +0000 (+0200)
Subject: display: arbeitet endlich wie gewuenscht
X-Git-Tag: alpha~9
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=1174010c4fd11ff9111732a2a7d31be18a02bf46

display: arbeitet endlich wie gewuenscht
---

diff --git a/src/display.vhd b/src/display.vhd
index 17a717e..55d07fc 100644
--- a/src/display.vhd
+++ b/src/display.vhd
@@ -34,6 +34,7 @@ architecture beh of display is
 	signal d_get_int, d_get_next : std_logic;
 	signal command_int, command_next : std_logic_vector(7 downto 0);
 	signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
+	signal istate_next, istate_int : signed(2 downto 0);
 begin
 	d_zeile <= d_zeile_int;
 	d_spalte <= d_spalte_int;
@@ -46,6 +47,7 @@ begin
 		if sys_res_n = '0' then
 			-- internal
 			state_int <= S_INIT;
+			istate_int <= (others => '0');
 			-- out
 			d_zeile_int <= (others => '0');
 			d_spalte_int <= (others => '0');
@@ -55,6 +57,7 @@ begin
 		elsif rising_edge(sys_clk) then
 			-- internal
 			state_int <= state_next;
+			istate_int <= istate_next;
 			-- out
 			d_zeile_int <= d_zeile_next;
 			d_spalte_int <= d_spalte_next;
@@ -66,9 +69,10 @@ begin
 
 	-- next state
 	process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
-		d_char)
+		d_char, istate_int)
 	begin
 		state_next <= state_int;
+		istate_next <= istate_int;
 
 		case state_int is
 			when S_INIT =>
@@ -86,11 +90,13 @@ begin
 				state_next <= S_COUNTUP;
 			when S_CR1 =>
 				if free = '0' then
-					state_next <= S_NL1;
+					state_next <= S_WAIT;
+					istate_next <= b"000"; -- => danach S_NL1
 				end if;
 			when S_NL1 =>
 				if free = '0' then
-					state_next <= S_COUNTUP;
+					state_next <= S_WAIT;
+					istate_next <= b"111";
 				end if;
 			when S_COUNTUP =>
 				state_next <= S_GETCH;
@@ -103,6 +109,7 @@ begin
 			when S_PUTCH2 =>
 				if free = '0' or (free = '1' and d_char = x"00") then
 					state_next <= S_WAIT;
+					istate_next <= b"111";
 				end if;
 			when S_WAIT =>
 				if free = '1' and d_done = '0' then
@@ -110,12 +117,10 @@ begin
 				end if;
 			when S_NOP1 =>
 				if free = '1' then
-					state_next <= SIDLE;
-					--if unsigned(d_spalte_int) = 71 then
-					--	state_next <= SIDLE;
-					--else
-					--	state_next <= S_COUNTUP;
-					--end if;
+					case istate_int is
+						when b"000" => state_next <= S_NL1;
+						when others => state_next <= SIDLE;
+					end case;
 				end if;
 		end case;
 	end process;
diff --git a/src/history.vhd b/src/history.vhd
index 1c69612..ae5d2e9 100644
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -153,10 +153,11 @@ begin
 		data_in_next <= data_in_int;
 
 		case state_int is
-			when SIDLE =>
-				null;
 			when S_S_INIT =>
 				null;
+			when SIDLE =>
+				-- TODO: tmp fix
+				d_new_result_next <= '0';
 			when S_S_WRITE =>
 				wr_next <= '1';
 				address_next <= s_cnt_int;
diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd
index de0f668..4d39020 100644
--- a/src/sp_ram.vhd
+++ b/src/sp_ram.vhd
@@ -20,8 +20,7 @@ end entity sp_ram;
 architecture beh of sp_ram is
 	subtype RAM_ENTRY_TYPE is hbyte;
 	type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE;
-	signal ram : RAM_TYPE := (1 => x"41", 2 => x"42", 3 => x"43", 4 => x"44",
-	5 => x"45", 6 => x"46", 7 => x"47", 8 => x"48", 9 => x"49", 10 => x"50", others => x"00");
+	signal ram : RAM_TYPE := (others => x"00");
 begin
 	process(sys_clk)
 	begin