From: Bernhard Urban Date: Fri, 21 May 2010 20:32:19 +0000 (+0200) Subject: history: clear ram on reset X-Git-Tag: abgabe~66 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=09b4e91e343349c7c4c3b0e06fd4e2b79b8d95e6 history: clear ram on reset history: quartuswarning fix fuer RAM (aber nicht alle warnings eliminiert) history/display: handling bei > 50 eingaben, dazu muss auch vor jeder neuen eingabe der speicherbereich der verwendet werden soll, gecleart werden --- diff --git a/src/TODO b/src/TODO index 1bcbbf6..3a619e9 100644 --- a/src/TODO +++ b/src/TODO @@ -2,20 +2,13 @@ hernehmen -- rs232/pc-kommunikation - 1. schauen ob die eintraege der "einfachen" history gedumpt werden. - - 2. history komplett fertig stellen (da wir dann eine gute debug moeglichkeit - haben) +- rs232/pc-kommunikation: RAM dumpen - alu postlayout noch an die neue alu anpassen (... wenn das projekt final is), dass ma eine postlayoutsim bei der abgabe zum herzeigen haben -- was passiert nach 50 berechnungen? - - - scanner rewrite: nicht bei key-release sondern bei key-pressed o vorteil: man kann auf der taste drauf bleiben und man kann keine zahlen mehr mit den coursertasten eingeben diff --git a/src/beh_history_tb.do b/src/beh_history_tb.do index ffd92e7..0299a32 100644 --- a/src/beh_history_tb.do +++ b/src/beh_history_tb.do @@ -19,6 +19,9 @@ add wave inst_parser/state_int add wave inst/p_sp_read_int add wave inst/p_sp_write_int +add wave inst/pos_int +add wave inst_disp/d_zeile_int + #rauszoomen wave zoomout 500.0 diff --git a/src/display.vhd b/src/display.vhd index fb6649f..2499ef4 100644 --- a/src/display.vhd +++ b/src/display.vhd @@ -286,8 +286,8 @@ begin when S_ZEILEUP => d_spalte_next <= (others => '0'); case d_zeile_int is - -- 49 * 2 + 1 - when "1100010" => d_zeile_next <= (others => '0'); + when + std_logic_vector(to_unsigned((49*2)+1,d_zeile_int'length)) => d_zeile_next <= (others => '0'); when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1); end case; diff --git a/src/history.test b/src/history.test index 578998e..922b753 100644 --- a/src/history.test +++ b/src/history.test @@ -1,6 +1,8 @@ # readme: folgende spezialzeichen werden zum testen verwendet # ! ... Backspace # +#t0: +123+12 # testfall 1: asdf213 # testfall 2: @@ -12,3 +14,93 @@ asdf213 # testfall 5: # ab "999" sind es zu viele zeichen. danach folgt einmal backspace und ein 1er 3333333333333333333333333333333333333333333333333333333333333333333333999!1 +# t7: +1+1 +# t8: +1+1 +# t9: +1+1 +# t10: +1+1 +# t11: +1+1 +# t12: +1+1 +# t13: +1+1 +# t14: +1+1 +# t15: +1+1 +# t16: +1+1 +# t17: +1+1 +# t18: +1+1 +# t19: +1+1 +# t20: +1+1 +# t21: +1+1 +# t22: +1+1 +# t23: +1+1 +# t24: +1+1 +# t25: +1+1 +# t26: +1+1 +# t27: +1+1 +# t28: +1+1 +# t29: +1+1 +# t30: +1+1 +# t31: +1+1 +# t32: +1+1 +# t33: +1+1 +# t34: +1+1 +# t35: +1+1 +# t36: +1+1 +# t37: +1+1 +# t38: +1+1 +# t39: +1+1 +# t40: +1+1 +# t41: +1+1 +# t42: +1+1 +# t43: +1+1 +# t44: +1+1 +# t45: +1+1 +# t46: +1+1 +# t47: +1+1 +# t48: +1+1337 +# t49: +123412-1248 +# t50: +kacka1234-12 +# t51: +lol148 diff --git a/src/history.vhd b/src/history.vhd index cf091e3..9a65e59 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -37,7 +37,7 @@ end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE, - S_P_WRITE_DONE, S_P_DONE); + S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -73,7 +73,7 @@ begin begin if sys_res_n = '0' then -- internal - state_int <= SIDLE; + state_int <= S_INIT; was_bs_int <= '0'; pos_int <= (others => '0'); -- out @@ -120,11 +120,17 @@ begin -- next state process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int, - p_rget, p_wtake) + p_rget, p_wtake, pos_int, s_cnt_int) begin state_next <= state_int; case state_int is + when S_INIT => + -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt + -- noetig, aber spaetestens fuers dumpen per rs232 + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then + state_next <= SIDLE; + end if; when SIDLE => -- S_S_FIN: tmp.. if s_take = '1' then @@ -153,7 +159,15 @@ begin state_next <= S_S_FIN_POSUP; end if; when S_S_FIN_POSUP => - state_next <= SIDLE; + state_next <= S_S_CLEAR_NEXT0; + when S_S_CLEAR_NEXT0 => + if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + state_next <= S_S_CLEAR_NEXT1; + end if; + when S_S_CLEAR_NEXT1 => + if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + state_next <= SIDLE; + end if; when S_S_DONE => if s_take = '0' then state_next <= SIDLE; @@ -211,6 +225,15 @@ begin p_sp_write_next <= p_sp_write_int; case state_int is + when S_INIT => + wr_next <= '1'; + address_next <= pos_int; + data_in_next <= (others => '0'); + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then + pos_next <= (others => '0'); + else + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH)); + end if; when SIDLE => -- TODO: tmp fix d_new_result_next <= '0'; @@ -250,8 +273,32 @@ begin p_sp_read_next <= (others => '0'); p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length)); when S_S_FIN_POSUP => - -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen - pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); + -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then + pos_next <= (others => '0'); + else + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); + end if; + when S_S_CLEAR_NEXT0 => + -- die naechsten 142 bytes im speicher resetten + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); + data_in_next <= (others => '0'); + if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + s_cnt_next <= (0 => '1', others => '0'); + else + s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); + end if; + when S_S_CLEAR_NEXT1 => + -- die naechsten 142 bytes im speicher resetten + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int)); + data_in_next <= (others => '0'); + if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then + s_cnt_next <= (0 => '1', others => '0'); + else + s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); + end if; when S_S_DONE => s_done_next <= '1'; if was_bs_int = '0' then diff --git a/src/sp_ram.vhd b/src/sp_ram.vhd index 4d39020..66b23d2 100644 --- a/src/sp_ram.vhd +++ b/src/sp_ram.vhd @@ -19,7 +19,7 @@ end entity sp_ram; architecture beh of sp_ram is subtype RAM_ENTRY_TYPE is hbyte; - type RAM_TYPE is array (1 to (2 ** ADDR_WIDTH)) of RAM_ENTRY_TYPE; + type RAM_TYPE is array (0 to (2 ** ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; signal ram : RAM_TYPE := (others => x"00"); begin process(sys_clk)