From: Bernhard Urban Date: Sun, 16 May 2010 00:25:37 +0000 (+0200) Subject: quartus: nur noch ein tcl skript... X-Git-Tag: flashable_w00t~12 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=commitdiff_plain;h=00b04ab2e13e864bca89f80f211e887f2973c156 quartus: nur noch ein tcl skript... --- diff --git a/.gitignore b/.gitignore index 9dc857a..b150b26 100644 --- a/.gitignore +++ b/.gitignore @@ -22,3 +22,5 @@ src/transcript #quartus quartus/calc/ src/quartus*.tmp +quartus/project_web.tcl +quartus/project_tilab.tcl diff --git a/quartus/linux_tilab.sh b/quartus/linux_tilab.sh index ebed0db..dcfd9b4 100755 --- a/quartus/linux_tilab.sh +++ b/quartus/linux_tilab.sh @@ -1,6 +1,8 @@ #!/bin/sh unset LS_COLORS +sed -e 's/%DEVICE%/EP1S25F672C6/g' project_gen.tcl > project_tilab.tcl mkdir -p calc cd calc quartus_sh -t ../project_tilab.tcl cd .. +#EP1S25F672C6 diff --git a/quartus/linux_web.sh b/quartus/linux_web.sh index 47b6381..a6d0b4a 100755 --- a/quartus/linux_web.sh +++ b/quartus/linux_web.sh @@ -1,6 +1,8 @@ #!/bin/sh unset LS_COLORS +sed -e 's/%DEVICE%/EP1S10F672C6/g' project_gen.tcl > project_web.tcl mkdir -p calc cd calc quartus_sh -t ../project_web.tcl cd .. +#EP1S10F672C6 diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl new file mode 100644 index 0000000..40dc720 --- /dev/null +++ b/quartus/project_gen.tcl @@ -0,0 +1,61 @@ +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "calc"]} { + puts "Project calc is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists calc]} { + project_open -revision calc calc + } else { + project_new -revision calc calc + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY Stratix + set_global_assignment -name DEVICE %DEVICE% + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name MISC_FILE "calc.dpf" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + + #set_global_assignment -name TOP_LEVEL_ENTITY calc + set_global_assignment -name TOP_LEVEL_ENTITY scanner + set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd + #set_global_assignment -name VHDL_FILE ../../src/calc.vhd + set_global_assignment -name VHDL_FILE ../../src/alu.vhd + set_global_assignment -name VHDL_FILE ../../src/parser.vhd + set_global_assignment -name VHDL_FILE ../../src/scanner.vhd + + set_location_assignment PIN_N3 -to sys_clk + set_location_assignment PIN_AF17 -to sys_res_n + + set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk + set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk + + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/quartus/project_tilab.tcl b/quartus/project_tilab.tcl deleted file mode 100755 index 256fe65..0000000 --- a/quartus/project_tilab.tcl +++ /dev/null @@ -1,60 +0,0 @@ -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "calc"]} { - puts "Project calc is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists calc]} { - project_open -revision calc calc - } else { - project_new -revision calc calc - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY Stratix - set_global_assignment -name DEVICE EP1S25F672C6 - set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga - set_global_assignment -name MISC_FILE "calc.dpf" - set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" - set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" - - #set_global_assignment -name TOP_LEVEL_ENTITY calc - set_global_assignment -name TOP_LEVEL_ENTITY parser - set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd - #set_global_assignment -name VHDL_FILE ../../src/calc.vhd - set_global_assignment -name VHDL_FILE ../../src/alu.vhd - set_global_assignment -name VHDL_FILE ../../src/parser.vhd - - set_location_assignment PIN_N3 -to sys_clk - set_location_assignment PIN_AF17 -to sys_res_n - - set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk - set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk - - set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" - set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments - - # Close project - if {$need_to_close_project} { - project_close - } -} diff --git a/quartus/project_web.tcl b/quartus/project_web.tcl deleted file mode 100755 index 5d297b1..0000000 --- a/quartus/project_web.tcl +++ /dev/null @@ -1,60 +0,0 @@ -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "calc"]} { - puts "Project calc is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists calc]} { - project_open -revision calc calc - } else { - project_new -revision calc calc - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY Stratix - set_global_assignment -name DEVICE EP1S10F672C6 - set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga - set_global_assignment -name MISC_FILE "calc.dpf" - set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" - set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" - - #set_global_assignment -name TOP_LEVEL_ENTITY calc - set_global_assignment -name TOP_LEVEL_ENTITY parser - set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd - #set_global_assignment -name VHDL_FILE ../../src/calc.vhd - set_global_assignment -name VHDL_FILE ../../src/alu.vhd - set_global_assignment -name VHDL_FILE ../../src/parser.vhd - - set_location_assignment PIN_N3 -to sys_clk - set_location_assignment PIN_AF17 -to sys_res_n - - set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk - set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk - - set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" - set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments - - # Close project - if {$need_to_close_project} { - project_close - } -}