added waiting states to pccom

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 94af8430a5497e8bd72d633a60a1d9483a832f84..bb15b065194f9e32f24de8d848af9baa674229f8 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -36,9 +36,8 @@ architecture beh of pc_communication is
        signal new_i, new_i_next : std_logic;
        signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
-       signal s_done, s_done_next : std_logic;
 
-       type STATE_PC is (IDLE, FETCH, FORWARD, DONE);
+       type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
        signal state, state_next : STATE_PC ;
 
 begin
@@ -61,7 +60,6 @@ begin
                        new_i <= '0';
                        tx_data_i <= "00000000";
                        tx_done_i <= '0';
-                       s_done <= '0';
                elsif rising_edge(sys_clk) then
                        spalte <= spalte_next;
                        zeile <= zeile_next;
@@ -70,57 +68,43 @@ begin
                        new_i <= new_i_next;
                        tx_done_i <= tx_done_i_next;
                        tx_data_i <= tx_data_i_next;
-                       s_done <= s_done_next;
                end if;
        end process sync;
 
        output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
-       variable spalte_up : std_logic;
        begin
                get_next <= '0';
                new_i_next <= '0';
 
-               s_done_next <= '0';
                spalte_next <= spalte;
                zeile_next <= zeile;
                tx_data_i_next <= tx_data_i;
-               spalte_up := '0';
 
                case state is
                        when IDLE =>
                                null;
                        when FETCH =>
                                get_next <= '1';
+                       when WAIT_HIST =>
                                tx_data_i_next <= d_char;
                        when FORWARD =>
                                new_i_next <= '1';
-                               if (tx_done_i = '1') then
-                                       spalte_up := '1';
-                               end if;
-
-                       when DONE =>
+                       when WAIT_UART =>
                                null;
-               end case;
-
-               if spalte_up = '1' then
-                       if spalte = hspalte_max  then
-                               if zeile = hzeile_max then
+                       when UART_DONE =>
+                               if tx_data_i = x"00" or spalte = hspalte_max then
+                                       zeile_next <= zeile + 1;
                                        spalte_next <= 1;
-                                       zeile_next <= 1;
-                                       s_done_next <= '1';
+                                       if zeile = hzeile_max then
+                                               zeile_next <= 1;
+                                       end if;
                                else
-                                       spalte_next <= 1;
-                                       zeile_next <= zeile + 1;
+                                       spalte_next <= spalte + 1;
                                end if;
-                       else
-                               spalte_next <= spalte + 1; --overflow here!
-                               zeile_next <= zeile;
-                       end if;
-               end if;
-
+               end case;
        end process output_pc;
 
-       next_state_pc : process (state, rx_new, rx_data, btn_a, d_done, tx_done_i, s_done)
+       next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
        begin
                state_next <= state;
                case state is
@@ -129,17 +113,24 @@ begin
                                        state_next <= FETCH;
                                end if;
                        when FETCH =>
+                               state_next <= WAIT_HIST;
+                       when WAIT_HIST =>
                                if (d_done = '1') then
                                        state_next <= FORWARD;
-                               elsif (s_done = '1') then
-                                       state_next <= IDLE;
                                end if;
                        when FORWARD =>
+                               state_next <= WAIT_UART;
+                       when WAIT_UART =>
                                if (tx_done_i = '1') then
+                                       state_next <= UART_DONE;
+                               end if;
+                       when UART_DONE =>
+                               if (tx_data_i = x"00" or spalte = hspalte_max) and
+                                       zeile = hzeile_max then
+                                       state_next <= IDLE;
+                               else
                                        state_next <= FETCH;
                                end if;
-                       when DONE =>
-                               state_next <= IDLE;
                end case;
        end process next_state_pc;