X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fpc_communication.vhd;h=8a29ba7976e6b6c802c7a372b6e6800c91ecec7d;hp=410bc4fbb05aa0674f9e0eab1aa024bfa3da3b4d;hb=78b81af08fdecb68941b50aa298dc6b8492ce770;hpb=7b885817d4224b311880d3c50cbfe176e1c7c6b4

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 410bc4f..8a29ba7 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -7,19 +7,15 @@ entity pc_communication is
 	port (
 		sys_clk : in std_logic;
 		sys_res_n : in std_logic;
-
 		--button
 		btn_a : in std_logic;
-
 		--uart_tx
 		tx_data : out std_logic_vector(7 downto 0);
 		tx_new : out std_logic;
 		tx_done : in std_logic;
-
 		--uart_rx
 		rx_data : in std_logic_vector(7 downto 0);
 		rx_new : in std_logic;
-
 		-- History
 		pc_zeile : out hzeile;
 		pc_spalte : out hspalte;
@@ -37,7 +33,7 @@ architecture beh of pc_communication is
 	signal tx_done_i, tx_done_i_next : std_logic;
 	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-	type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+	type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
 		NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
 		PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
 		PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
@@ -72,7 +68,7 @@ begin
 	end process sync;
 
 	process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
-			pc_done)
+			pc_done, rx_data)
 		variable tmp : std_logic_vector(6 downto 0);
 	begin
 		get_next <= '0';
@@ -84,8 +80,7 @@ begin
 		state_next <= state;
 		case state is
 			when IDLE =>
---				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
-				if (rx_new = '1') or btn_a = '0' then
+				if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
 					state_next <= PRINT_NO0_WAIT;
 				end if;
 
@@ -161,22 +156,21 @@ begin
 			when FORWARD =>
 				tx_data_i_next <= pc_char;
 				new_i_next <= '1';
-				-- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
-				get_next <= '1';
-				state_next <= WAIT_UART;
-			when WAIT_UART =>
-				new_i_next <= '1';
+				-- halte pc_get weiterhin high sodass pc_char garantiert
+				-- gleicht bleibt (blockiert history!)
 				get_next <= '1';
 				if tx_done_i = '1' then
 					state_next <= UART_DONE;
 				end if;
 			when UART_DONE =>
-				state_next <= FETCH;
-				spalte_next <= spalte + 1;
-				if spalte = HSPALTE_MAX + 1 then
-					state_next <= NL;
-					spalte_next <= 1;
-					zeile_next <= zeile + 1;
+				if tx_done_i = '0' then
+					state_next <= FETCH;
+					spalte_next <= spalte + 1;
+					if spalte = HSPALTE_MAX + 1 then
+						state_next <= NL;
+						spalte_next <= 1;
+						zeile_next <= zeile + 1;
+					end if;
 				end if;
 			when NL =>
 				tx_data_i_next <= x"0a";
@@ -195,7 +189,7 @@ begin
 			when CR_WAIT =>
 				tmp := std_logic_vector(to_unsigned(zeile,7));
 				if tmp(0) = '0' then
-					-- es handelt sich um eingabe
+					-- es handelt sich um eingabe im naechsten schritt
 					-- => print zeilennummer
 					state_next <= PRINT_NO0_WAIT;
 				else