X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fpc_communication.vhd;fp=src%2Fpc_communication.vhd;h=c422ed7ade9d9dfb9cecf4992c4c674ab90ec9b1;hp=b593b33a1a01f318a953bc33863fe0bc29c4f51b;hb=5198223f6d43e915eed4be1d0bbbbc7f908ef6b1;hpb=b42b2b9d669e1d12db43c70704b4657901d1ab02

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index b593b33..c422ed7 100644
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -24,26 +24,22 @@ entity pc_communication is
 		pc_zeile : out hzeile;
 		pc_spalte : out hspalte;
 		pc_get :  out std_logic;
-		pc_busy : in std_logic; --signals if the history module actually grants our request.
 		pc_done : in std_logic;
 		pc_char : in hbyte
 	);
 end entity pc_communication;
 
 architecture beh of pc_communication is
-	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 1;
-	signal zeile , zeile_next : integer range 1 to HZEILE_MAX + 1;
+	signal spalte, spalte_next : integer range 1 to HSPALTE_MAX + 2;
+	signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
 	signal get, get_next : std_logic;
 	signal new_i, new_i_next : std_logic;
 	signal tx_done_i, tx_done_i_next : std_logic;
 	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
-	type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
+	type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CALC_VAL);
 	signal state, state_next : STATE_PC ;
-
 begin
-
-
 	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
 	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
 	pc_get <= get;
@@ -56,10 +52,10 @@ begin
 		if sys_res_n = '0' then
 			state <= IDLE;
 			spalte <= 1;
-			zeile <= 1;
+			zeile <= 0;
 			get <= '0';
 			new_i <= '0';
-			tx_data_i <= "00000000";
+			tx_data_i <= x"00";
 			tx_done_i <= '0';
 		elsif rising_edge(sys_clk) then
 			spalte <= spalte_next;
@@ -86,28 +82,34 @@ begin
 				null;
 			when FETCH =>
 				get_next <= '1';
-			when WAIT_HIST =>
-				tx_data_i_next <= pc_char;
 			when FORWARD =>
+				tx_data_i_next <= pc_char;
 				new_i_next <= '1';
+				-- halte pc_get weiterhin high sodass pc_char garantiert gleich bleibt
+				get_next <= '1';
 			when WAIT_UART =>
 				new_i_next <= '1';
-			when UART_DONE =>
-				if tx_data_i = x"00" or spalte = HSPALTE_MAX then
+				get_next <= '1';
+			when UART_DONE => null;
+				-- get_next <= '0';
+				-- new_i_next <= '0';
+			when CALC_VAL =>
+				spalte_next <= spalte + 1;
+				if spalte = HSPALTE_MAX + 1 then
 					tx_data_i_next <= x"0a";
-					zeile_next <= zeile + 1;
+					new_i_next <= '1';
+
 					spalte_next <= 1;
-					if zeile = HZEILE_MAX then
-						zeile_next <= 1;
+					zeile_next <= zeile + 1;
+					if zeile = HZEILE_MAX-1 then
+						zeile_next <= 0;
 					end if;
-				else
-					spalte_next <= spalte + 1;
 				end if;
 		end case;
 	end process output_pc;
 
-	next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
-		state, tx_data_i ,tx_done_i, zeile)
+	next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+		tx_data_i ,tx_done_i, zeile, pc_char)
 	begin
 		state_next <= state;
 		case state is
@@ -117,14 +119,12 @@ begin
 					state_next <= FETCH;
 				end if;
 			when FETCH =>
-				if pc_busy = '1' then
-					state_next <= WAIT_HIST;
-				else
-					state_next <= FETCH;
-				end if;
-			when WAIT_HIST =>
-				if (pc_done = '1') then
-					state_next <= FORWARD;
+				if pc_done = '1' and tx_done_i = '0' then
+					if pc_char = x"00" then
+						state_next <= UART_DONE;
+					else
+						state_next <= FORWARD;
+					end if;
 				end if;
 			when FORWARD =>
 				state_next <= WAIT_UART;
@@ -133,13 +133,13 @@ begin
 					state_next <= UART_DONE;
 				end if;
 			when UART_DONE =>
-				if (tx_data_i = x"00" or spalte = HSPALTE_MAX) and
-					zeile = HZEILE_MAX then
+				state_next <= CALC_VAL;
+			when CALC_VAL =>
+				if spalte = HSPALTE_MAX + 1 and zeile = HZEILE_MAX - 1 then
 					state_next <= IDLE;
 				else
 					state_next <= FETCH;
 				end if;
 		end case;
 	end process next_state_pc;
-
 end architecture beh;