X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fhistory.vhd;h=0c918687d73c07d569e9ef03b9cf7793042d9cf0;hp=ca9800f1dd5140b7307e936523f460a52fd30e67;hb=HEAD;hpb=9f86188ebcedaf3cc7a7106b0a8d6a96493d41bc diff --git a/src/history.vhd b/src/history.vhd index ca9800f..0c91868 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -8,7 +8,11 @@ entity history is sys_clk : in std_logic; sys_res_n : in std_logic; -- PC-komm - -- TODO: pins + pc_get : in std_logic; + pc_spalte : in hspalte; + pc_zeile : in hzeile; + pc_char : out hbyte; + pc_done : out std_logic; -- Scanner s_char : in hbyte; s_take : in std_logic; @@ -24,17 +28,20 @@ entity history is d_done : out std_logic; d_char : out hbyte; -- Parser - -- TODO: pins - - -- TODO: tmp only! - do_it : in std_logic; - finished : out std_logic + p_rget : in std_logic; + p_rdone : out std_logic; + p_read : out hbyte; + p_wtake : in std_logic; + p_wdone : out std_logic; + p_write : in hbyte; + p_finished : in std_logic ); end entity history; architecture beh of history is type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN, - S_D_INIT, S_D_READ, S_S_FIN_POSUP); + S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE, + S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ); signal state_int, state_next : HISTORY_STATE; signal was_bs_int, was_bs_next : std_logic; signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -45,8 +52,13 @@ architecture beh of history is signal d_new_bs_int, d_new_bs_next: std_logic; signal d_done_int, d_done_next : std_logic; signal d_char_int, d_char_next : hbyte; - - signal finished_int, finished_next : std_logic; + signal p_rdone_int, p_rdone_next : std_logic; + signal p_wdone_int, p_wdone_next : std_logic; + signal p_read_int, p_read_next : hbyte; + signal p_sp_read_int, p_sp_read_next : hspalte; + signal p_sp_write_int, p_sp_write_next : hspalte; + signal pc_char_next ,pc_char_int : hbyte; + signal pc_done_next, pc_done_int : std_logic; -- ram signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0); @@ -59,14 +71,17 @@ begin d_new_bs <= d_new_bs_int; d_done <= d_done_int; d_char <= d_char_int; - - finished <= finished_int; + p_rdone <= p_rdone_int; + p_wdone <= p_wdone_int; + p_read <= p_read_int; + pc_done <= pc_done_int; + pc_char <= pc_char_int; process(sys_clk, sys_res_n) begin if sys_res_n = '0' then -- internal - state_int <= SIDLE; + state_int <= S_INIT; was_bs_int <= '0'; pos_int <= (others => '0'); -- out @@ -77,8 +92,14 @@ begin d_new_bs_int <= '0'; d_done_int <= '0'; d_char_int <= (others => '0'); + p_rdone_int <= '0'; + p_wdone_int <= '0'; + p_read_int <= (others => '0'); + p_sp_read_int <= (others => '0'); + p_sp_write_int <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_int'length)); - finished_int <= '0'; + pc_char_int <= (others => '0'); + pc_done_int <= '0'; address_int <= (0 => '1', others => '0'); data_in_int <= x"00"; @@ -96,8 +117,14 @@ begin d_new_bs_int <= d_new_bs_next; d_done_int <= d_done_next; d_char_int <= d_char_next; + p_rdone_int <= p_rdone_next; + p_wdone_int <= p_wdone_next; + p_read_int <= p_read_next; + p_sp_read_int <= p_sp_read_next; + p_sp_write_int <= p_sp_write_next; - finished_int <= finished_next; + pc_char_int <= pc_char_next; + pc_done_int <= pc_done_next; address_int <= address_next; data_in_int <= data_in_next; @@ -106,19 +133,32 @@ begin end process; -- next state - process(state_int, d_get, do_it, s_take, s_backspace, was_bs_int) + process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int, + p_rget, p_wtake, pos_int, s_cnt_int) begin state_next <= state_int; case state_int is + when S_INIT => + -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt + -- noetig, aber spaetestens fuers dumpen per rs232 + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then + state_next <= SIDLE; + end if; when SIDLE => -- S_S_FIN: tmp.. if s_take = '1' then state_next <= S_S_INIT; - elsif do_it = '1' then + elsif p_rget = '1' then + state_next <= S_P_READ; + elsif p_wtake = '1' then + state_next <= S_P_WRITE; + elsif p_finished = '1' then state_next <= S_S_FIN; elsif d_get = '1' then state_next <= S_D_INIT; + elsif pc_get = '1' then + state_next <= S_PC_INIT; end if; when S_S_INIT => if s_backspace = '1' then @@ -131,11 +171,19 @@ begin when S_S_BS => state_next <= S_S_DONE; when S_S_FIN => - if do_it = '0' then + if p_finished = '0' then state_next <= S_S_FIN_POSUP; end if; when S_S_FIN_POSUP => - state_next <= SIDLE; + state_next <= S_S_CLEAR_NEXT0; + when S_S_CLEAR_NEXT0 => + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then + state_next <= S_S_CLEAR_NEXT1; + end if; + when S_S_CLEAR_NEXT1 => + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then + state_next <= SIDLE; + end if; when S_S_DONE => if s_take = '0' then state_next <= SIDLE; @@ -147,14 +195,36 @@ begin if d_get = '0' then state_next <= SIDLE; end if; + when S_PC_INIT => + state_next <= S_PC_READ; + when S_PC_READ => + if pc_get = '0' then + state_next <= SIDLE; + end if; + when S_P_READ => + state_next <= S_P_READ_DONE; + when S_P_READ_DONE => + if p_rget = '0' then + state_next <= S_P_DONE; + end if; + when S_P_WRITE => + state_next <= S_P_WRITE_DONE; + when S_P_WRITE_DONE => + if p_wtake = '0' then + state_next <= S_P_DONE; + end if; + when S_P_DONE => + state_next <= SIDLE; end case; end process; -- out process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int, - data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int, - was_bs_int, s_take, pos_int) + data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int, + was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int, + p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte) variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0); + variable spalte_tmp : hspalte; variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0); begin s_done_next <= '0'; @@ -166,21 +236,35 @@ begin d_new_bs_next <= '0'; d_done_next <= '0'; d_char_next <= (others => '0'); - finished_next <= '0'; wr_next <= '0'; address_next <= address_int; data_in_next <= data_in_int; + pc_done_next <= '0'; + pc_char_next <= pc_char_int; + p_rdone_next <= p_rdone_int; + p_wdone_next <= p_wdone_int; + p_read_next <= p_read_int; + p_sp_read_next <= p_sp_read_int; + p_sp_write_next <= p_sp_write_int; case state_int is + when S_INIT => + wr_next <= '1'; + address_next <= pos_int; + data_in_next <= (others => '0'); + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then + pos_next <= (others => '0'); + else + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH)); + end if; when SIDLE => - -- TODO: tmp fix d_new_result_next <= '0'; when S_S_INIT => null; when S_S_WRITE => - -- nur bei < 71 weiter machen - -- TODO: '/=' billiger als '<' ? - if unsigned(s_cnt_int) /= 71 then + -- nur bei < HSPALTE_MAX weiter machen + -- Hint: '/=' billiger als '<' + if unsigned(s_cnt_int) /= HSPALTE_MAX then wr_next <= '1'; address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); data_in_next <= s_char; @@ -199,18 +283,43 @@ begin addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int; end if; s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0); - wr_next <= '1'; address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp)); data_in_next <= (others => '0'); was_bs_next <= '1'; when S_S_FIN => - finished_next <= '1'; s_cnt_next <= (0 => '1', others => '0'); d_new_result_next <= '1'; + -- resetten der parser counter + p_sp_read_next <= (others => '0'); + p_sp_write_next <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_next'length)); when S_S_FIN_POSUP => - -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen - pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); + -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen + if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then + pos_next <= (others => '0'); + else + pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH)); + end if; + when S_S_CLEAR_NEXT0 => + -- die naechsten 142 bytes im speicher resetten + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int)); + data_in_next <= (others => '0'); + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then + s_cnt_next <= (0 => '1', others => '0'); + else + s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); + end if; + when S_S_CLEAR_NEXT1 => + -- die naechsten 142 bytes im speicher resetten + wr_next <= '1'; + address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(s_cnt_int)); + data_in_next <= (others => '0'); + if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then + s_cnt_next <= (0 => '1', others => '0'); + else + s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1); + end if; when S_S_DONE => s_done_next <= '1'; if was_bs_int = '0' then @@ -223,7 +332,7 @@ begin when S_D_INIT => addr_tmp := (others => '0'); addr_tmp(hzeile'length - 1 downto 0) := d_zeile; - mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH)); + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte)); address_next <= addr_tmp; @@ -232,10 +341,42 @@ begin when S_D_READ => d_char_next <= data_out; d_done_next <= '1'; + + when S_PC_INIT => + addr_tmp := (others => '0'); + addr_tmp(hzeile'length - 1 downto 0) := pc_zeile; + mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH)); + addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0); + addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte)); + address_next <= addr_tmp; + when S_PC_READ => + pc_done_next <= '1'; + pc_char_next <= data_out; + + when S_P_READ => + wr_next <= '0'; + spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1); + p_sp_read_next <= spalte_tmp; + address_next <= std_logic_vector(unsigned(pos_int) + unsigned(spalte_tmp)); + when S_P_READ_DONE => + p_rdone_next <= '1'; + p_read_next <= data_out; + + when S_P_WRITE => + wr_next <= '1'; + data_in_next <= p_write; + spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1); + p_sp_write_next <= spalte_tmp; + address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(spalte_tmp)); + when S_P_WRITE_DONE => + p_wdone_next <= '1'; + when S_P_DONE => + p_rdone_next <= '0'; + p_wdone_next <= '0'; end case; end process; - sp_ram_inst : entity work.sp_ram(beh) + sp_ram_inst : sp_ram generic map ( ADDR_WIDTH => H_RAM_WIDTH )