X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fgen_pkg.vhd;fp=src%2Fgen_pkg.vhd;h=922911cb73134904fd0fd207c6c7b47715fcd5d9;hp=f8a2963d90405aea55fe3bd4271915482288685a;hb=51361c5dc1ab06332a04260f5192adcb398238e6;hpb=a1b9896ecd59e16ef6c28bc6990eadd6e0c515c8

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index f8a2963..922911c 100644
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -73,6 +73,196 @@ package gen_pkg is
 	constant SC_ENTER : hbyte := x"5a";
 	constant SC_BKSP : hbyte := x"66";
 	constant SC_SPACE : hbyte := x"29";
+
+	-- components...
+	component alu is
+		port (
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			opcode : in alu_ops;
+			op1 : in csigned;
+			op2 : in csigned;
+			op3 : out csigned;
+			opM : out csigned;
+			do_calc : in std_logic;
+			calc_done : out std_logic;
+			calc_error : out std_logic
+		);
+	end component alu;
+
+	component parser is
+		port (
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			-- History
+			p_rget : out std_logic;
+			p_rdone : in std_logic;
+			p_read : in hbyte;
+			p_wtake : out std_logic;
+			p_wdone : in std_logic;
+			p_write : out hbyte;
+			p_finished : out std_logic;
+			-- Scanner
+			do_it : in std_logic;
+			finished : out std_logic
+		);
+	end component parser;
+
+	component scanner is
+		port
+		(
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			-- PS/2
+			new_data : in std_logic;
+			data : in std_logic_vector(7 downto 0);
+			-- History
+			s_char : out hbyte;
+			s_take : out std_logic;
+			s_done : in std_logic;
+			s_backspace : out std_logic;
+			-- Parser
+			do_it : out std_logic;
+			finished : in std_logic
+		);
+	end component scanner;
+
+	component history is
+		port (
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			-- PC-komm
+			pc_get :  in std_logic;
+			pc_spalte : in hspalte;
+			pc_zeile : in hzeile;
+			pc_char : out hbyte;
+			pc_done : out std_logic;
+			-- Scanner
+			s_char : in hbyte;
+			s_take : in std_logic;
+			s_done : out std_logic;
+			s_backspace : in std_logic;
+			-- Display
+			d_new_eingabe : out std_logic;
+			d_new_result : out std_logic;
+			d_new_bs : out std_logic;
+			d_zeile : in hzeile;
+			d_spalte : in hspalte;
+			d_get : in std_logic;
+			d_done : out std_logic;
+			d_char : out hbyte;
+			-- Parser
+			p_rget : in std_logic;
+			p_rdone : out std_logic;
+			p_read : out hbyte;
+			p_wtake : in std_logic;
+			p_wdone : out std_logic;
+			p_write : in hbyte;
+			p_finished : in std_logic
+		);
+	end component history;
+
+	component display is
+		port (
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			-- History
+			d_new_eingabe : in std_logic;
+			d_new_result : in std_logic;
+			d_new_bs : in std_logic;
+			d_zeile : out hzeile;
+			d_spalte : out hspalte;
+			d_get : out std_logic;
+			d_done : in std_logic;
+			d_char : in hbyte;
+			-- VGA
+			command : out std_logic_vector(7 downto 0);
+			command_data : out std_logic_vector(31 downto 0);
+			free : in std_logic
+		);
+	end component display;
+
+	component pc_communication is
+		port (
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+
+			--button
+			btn_a : in std_logic;
+
+			--uart_tx
+			tx_data : out std_logic_vector(7 downto 0);
+			tx_new : out std_logic;
+			tx_done : in std_logic;
+
+			--uart_rx
+			rx_data : in std_logic_vector(7 downto 0);
+			rx_new : in std_logic;
+
+			-- History
+			pc_zeile : out hzeile;
+			pc_spalte : out hspalte;
+			pc_get :  out std_logic;
+			pc_done : in std_logic;
+			pc_char : in hbyte
+		);
+	end component pc_communication;
+
+	component uart_rx is
+		generic (
+			CLK_FREQ : integer := 33000000;
+			BAUDRATE : integer := 115200
+		);
+		port(
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			rxd : in std_logic;
+			rx_data : out std_logic_vector(7 downto 0);
+			rx_new : out std_logic
+		);
+	end component uart_rx;
+
+	component uart_tx is
+		generic (
+			CLK_FREQ : integer := 33000000;
+			BAUDRATE : integer := 115200
+		);
+		port(
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			txd : out std_logic;
+			tx_data : in std_logic_vector(7 downto 0);
+			tx_new : in std_logic;
+			tx_done : out std_logic
+		);
+	end component uart_tx;
+
+	component vpll IS
+		port (
+			inclk0 : in std_logic := '0';
+			c0 : out std_logic 
+		);
+	end component vpll;
+	
+	component clk_vga_s3e is
+		port (
+			clk50 : in std_logic;
+			clk25 : out std_logic
+		);
+	end component clk_vga_s3e;
+
+	component sp_ram is
+		generic (
+			ADDR_WIDTH : integer range 1 to integer'high
+		);
+		port (
+			sys_clk : in std_logic;
+			address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+			data_out : out hbyte;
+			wr : in std_logic;
+			data_in : in hbyte
+		);
+	end component sp_ram;
 end package gen_pkg;
 
 package body gen_pkg is