X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fbeh_scanner_tb.vhd;h=d9b7bb4610d4942cf4ee31cca788896c29e9cdf3;hp=d3cfe69fa864b9370bceaa1475906cfaf2b468be;hb=HEAD;hpb=84b6ef65190dbb25538b87572d2b2312ee447107

diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd
index d3cfe69..d9b7bb4 100644
--- a/src/beh_scanner_tb.vhd
+++ b/src/beh_scanner_tb.vhd
@@ -21,7 +21,7 @@ architecture sim of beh_scanner_tb is
 
 	signal stop : boolean := false;
 begin
-	inst : entity work.scanner(beh)
+	inst : scanner
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -81,7 +81,7 @@ begin
 			f1_loop : while not endfile(f) loop
 				readline (f, l);
 				input := (others => nul);
-				if (l'length <= 72) then
+				if (l'length <= HSPALTE_MAX+1) then
 					input(1 to l'length) := l.all;
 					if (input(1) = '#') then
 						next f1_loop;
@@ -97,7 +97,7 @@ begin
 			f2_loop : while not endfile(f) loop
 				readline (f, l);
 				expectedresult := (others => nul);
-				if (l'length <= 72) then
+				if (l'length <= HSPALTE_MAX+1) then
 					expectedresult(1 to l'length) := l.all;
 					if (expectedresult(1) = '#') then
 						next f2_loop;