X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=hwmod.git;a=blobdiff_plain;f=src%2Fbeh_pc_communication_tb.vhd;h=aa921e2dfc93bab00051a9a51a84fa4b83cb4f3a;hp=63ba7cc6a076981d194c1112da2d2f1244dbb7c2;hb=HEAD;hpb=93155b7836692298643a4f0a89663e3850067407

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 63ba7cc..aa921e2 100644
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -21,16 +21,16 @@ architecture sim of beh_pc_communication_tb is
 		signal tx_new : std_logic;
 		signal tx_done : std_logic;
 		signal rx_new : std_logic;
-		signal d_get : std_logic;
-		signal d_done : std_logic;
+		signal pc_get : std_logic;
+		signal pc_done : std_logic;
 		signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
-		signal d_zeile : hzeile;
-		signal d_spalte : hspalte;
-		signal d_char : hbyte;
+		signal pc_zeile : hzeile;
+		signal pc_spalte : hspalte;
+		signal pc_char : hbyte;
 begin
-	-- display
-	inst : entity work.pc_communication(beh)
+	-- pc_communication
+	inst : pc_communication
 	port map (
 		sys_clk => sys_clk,
 		sys_res_n => sys_res_n,
@@ -48,11 +48,11 @@ begin
 		rx_new => rx_new,
 
 		-- History
-		d_zeile => d_zeile,
-		d_spalte => d_spalte,
-		d_get => d_get,
-		d_done => d_done,
-		d_char => d_char
+		pc_zeile => pc_zeile,
+		pc_spalte => pc_spalte,
+		pc_get => pc_get,
+		pc_done => pc_done,
+		pc_char => pc_char
 	);
 
 	clk : process
@@ -65,30 +65,30 @@ begin
 
 	stub_history : process
 		file f : text open read_mode is "../../src/pc_communication.test";
-		--variable rb : hbyte;
 		variable rb : character;
 		variable good : boolean;
 		variable i : integer;
 		variable buf : my_string;
 		variable l : line;
 	begin
-		--take control of the situation.
-		d_char <= (others => '0');
+		pc_char <= (others => '0');
+		pc_done <= '0';
 		wait until sys_res_n = '1';
 
 		while not endfile (f) loop
 			readline(f, l);
+			buf := l.all;
 			i := 1;
 			while i < l'length loop
-				wait until rising_edge(d_get);
-				d_done <= '0';
-				d_char <= (others => '0');
-				wait for 90 ns;
-
-				d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
-				d_done <= '1';
+				pc_done <= '0';
+				wait until rising_edge(pc_get);
+				wait for 150 ns;
+				pc_char <= (others => '0');
+				wait for 30 ns;
+				pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+				i := i + 1;
+				pc_done <= '1';
 				wait for 30 ns;
-				
 			end loop;
 		end loop;
 
@@ -97,9 +97,10 @@ begin
 
 	stub_uart : process
 	begin
+		tx_done <= '0';
+		wait until sys_res_n = '1';
 		while true loop
 			tx_done <= '0';
-			wait until sys_res_n = '1';
 			wait until rising_edge(tx_new);
 			wait for 300 ns;
 			tx_done <= '1';
@@ -112,19 +113,16 @@ begin
 		-- init & reset
 		-- we only simulate pressing of button a by now!
 		sys_res_n <= '0';
-		btn_a <= '0';
-		tx_data <= ( others => '0');
+		btn_a <= '1';
 		rx_data <= ( others => '0');
-		d_zeile <= ( others => '0');
-		d_spalte <= ( others => '0');
 		rx_new <= '0';
 		
 		wait for 90 ns;
 		sys_res_n <= '1';
 		wait for 30 ns;
-		btn_a <= '1';
-		wait for 15 ns;
 		btn_a <= '0';
+		wait for 30 ns;
+		btn_a <= '1';
 		wait;
 		--wait for 1000 ns;
 		--assert false report "test beendet" severity failure;