uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / uart_tx.vhd

diff --git a/src/uart_tx.vhd b/src/uart_tx.vhd
index 4c97578484e6d47899ae927bf4d12e2d3f7541a3..a851656f02618a636ab8bfa915f43df8fcbf3a83 100644 (file)
--- a/src/uart_tx.vhd
+++ b/src/uart_tx.vhd
@@ -1,12 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---use work.gen_pkg.all;
-
---package int_types is
---     type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE);
---     type PARITY_TYPE is (ODD, EVEN, NONE);
---end package int_types;
+use work.gen_pkg.all;
 
 entity uart_tx is
        generic (
@@ -31,8 +26,8 @@ architecture beh of uart_tx is
 
        signal txd_next, txd_int : std_logic;
        signal tx_done_next, tx_done_int : std_logic;
-       signal tx_to_send : std_logic_vector(0 to 10);
-       signal bitcnt_int, bitcnt_next : integer range 0 to 10;
+       signal tx_to_send : std_logic_vector(10 downto 0);
+       signal bitcnt_int, bitcnt_next : integer range 0 to 11;
        signal baudcnt_int, baudcnt_next : integer range 0 to BAUD;
 begin
        txd <= txd_int;
@@ -53,13 +48,13 @@ begin
                        tx_done_int <= tx_done_next;
                        bitcnt_int <= bitcnt_next;
                        baudcnt_int <= baudcnt_next;
-                       -- HIGHBIT (1) | STARTBIT (1) | DATA (8) | STOPBIT (1)
-                       -- TODO: passt das wegen der endianess?
-                       tx_to_send <= '1' & '0' & tx_data & '1';
+                       -- STOPBIT (1) | DATA (8) | STARTBIT (1) | HIGHBIT (1)
+                       tx_to_send <= '1' & tx_data & '0' & '1';
                end if;
        end process;
 
-       process(tx_new, tx_to_send, state_int, bitcnt_int, baudcnt_int)
+       process(tx_new, tx_to_send, state_int, bitcnt_int, baudcnt_int,
+               tx_done_int, txd_int)
        begin
                state_next <= state_int;
                tx_done_next <= tx_done_int;