uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / scanner.vhd

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 9e1f0bde5b9e8e28fc8e657d587980fa3d0dd2a9..1710dc437888bae405c9fe804fcf1827ae4f450d 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -23,7 +23,7 @@ entity scanner is
 end entity scanner;
 
 architecture beh of scanner is
-       type SCANNER_STATE is (SIDLE, SREAD, SMOD, STAKE, SDEL, SENTER);
+       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER);
        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
@@ -63,30 +63,42 @@ begin
 
                case state_int is
                        when SIDLE =>
-                               if new_data = '1' and finished = '0' and s_done = '0' then
-                                       state_next <= SREAD;
+                               if new_data = '1' then
+                                       case data is
+                                               when x"f0" =>
+                                                       state_next <= SIGNORE_NEXT;
+                                               when x"e0" =>
+                                                       state_next <= SREAD_NEXT;
+                                               when SC_BKSP =>
+                                                       state_next <= SDEL;
+                                               when SC_ENTER =>
+                                                       state_next <= SENTER;
+                                               when SC_KP_0 | SC_KP_1 | SC_KP_2 |
+                                                       SC_KP_3 | SC_KP_4 | SC_KP_5 | SC_KP_6 |
+                                                       SC_KP_7 | SC_KP_8 | SC_KP_9 |
+                                                       SC_0 | SC_1 | SC_2 | SC_3 | SC_4 |
+                                                       SC_5 | SC_6 | SC_7 | SC_8 | SC_9 |
+                                                       SC_PLUS | SC_KP_PLUS |
+                                                       SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
+                                                               state_next <= STAKE;
+                                               when others => state_next <= SIDLE;
+                                       end case;
                                end if;
-                       when SREAD =>
-                               case data is
-                                       when x"e0" => state_next <= SMOD;
-                                       when SC_BKSP => state_next <= SDEL;
-                                       when SC_ENTER => state_next <= SENTER;
-                                       when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
-                                               SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
-                                               SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
-                                               SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
-                                                       state_next <= STAKE;
-                                       when others => state_next <= SIDLE;
-                               end case;
-                       when SMOD =>
+                       when SIGNORE_NEXT =>
                                if new_data = '1' then
-                                       if data = SC_KP_ENTER then
-                                               state_next <= SENTER;
-                                       elsif data = SC_KP_DIV then
-                                               state_next <= STAKE;
-                                       else
-                                               state_next <= SIDLE;
-                                       end if;
+                                       state_next <= SIDLE;
+                               end if;
+                       when SREAD_NEXT =>
+                               if new_data = '1' then
+                                       case data is
+                                               when x"f0" =>
+                                                       state_next <= SIGNORE_NEXT;
+                                               when SC_ENTER =>
+                                                       state_next <= SENTER;
+                                               when SC_KP_DIV =>
+                                                       state_next <= STAKE;
+                                               when others => state_next <= SIDLE;
+                                       end case;
                                end if;
                        when STAKE | SDEL=>
                                if s_done = '1' then
@@ -100,22 +112,22 @@ begin
        end process;
 
        -- out
-       process(state_int, data)
+       process(state_int, data, s_char_int, new_data)
                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin
                        case x is
-                               when SC_KP_0 => y := x"30";
-                               when SC_KP_1 => y := x"31";
-                               when SC_KP_2 => y := x"32";
-                               when SC_KP_3 => y := x"33";
-                               when SC_KP_4 => y := x"34";
-                               when SC_KP_5 => y := x"35";
-                               when SC_KP_6 => y := x"36";
-                               when SC_KP_7 => y := x"37";
-                               when SC_KP_8 => y := x"38";
-                               when SC_KP_9 => y := x"39";
-                               when SC_KP_PLUS => y := x"2b";
+                               when SC_KP_0 | SC_0 => y := x"30";
+                               when SC_KP_1 | SC_1 => y := x"31";
+                               when SC_KP_2 | SC_2 => y := x"32";
+                               when SC_KP_3 | SC_3 => y := x"33";
+                               when SC_KP_4 | SC_4 => y := x"34";
+                               when SC_KP_5 | SC_5 => y := x"35";
+                               when SC_KP_6 | SC_6 => y := x"36";
+                               when SC_KP_7 | SC_7 => y := x"37";
+                               when SC_KP_8 | SC_8 => y := x"38";
+                               when SC_KP_9 | SC_9 => y := x"39";
+                               when SC_KP_PLUS | SC_PLUS => y := x"2b";
                                when SC_KP_MINUS => y := x"2d";
                                when SC_KP_MUL => y := x"2a";
                                when SC_KP_DIV => y := x"2f";
@@ -125,18 +137,15 @@ begin
                        return y;
                end function;
        begin
-               s_char_next <= (others => '0');
+               s_char_next <= s_char_int;
                s_take_next <= '0';
                s_backspace_next <= '0';
                do_it_next <= '0';
 
                case state_int is
-                       when SIDLE =>
-                               null;
-                       when SREAD =>
-                               null;
-                       when SMOD =>
-                               null;
+                       when SIDLE => null;
+                       when SIGNORE_NEXT => null;
+                       when SREAD_NEXT => null;
                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));